Merge "disp: msm: sde: add rev check for shima target"

This commit is contained in:
qctecmdr
2020-07-14 09:50:09 -07:00
committad av Gerrit - the friendly Code Review server
förälder 8c127fd44f bb7d5f490f
incheckning 5e96ba152b
4 ändrade filer med 58 tillägg och 1 borttagningar

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@@ -4739,6 +4739,43 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
sde_cfg->dither_luma_mode_support = true;
sde_cfg->mdss_hw_block_size = 0x158;
sde_cfg->has_trusted_vm_support = true;
} else if (IS_HOLI_TARGET(hw_rev)) {
sde_cfg->has_cwb_support = false;
sde_cfg->has_qsync = true;
sde_cfg->perf.min_prefill_lines = 24;
sde_cfg->vbif_qos_nlvl = 8;
sde_cfg->ts_prefill_rev = 2;
sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
sde_cfg->delay_prg_fetch_start = true;
sde_cfg->sui_ns_allowed = true;
sde_cfg->sui_misr_supported = true;
sde_cfg->sui_block_xin_mask = 0xC01;
sde_cfg->has_hdr = false;
sde_cfg->has_sui_blendstage = true;
sde_cfg->vbif_disable_inner_outer_shareable = true;
sde_cfg->mdss_hw_block_size = 0x158;
} else if (IS_SHIMA_TARGET(hw_rev)) {
sde_cfg->has_cwb_support = true;
sde_cfg->has_wb_ubwc = true;
sde_cfg->has_qsync = true;
sde_cfg->perf.min_prefill_lines = 35;
sde_cfg->vbif_qos_nlvl = 8;
sde_cfg->ts_prefill_rev = 2;
sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
sde_cfg->delay_prg_fetch_start = true;
sde_cfg->sui_ns_allowed = true;
sde_cfg->sui_misr_supported = true;
sde_cfg->sui_block_xin_mask = 0xE71;
sde_cfg->has_sui_blendstage = true;
sde_cfg->has_3d_merge_reset = true;
sde_cfg->has_hdr = true;
sde_cfg->has_hdr_plus = true;
set_bit(SDE_MDP_DHDR_MEMPOOL, &sde_cfg->mdp[0].features);
sde_cfg->has_vig_p010 = true;
sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_1_0_0;
sde_cfg->inline_disable_const_clr = true;
sde_cfg->vbif_disable_inner_outer_shareable = true;
sde_cfg->mdss_hw_block_size = 0x158;
} else {
SDE_ERROR("unsupported chipset id:%X\n", hw_rev);
sde_cfg->perf.min_prefill_lines = 0xffff;