qcacmn: Add hal_rx_is_unicast API
Implement hal_rx_is_unicase API based on the chipset as the macro to retrieve is_unicast bit value is chipset dependent. Change-Id: I38807f478c295309adf2a07ce9010b1bc04c734e CRs-Fixed: 2522133
This commit is contained in:

committed by
nshrivas

parent
68d6f0d585
commit
5ddc518b2e
@@ -814,7 +814,7 @@ dp_rx_null_q_desc_handle(struct dp_soc *soc, qdf_nbuf_t nbuf,
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vdev->wds_enabled))
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vdev->wds_enabled))
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dp_rx_wds_srcport_learn(soc, rx_tlv_hdr, peer, nbuf);
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dp_rx_wds_srcport_learn(soc, rx_tlv_hdr, peer, nbuf);
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if (hal_rx_is_unicast(rx_tlv_hdr)) {
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if (hal_rx_is_unicast(soc->hal_soc, rx_tlv_hdr)) {
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tid = hal_rx_tid_get(soc->hal_soc, rx_tlv_hdr);
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tid = hal_rx_tid_get(soc->hal_soc, rx_tlv_hdr);
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if (!peer->rx_tid[tid].hw_qdesc_vaddr_unaligned)
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if (!peer->rx_tid[tid].hw_qdesc_vaddr_unaligned)
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dp_rx_tid_setup_wifi3(peer, tid, 1, IEEE80211_SEQ_MAX);
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dp_rx_tid_setup_wifi3(peer, tid, 1, IEEE80211_SEQ_MAX);
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@@ -405,6 +405,7 @@ struct hal_hw_txrx_ops {
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QDF_STATUS
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QDF_STATUS
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(*hal_rx_mpdu_get_addr4)(uint8_t *buf, uint8_t *mac_addr);
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(*hal_rx_mpdu_get_addr4)(uint8_t *buf, uint8_t *mac_addr);
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uint8_t (*hal_rx_get_mpdu_sequence_control_valid)(uint8_t *buf);
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uint8_t (*hal_rx_get_mpdu_sequence_control_valid)(uint8_t *buf);
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bool (*hal_rx_is_unicast)(uint8_t *buf);
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};
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};
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/**
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/**
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@@ -1216,26 +1216,17 @@ enum hal_rx_mpdu_info_sw_frame_group_id_type {
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/**
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/**
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* hal_rx_is_unicast: check packet is unicast frame or not.
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* hal_rx_is_unicast: check packet is unicast frame or not.
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*
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* @hal_soc_hdl: hal_soc handle
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* @ buf: pointer to rx pkt TLV.
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* @buf: pointer to rx pkt TLV.
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*
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*
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* Return: true on unicast.
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* Return: true on unicast.
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*/
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*/
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static inline bool
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static inline bool
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hal_rx_is_unicast(uint8_t *buf)
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hal_rx_is_unicast(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
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{
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{
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struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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struct rx_mpdu_start *mpdu_start =
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&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
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uint32_t grp_id;
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uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
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grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
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return hal_soc->ops->hal_rx_is_unicast(buf);
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RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)),
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RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK,
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RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB));
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return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
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}
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}
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/**
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/**
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@@ -544,6 +544,29 @@ static uint8_t hal_rx_get_mpdu_sequence_control_valid_6290(uint8_t *buf)
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return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
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return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
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}
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}
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/**
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* hal_rx_is_unicast_6290: check packet is unicast frame or not.
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*
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* @ buf: pointer to rx pkt TLV.
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*
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* Return: true on unicast.
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*/
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static bool hal_rx_is_unicast_6290(uint8_t *buf)
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{
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struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
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struct rx_mpdu_start *mpdu_start =
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&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
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uint32_t grp_id;
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uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
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grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
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RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)),
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RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK,
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RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB));
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return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
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}
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struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
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struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
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/* init and setup */
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/* init and setup */
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hal_srng_dst_hw_init_generic,
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hal_srng_dst_hw_init_generic,
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@@ -606,6 +629,7 @@ struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
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hal_rx_mpdu_get_addr3_6290,
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hal_rx_mpdu_get_addr3_6290,
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hal_rx_mpdu_get_addr4_6290,
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hal_rx_mpdu_get_addr4_6290,
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hal_rx_get_mpdu_sequence_control_valid_6290,
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hal_rx_get_mpdu_sequence_control_valid_6290,
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hal_rx_is_unicast_6290,
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};
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};
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struct hal_hw_srng_config hw_srng_table_6290[] = {
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struct hal_hw_srng_config hw_srng_table_6290[] = {
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@@ -542,6 +542,29 @@ static uint8_t hal_rx_get_mpdu_sequence_control_valid_6390(uint8_t *buf)
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return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
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return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
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}
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}
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/**
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* hal_rx_is_unicast_6390: check packet is unicast frame or not.
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*
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* @ buf: pointer to rx pkt TLV.
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*
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* Return: true on unicast.
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*/
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static bool hal_rx_is_unicast_6390(uint8_t *buf)
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{
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struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
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struct rx_mpdu_start *mpdu_start =
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&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
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uint32_t grp_id;
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uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
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grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
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RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)),
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RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK,
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RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB));
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return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
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}
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struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
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struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
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/* init and setup */
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/* init and setup */
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hal_srng_dst_hw_init_generic,
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hal_srng_dst_hw_init_generic,
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@@ -604,6 +627,7 @@ struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
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hal_rx_mpdu_get_addr3_6390,
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hal_rx_mpdu_get_addr3_6390,
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hal_rx_mpdu_get_addr4_6390,
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hal_rx_mpdu_get_addr4_6390,
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hal_rx_get_mpdu_sequence_control_valid_6390,
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hal_rx_get_mpdu_sequence_control_valid_6390,
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hal_rx_is_unicast_6390,
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};
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};
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struct hal_hw_srng_config hw_srng_table_6390[] = {
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struct hal_hw_srng_config hw_srng_table_6390[] = {
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@@ -448,6 +448,29 @@ static uint8_t hal_rx_get_mpdu_sequence_control_valid_6490(uint8_t *buf)
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return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
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return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
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}
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}
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/**
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* hal_rx_is_unicast_6490: check packet is unicast frame or not.
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*
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* @ buf: pointer to rx pkt TLV.
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*
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* Return: true on unicast.
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*/
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static bool hal_rx_is_unicast_6490(uint8_t *buf)
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{
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struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
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struct rx_mpdu_start *mpdu_start =
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&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
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uint32_t grp_id;
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uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
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grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
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RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)),
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RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK,
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RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB));
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return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
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}
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struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
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struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
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/* rx */
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/* rx */
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hal_rx_get_rx_fragment_number_6490,
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hal_rx_get_rx_fragment_number_6490,
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@@ -470,4 +493,5 @@ struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
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hal_rx_mpdu_get_addr3_6490,
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hal_rx_mpdu_get_addr3_6490,
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hal_rx_mpdu_get_addr4_6490,
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hal_rx_mpdu_get_addr4_6490,
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hal_rx_get_mpdu_sequence_control_valid_6490,
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hal_rx_get_mpdu_sequence_control_valid_6490,
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hal_rx_is_unicast_6490,
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};
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};
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@@ -539,6 +539,29 @@ static uint8_t hal_rx_get_mpdu_sequence_control_valid_8074v1(uint8_t *buf)
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return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
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return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
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}
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}
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/**
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* hal_rx_is_unicast_8074v1: check packet is unicast frame or not.
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*
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* @ buf: pointer to rx pkt TLV.
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*
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* Return: true on unicast.
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*/
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static bool hal_rx_is_unicast_8074v1(uint8_t *buf)
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{
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struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
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struct rx_mpdu_start *mpdu_start =
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&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
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uint32_t grp_id;
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uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
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grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
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RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)),
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RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK,
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RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB));
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return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
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}
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struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
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struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
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/* init and setup */
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/* init and setup */
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@@ -602,6 +625,7 @@ struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
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hal_rx_mpdu_get_addr3_8074v1,
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hal_rx_mpdu_get_addr3_8074v1,
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hal_rx_mpdu_get_addr4_8074v1,
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hal_rx_mpdu_get_addr4_8074v1,
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hal_rx_get_mpdu_sequence_control_valid_8074v1,
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hal_rx_get_mpdu_sequence_control_valid_8074v1,
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hal_rx_is_unicast_8074v1,
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};
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};
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struct hal_hw_srng_config hw_srng_table_8074[] = {
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struct hal_hw_srng_config hw_srng_table_8074[] = {
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@@ -536,6 +536,29 @@ static uint8_t hal_rx_get_mpdu_sequence_control_valid_8074v2(uint8_t *buf)
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return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
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return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
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}
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}
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/**
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* hal_rx_is_unicast_8074v2: check packet is unicast frame or not.
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*
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* @ buf: pointer to rx pkt TLV.
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*
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* Return: true on unicast.
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*/
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static bool hal_rx_is_unicast_8074v2(uint8_t *buf)
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{
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struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
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struct rx_mpdu_start *mpdu_start =
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&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
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uint32_t grp_id;
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uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
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grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
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RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)),
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RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK,
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RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB));
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return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
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}
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struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
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struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
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/* init and setup */
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/* init and setup */
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@@ -599,6 +622,7 @@ struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
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hal_rx_mpdu_get_addr3_8074v2,
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hal_rx_mpdu_get_addr3_8074v2,
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hal_rx_mpdu_get_addr4_8074v2,
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hal_rx_mpdu_get_addr4_8074v2,
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hal_rx_get_mpdu_sequence_control_valid_8074v2,
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hal_rx_get_mpdu_sequence_control_valid_8074v2,
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hal_rx_is_unicast_8074v2,
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};
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};
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struct hal_hw_srng_config hw_srng_table_8074v2[] = {
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struct hal_hw_srng_config hw_srng_table_8074v2[] = {
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@@ -546,6 +546,29 @@ static uint8_t hal_rx_get_mpdu_sequence_control_valid_9000(uint8_t *buf)
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return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
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return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
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}
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}
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/**
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* hal_rx_is_unicast_9000: check packet is unicast frame or not.
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*
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* @ buf: pointer to rx pkt TLV.
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*
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* Return: true on unicast.
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*/
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static bool hal_rx_is_unicast_9000(uint8_t *buf)
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{
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struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
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struct rx_mpdu_start *mpdu_start =
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&pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
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uint32_t grp_id;
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uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
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grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
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RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)),
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RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK,
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RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB));
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return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
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}
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struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
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struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
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/* init and setup */
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/* init and setup */
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@@ -609,6 +632,7 @@ struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
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|||||||
hal_rx_mpdu_get_addr3_9000,
|
hal_rx_mpdu_get_addr3_9000,
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||||||
hal_rx_mpdu_get_addr4_9000,
|
hal_rx_mpdu_get_addr4_9000,
|
||||||
hal_rx_get_mpdu_sequence_control_valid_9000,
|
hal_rx_get_mpdu_sequence_control_valid_9000,
|
||||||
|
hal_rx_is_unicast_9000,
|
||||||
};
|
};
|
||||||
|
|
||||||
struct hal_hw_srng_config hw_srng_table_9000[] = {
|
struct hal_hw_srng_config hw_srng_table_9000[] = {
|
||||||
|
Reference in New Issue
Block a user