msm: camera: icp: Add WD clear logic for lx7

AHB WD modules only support async reset. In order to clear
WD without complete camera reset disable and clear
WD interrupt. Kernel driver subscribes only for WD0, this
change adds this sequence only for WD0.

CRs-Fixed: 2841729
Change-Id: I0913d20fc3bd4bf911484efa42fb5889e539fea0
Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>

drivers/cam_icp/icp_hw/lx7_hw/lx7_core.c

@@ -857,8 +857,15 @@ irqreturn_t cam_lx7_handle_irq(int irq_num, void *data)
 	cam_io_w_mb(status, cirq_base + ICP_LX7_CIRQ_OB_CLEAR);
 	cam_io_w_mb(LX7_IRQ_CLEAR_CMD, cirq_base + ICP_LX7_CIRQ_OB_IRQ_CMD);
 
-	if (status & (LX7_WDT_BITE_WS0 | LX7_WDT_BITE_WS1)) {
-		CAM_ERR_RATE_LIMIT(CAM_ICP, "got watchdog interrupt from LX7");
+	if (status & LX7_WDT_BITE_WS0) {
+		/* WD clear sequence - SW listens only to WD0 */
+		cam_io_w_mb(0x0,
+			lx7_info->soc_info.reg_map[LX7_WD0_BASE].mem_base +
+			ICP_LX7_WD_CTRL);
+		cam_io_w_mb(0x1,
+			lx7_info->soc_info.reg_map[LX7_WD0_BASE].mem_base +
+			ICP_LX7_WD_INTCLR);
+		CAM_ERR_RATE_LIMIT(CAM_ICP, "Fatal: Watchdog Bite from LX7");
 		recover = true;
 	}
 

drivers/cam_icp/icp_hw/lx7_hw/lx7_core.h

@@ -15,6 +15,7 @@
 enum cam_lx7_reg_base {
 	LX7_CSR_BASE,
 	LX7_CIRQ_BASE,
+	LX7_WD0_BASE,
 	LX7_SYS_BASE,
 	LX7_BASE_MAX,
 };

drivers/cam_icp/icp_hw/lx7_hw/lx7_reg.h

@@ -20,6 +20,10 @@
 #define ICP_LX7_CIRQ_OB_CLEAR  0x4
 #define ICP_LX7_CIRQ_OB_STATUS 0xc
 
+/* ICP WD reg space */
+#define ICP_LX7_WD_CTRL        0x8
+#define ICP_LX7_WD_INTCLR      0xC
+
 /* These bitfields are shared by OB_MASK, OB_CLEAR, OB_STATUS */
 #define LX7_WDT_BITE_WS1       (1 << 6)
 #define LX7_WDT_BARK_WS1       (1 << 5)