qcacmn: Clear HW REO cache for shared reo qref entries

Clear HW REO cache when new entry is written to shared
REO qref table.

Change-Id: I43cffb66b3e7fdf62afb7ffc1729275b868b9888
CRs-Fixed: 3189158

dp/wifi3.0/dp_peer.c

@@ -3940,9 +3940,6 @@ void dp_peer_rx_init(struct dp_pdev *pdev, struct dp_peer *peer)
 	peer->hw_buffer_size = 0;
 	peer->kill_256_sessions = 0;
 
-	if (hal_reo_shared_qaddr_is_enable(pdev->soc->hal_soc))
-		hal_reo_shared_qaddr_cache_clear(pdev->soc->hal_soc);
-
 	/* Setup default (non-qos) rx tid queue */
 	dp_rx_tid_setup_wifi3(peer, DP_NON_QOS_TID, 1, 0);
 

hal/wifi3.0/be/hal_be_generic_api.h

@@ -618,6 +618,33 @@ hal_txmon_status_parse_tlv_generic_be(void *data_ppdu_info,
 #endif /* QCA_MONITOR_2_0_SUPPORT */
 
 #ifdef REO_SHARED_QREF_TABLE_EN
+static void hal_reo_shared_qaddr_cache_clear_be(hal_soc_handle_t hal_soc_hdl)
+{
+	struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
+	uint32_t reg_val = 0;
+
+	/* Set Qdesc clear bit to erase REO internal storage for Qdesc pointers
+	 * of 37 peer/tids
+	 */
+	reg_val = HAL_REG_READ(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE));
+	reg_val |= HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1);
+	HAL_REG_WRITE(hal,
+		      HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
+		      reg_val);
+
+	/* Clear Qdesc clear bit to erase REO internal storage for Qdesc pointers
+	 * of 37 peer/tids
+	 */
+	reg_val &= ~(HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1));
+	HAL_REG_WRITE(hal,
+		      HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
+		      reg_val);
+
+	hal_verbose_debug("hal_soc: %pK :Setting CLEAR_DESC_ARRAY field of"
+			  "WCSS_UMAC_REO_R0_QDESC_ADDR_READ and resetting back"
+			  "to erase stale entries in reo storage: regval:%x", hal, reg_val);
+}
+
 /* hal_reo_shared_qaddr_write(): Write REO tid queue addr
  * LUT shared by SW and HW at the index given by peer id
  * and tid.
@@ -658,6 +685,7 @@ static void hal_reo_shared_qaddr_write_be(hal_soc_handle_t hal_soc_hdl,
 	else
 		reo_qref->receive_queue_number = 0;
 
+	hal_reo_shared_qaddr_cache_clear_be(hal_soc_hdl);
 	hal_verbose_debug("hw_qdesc_paddr: %pK, tid: %d, reo_qref:%pK,"
 			  "rx_reo_queue_desc_addr_31_0: %x,"
 			  "rx_reo_queue_desc_addr_39_32: %x",
@@ -666,33 +694,6 @@ static void hal_reo_shared_qaddr_write_be(hal_soc_handle_t hal_soc_hdl,
 			  reo_qref->rx_reo_queue_desc_addr_39_32);
 }
 
-static void hal_reo_shared_qaddr_cache_clear_be(hal_soc_handle_t hal_soc_hdl)
-{
-	struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
-	uint32_t reg_val = 0;
-
-	/* Set Qdesc clear bit to erase REO internal storage for Qdesc pointers
-	 * of 37 peer/tids
-	 */
-	reg_val = HAL_REG_READ(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE));
-	reg_val |= HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1);
-	HAL_REG_WRITE(hal,
-		      HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
-		      reg_val);
-
-	/* Clear Qdesc clear bit to erase REO internal storage for Qdesc pointers
-	 * of 37 peer/tids
-	 */
-	reg_val &= ~(HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1));
-	HAL_REG_WRITE(hal,
-		      HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
-		      reg_val);
-
-	hal_verbose_debug("hal_soc: %pK :Setting CLEAR_DESC_ARRAY field of"
-			  "WCSS_UMAC_REO_R0_QDESC_ADDR_READ and resetting back"
-			  "to erase stale entries in reo storage: regval:%x", hal, reg_val);
-}
-
 /**
  * hal_reo_shared_qaddr_setup() - Allocate MLO and Non MLO reo queue
  * reference table shared between SW and HW and initialize in Qdesc Base0