samsung-sm8650/android_kernel_samsung_sm8650-modules
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msm: camera: isp: Update latency buffer allocation in header

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Based on the chipset update the latency buffer alloc config for
SFE RD. This value can obtained from CAMNOC HPG for a given target.

CRs-Fixed: 2841729
Change-Id: I86acf62e62edc473231f6fe75d9d4780a7f099ae
Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>
This commit is contained in:
Karthik Anantha Ram
2021-09-02 15:04:01 -07:00
parent c828b82890
commit 5c9aac95eb
4 changed files with 23 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe680.h
View File

@@ -498,6 +498,13 @@ static struct cam_sfe_bus_rd_hw_info sfe680_bus_rd_hw_info = {
}, },
}, },
.top_irq_shift = 0x1, .top_irq_shift = 0x1,
/*
* Refer to CAMNOC HPG for the updated value for a given target
* 48 OTs, 2 SFEs each with 3 RDs, 48 / 6 = 8
* We can allocate 256 * 8 = 2048 bytes. 256 bytes being
* the minimum
*/
.latency_buf_allocation = 2048,
}; };
static struct cam_irq_register_set sfe680_bus_wr_irq_reg[1] = { static struct cam_irq_register_set sfe680_bus_wr_irq_reg[1] = {

1
drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe780.h
View File

@@ -747,6 +747,7 @@ static struct cam_sfe_bus_rd_hw_info sfe780_bus_rd_hw_info = {
}, },
}, },
.top_irq_shift = 0x1, .top_irq_shift = 0x1,
.latency_buf_allocation = 2048,
}; };
static struct cam_irq_register_set sfe780_bus_wr_irq_reg[1] = { static struct cam_irq_register_set sfe780_bus_wr_irq_reg[1] = {

14
drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_rd.c
View File

@@ -29,7 +29,6 @@ static const char drv_name[] = "sfe_bus_rd";
#define MAX_REG_VAL_PAIR_SIZE \ #define MAX_REG_VAL_PAIR_SIZE \
(MAX_BUF_UPDATE_REG_NUM * 2 * CAM_PACKET_MAX_PLANES) (MAX_BUF_UPDATE_REG_NUM * 2 * CAM_PACKET_MAX_PLANES)
#define BUS_RD_DEFAULT_LATENCY_BUF_ALLOC 512
#define CAM_SFE_BUS_RD_PAYLOAD_MAX 16 #define CAM_SFE_BUS_RD_PAYLOAD_MAX 16
static uint32_t bus_rd_error_irq_mask[1] = { static uint32_t bus_rd_error_irq_mask[1] = {
@@ -134,6 +133,7 @@ struct cam_sfe_bus_rd_priv {
int error_irq_handle; int error_irq_handle;
void *tasklet_info; void *tasklet_info;
uint32_t top_irq_shift; uint32_t top_irq_shift;
uint32_t latency_buf_allocation;
}; };
static void cam_sfe_bus_rd_pxls_to_bytes(uint32_t pxls, uint32_t fmt, static void cam_sfe_bus_rd_pxls_to_bytes(uint32_t pxls, uint32_t fmt,
@@ -404,7 +404,7 @@ static int cam_sfe_bus_acquire_rm(
rsrc_data->unpacker_cfg = rsrc_data->unpacker_cfg =
cam_sfe_bus_get_unpacker_fmt(unpacker_fmt); cam_sfe_bus_get_unpacker_fmt(unpacker_fmt);
rsrc_data->latency_buf_allocation = rsrc_data->latency_buf_allocation =
BUS_RD_DEFAULT_LATENCY_BUF_ALLOC; bus_rd_priv->latency_buf_allocation;
rsrc_data->enable_caching = false; rsrc_data->enable_caching = false;
rsrc_data->enable_disable_cfg_done = false; rsrc_data->enable_disable_cfg_done = false;
rsrc_data->offset = 0; rsrc_data->offset = 0;
@@ -470,12 +470,11 @@ static int cam_sfe_bus_start_rm(struct cam_isp_resource_node *rm_res)
rm_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; rm_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING;
CAM_DBG(CAM_SFE, CAM_DBG(CAM_SFE,
"Start SFE:%d RM:%d offset:0x%X width:%d[in bytes: %u] height:%d", "Start SFE:%d RM:%d offset:0x%X width:%d [in bytes: %u] height:%d unpack_fmt:%d stride:%d latency_buf_alloc:%u",
rm_data->common_data->core_index, rm_data->index, rm_data->common_data->core_index, rm_data->index,
(uint32_t) rm_data->hw_regs->cfg, rm_data->offset, rm_data->width, width_in_bytes,
rm_data->width, width_in_bytes, rm_data->height); rm_data->height, rm_data->unpacker_cfg, rm_data->stride,
CAM_DBG(CAM_SFE, "RM:%d pk_fmt:%d stride:%d", rm_data->index, rm_data->latency_buf_allocation);
rm_data->unpacker_cfg, rm_data->stride);
return 0; return 0;
} }
@@ -1721,6 +1720,7 @@ int cam_sfe_bus_rd_init(
bus_priv->common_data.sfe_irq_controller = sfe_irq_controller; bus_priv->common_data.sfe_irq_controller = sfe_irq_controller;
bus_priv->common_data.common_reg = &bus_rd_hw_info->common_reg; bus_priv->common_data.common_reg = &bus_rd_hw_info->common_reg;
bus_priv->top_irq_shift = bus_rd_hw_info->top_irq_shift; bus_priv->top_irq_shift = bus_rd_hw_info->top_irq_shift;
bus_priv->latency_buf_allocation = bus_rd_hw_info->latency_buf_allocation;
rc = cam_irq_controller_init(drv_name, rc = cam_irq_controller_init(drv_name,
bus_priv->common_data.mem_base, bus_priv->common_data.mem_base,

14
drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_rd.h
View File

@@ -67,12 +67,13 @@ struct cam_sfe_bus_rd_info {
* *
* @Brief: HW register info for entire Bus * @Brief: HW register info for entire Bus
* *
* @common_reg: Common register details * @common_reg: Common register details
* @num_client: Number of bus rd clients * @num_client: Number of bus rd clients
* @bus_client_reg: Bus client register info * @bus_client_reg: Bus client register info
* @num_bus_rd_resc: Number of SFE BUS RD masters * @num_bus_rd_resc: Number of SFE BUS RD masters
* @sfe_bus_rd_info: SFE bus rd client info * @sfe_bus_rd_info: SFE bus rd client info
* @top_irq_shift: Top irq shift val * @top_irq_shift: Top irq shift val
* @latency_buf_allocation: latency buf allocation
*/ */
struct cam_sfe_bus_rd_hw_info { struct cam_sfe_bus_rd_hw_info {
struct cam_sfe_bus_rd_reg_offset_common common_reg; struct cam_sfe_bus_rd_reg_offset_common common_reg;
@@ -83,6 +84,7 @@ struct cam_sfe_bus_rd_hw_info {
struct cam_sfe_bus_rd_info struct cam_sfe_bus_rd_info
sfe_bus_rd_info[CAM_SFE_BUS_RD_MAX]; sfe_bus_rd_info[CAM_SFE_BUS_RD_MAX];
uint32_t top_irq_shift; uint32_t top_irq_shift;
uint32_t latency_buf_allocation;
}; };
/* /*