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@@ -29,7 +29,6 @@ static const char drv_name[] = "sfe_bus_rd";
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#define MAX_REG_VAL_PAIR_SIZE \
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#define MAX_REG_VAL_PAIR_SIZE \
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(MAX_BUF_UPDATE_REG_NUM * 2 * CAM_PACKET_MAX_PLANES)
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(MAX_BUF_UPDATE_REG_NUM * 2 * CAM_PACKET_MAX_PLANES)
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-#define BUS_RD_DEFAULT_LATENCY_BUF_ALLOC 512
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#define CAM_SFE_BUS_RD_PAYLOAD_MAX 16
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#define CAM_SFE_BUS_RD_PAYLOAD_MAX 16
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static uint32_t bus_rd_error_irq_mask[1] = {
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static uint32_t bus_rd_error_irq_mask[1] = {
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@@ -134,6 +133,7 @@ struct cam_sfe_bus_rd_priv {
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int error_irq_handle;
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int error_irq_handle;
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void *tasklet_info;
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void *tasklet_info;
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uint32_t top_irq_shift;
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uint32_t top_irq_shift;
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+ uint32_t latency_buf_allocation;
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};
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};
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static void cam_sfe_bus_rd_pxls_to_bytes(uint32_t pxls, uint32_t fmt,
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static void cam_sfe_bus_rd_pxls_to_bytes(uint32_t pxls, uint32_t fmt,
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@@ -404,7 +404,7 @@ static int cam_sfe_bus_acquire_rm(
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rsrc_data->unpacker_cfg =
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rsrc_data->unpacker_cfg =
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cam_sfe_bus_get_unpacker_fmt(unpacker_fmt);
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cam_sfe_bus_get_unpacker_fmt(unpacker_fmt);
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rsrc_data->latency_buf_allocation =
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rsrc_data->latency_buf_allocation =
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- BUS_RD_DEFAULT_LATENCY_BUF_ALLOC;
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+ bus_rd_priv->latency_buf_allocation;
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rsrc_data->enable_caching = false;
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rsrc_data->enable_caching = false;
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rsrc_data->enable_disable_cfg_done = false;
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rsrc_data->enable_disable_cfg_done = false;
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rsrc_data->offset = 0;
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rsrc_data->offset = 0;
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@@ -470,12 +470,11 @@ static int cam_sfe_bus_start_rm(struct cam_isp_resource_node *rm_res)
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rm_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING;
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rm_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING;
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CAM_DBG(CAM_SFE,
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CAM_DBG(CAM_SFE,
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- "Start SFE:%d RM:%d offset:0x%X width:%d[in bytes: %u] height:%d",
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+ "Start SFE:%d RM:%d offset:0x%X width:%d [in bytes: %u] height:%d unpack_fmt:%d stride:%d latency_buf_alloc:%u",
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rm_data->common_data->core_index, rm_data->index,
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rm_data->common_data->core_index, rm_data->index,
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- (uint32_t) rm_data->hw_regs->cfg,
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- rm_data->width, width_in_bytes, rm_data->height);
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- CAM_DBG(CAM_SFE, "RM:%d pk_fmt:%d stride:%d", rm_data->index,
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- rm_data->unpacker_cfg, rm_data->stride);
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+ rm_data->offset, rm_data->width, width_in_bytes,
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+ rm_data->height, rm_data->unpacker_cfg, rm_data->stride,
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+ rm_data->latency_buf_allocation);
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return 0;
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return 0;
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}
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}
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@@ -1721,6 +1720,7 @@ int cam_sfe_bus_rd_init(
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bus_priv->common_data.sfe_irq_controller = sfe_irq_controller;
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bus_priv->common_data.sfe_irq_controller = sfe_irq_controller;
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bus_priv->common_data.common_reg = &bus_rd_hw_info->common_reg;
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bus_priv->common_data.common_reg = &bus_rd_hw_info->common_reg;
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bus_priv->top_irq_shift = bus_rd_hw_info->top_irq_shift;
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bus_priv->top_irq_shift = bus_rd_hw_info->top_irq_shift;
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+ bus_priv->latency_buf_allocation = bus_rd_hw_info->latency_buf_allocation;
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rc = cam_irq_controller_init(drv_name,
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rc = cam_irq_controller_init(drv_name,
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bus_priv->common_data.mem_base,
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bus_priv->common_data.mem_base,
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