From 5c7dfa0712d1d66f237906c21ac890af19177dd9 Mon Sep 17 00:00:00 2001 From: Satya Rama Aditya Pinapala Date: Tue, 23 Feb 2021 10:51:26 -0800 Subject: [PATCH] disp: msm: dsi: ensure even rate for DSI byte clock in DPHY For DPHY, DSI byte clock is used to derive the byte interface clock through a DIV_2 divider. While setting the rate for byte interface clock, if the byte clock rate is odd the recalculation of byte interface clock will fail. This can further lead to recalculation of byte clock and result in unexpected value for byte clock. The change ensures that for DPHY, the byte clock rate is always even to avoid such issues. Change-Id: I0a0371af75e5819ed1283b52b4681e70f55d66e0 Signed-off-by: Satya Rama Aditya Pinapala --- msm/dsi/dsi_ctrl.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/msm/dsi/dsi_ctrl.c b/msm/dsi/dsi_ctrl.c index ed7a21c2bc..769fc10b9a 100644 --- a/msm/dsi/dsi_ctrl.c +++ b/msm/dsi/dsi_ctrl.c @@ -1027,7 +1027,12 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl, bit_rate_per_lane = bit_rate; do_div(bit_rate_per_lane, num_of_lanes); byte_clk_rate = bit_rate_per_lane; - do_div(byte_clk_rate, 8); + /** + * Ensure that the byte clock rate is even to avoid failures + * during set rate for byte intf clock. + */ + byte_clk_rate = DIV_ROUND_CLOSEST(byte_clk_rate, 8); + byte_clk_rate &= ~BIT(0); byte_intf_clk_rate = byte_clk_rate; byte_intf_clk_div = host_cfg->byte_intf_clk_div; do_div(byte_intf_clk_rate, byte_intf_clk_div);