qcacmn: Changes in HW cookie conversion for MLO
Changes to have HW cookie conversion context per desc pool. This context will be used to program CMEM of the other SOC in case multi-chip MLO. Change-Id: I5ec68813e8fcb6d124698a52f5553acf9a7b1795
This commit is contained in:
Chaithanya Garrepalli
کامیت شده توسط
Madan Koyyalamudi
Madan Koyyalamudi
والد
0fb9dcb7eb
کامیت
5be4508174
@@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2021 The Linux Foundation. All rights reserved.
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* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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@@ -24,6 +25,9 @@
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/* maximum number of entries in one page of secondary page table */
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#define DP_CC_SPT_PAGE_MAX_ENTRIES 512
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/* maximum number of entries in one page of secondary page table */
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#define DP_CC_SPT_PAGE_MAX_ENTRIES_MASK (DP_CC_SPT_PAGE_MAX_ENTRIES - 1)
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/* maximum number of entries in primary page table */
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#define DP_CC_PPT_MAX_ENTRIES 1024
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@@ -76,6 +80,27 @@
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/* WBM2SW ring id for rx release */
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#define WBM2SW_REL_ERR_RING_NUM 5
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#endif
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/* tx descriptor are programmed at start of CMEM region*/
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#define DP_TX_DESC_CMEM_OFFSET 0
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/* size of CMEM needed for a tx desc pool*/
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#define DP_TX_DESC_POOL_CMEM_SIZE \
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((WLAN_CFG_NUM_TX_DESC_MAX / DP_CC_SPT_PAGE_MAX_ENTRIES) * \
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DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)
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/* Offset of rx descripotor pool */
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#define DP_RX_DESC_CMEM_OFFSET \
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DP_TX_DESC_CMEM_OFFSET + (MAX_TXDESC_POOLS * DP_TX_DESC_POOL_CMEM_SIZE)
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/* size of CMEM needed for a rx desc pool */
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#define DP_RX_DESC_POOL_CMEM_SIZE \
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((WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX / DP_CC_SPT_PAGE_MAX_ENTRIES) * \
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DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)
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/* get ppt_id from CMEM_OFFSET */
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#define DP_CMEM_OFFSET_TO_PPT_ID(offset) \
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((offset) / DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)
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/**
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* struct dp_spt_page_desc - secondary page table page descriptors
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* @next: pointer to next linked SPT page Desc
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@@ -86,28 +111,23 @@
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* @avail_entry_index: index for available entry that store TX/RX Desc VA
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*/
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struct dp_spt_page_desc {
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struct dp_spt_page_desc *next;
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uint8_t *page_v_addr;
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qdf_dma_addr_t page_p_addr;
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uint16_t ppt_index;
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uint16_t avail_entry_index;
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uint32_t ppt_index;
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};
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/**
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* struct dp_hw_cookie_conversion_t - main context for HW cookie conversion
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* @cmem_base: CMEM base address for primary page table setup
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* @cmem_offset: CMEM offset from base address for primary page table setup
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* @total_page_num: total DDR page allocated
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* @free_page_num: available DDR page number for TX/RX Desc ID initialization
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* @page_desc_freelist: available page Desc list
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* @page_desc_base: page Desc buffer base address.
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* @page_pool: DDR pages pool
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* @cc_lock: locks for page acquiring/free
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*/
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struct dp_hw_cookie_conversion_t {
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uint32_t cmem_base;
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uint32_t cmem_offset;
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uint32_t total_page_num;
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uint32_t free_page_num;
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struct dp_spt_page_desc *page_desc_freelist;
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struct dp_spt_page_desc *page_desc_base;
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struct qdf_mem_multi_page_t page_pool;
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qdf_spinlock_t cc_lock;
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@@ -148,9 +168,9 @@ struct dp_tx_bank_profile {
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* @soc: dp soc structure
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* @num_bank_profiles: num TX bank profiles
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* @bank_profiles: bank profiles for various TX banks
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* @hw_cc_ctx: core context of HW cookie conversion
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* @tx_spt_page_desc: spt page desc allocated for TX desc pool
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* @rx_spt_page_desc: spt page desc allocated for RX desc pool
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* @cc_cmem_base: cmem offset reserved for CC
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* @tx_cc_ctx: Cookie conversion context for tx desc pools
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* @rx_cc_ctx: Cookie conversion context for rx desc pools
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* @monitor_soc_be: BE specific monitor object
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*/
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struct dp_soc_be {
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@@ -158,9 +178,10 @@ struct dp_soc_be {
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uint8_t num_bank_profiles;
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qdf_mutex_t tx_bank_lock;
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struct dp_tx_bank_profile *bank_profiles;
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struct dp_hw_cookie_conversion_t hw_cc_ctx;
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struct dp_spt_page_desc_list tx_spt_page_desc[MAX_TXDESC_POOLS];
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struct dp_spt_page_desc_list rx_spt_page_desc[MAX_RXDESC_POOLS];
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struct dp_spt_page_desc *page_desc_base;
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uint32_t cc_cmem_base;
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struct dp_hw_cookie_conversion_t tx_cc_ctx[MAX_TXDESC_POOLS];
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struct dp_hw_cookie_conversion_t rx_cc_ctx[MAX_RXDESC_POOLS];
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#ifdef WLAN_SUPPORT_PPEDS
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struct dp_srng reo2ppe_ring;
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struct dp_srng ppe2tcl_ring;
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@@ -276,6 +297,22 @@ struct dp_peer_be *dp_get_be_peer_from_dp_peer(struct dp_peer *peer)
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return (struct dp_peer_be *)peer;
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}
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QDF_STATUS
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dp_hw_cookie_conversion_attach(struct dp_soc_be *be_soc,
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struct dp_hw_cookie_conversion_t *cc_ctx,
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uint32_t num_descs,
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enum dp_desc_type desc_type,
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uint8_t desc_pool_id);
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QDF_STATUS
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dp_hw_cookie_conversion_detach(struct dp_soc_be *be_soc,
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struct dp_hw_cookie_conversion_t *cc_ctx);
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QDF_STATUS
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dp_hw_cookie_conversion_init(struct dp_soc_be *be_soc,
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struct dp_hw_cookie_conversion_t *cc_ctx);
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QDF_STATUS
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dp_hw_cookie_conversion_deinit(struct dp_soc_be *be_soc,
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struct dp_hw_cookie_conversion_t *cc_ctx);
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/**
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* dp_cc_spt_page_desc_alloc() - allocate SPT DDR page descriptor from pool
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* @be_soc: beryllium soc handler
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@@ -311,7 +348,7 @@ void dp_cc_spt_page_desc_free(struct dp_soc_be *be_soc,
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*
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* Return: cookie ID
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*/
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static inline uint32_t dp_cc_desc_id_generate(uint16_t ppt_index,
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static inline uint32_t dp_cc_desc_id_generate(uint32_t ppt_index,
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uint16_t spt_index)
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{
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/*
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@@ -337,12 +374,10 @@ static inline uintptr_t dp_cc_desc_find(struct dp_soc *soc,
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uint32_t desc_id)
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{
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struct dp_soc_be *be_soc;
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struct dp_hw_cookie_conversion_t *cc_ctx;
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uint16_t ppt_page_id, spt_va_id;
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uint8_t *spt_page_va;
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be_soc = dp_get_be_soc_from_dp_soc(soc);
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cc_ctx = &be_soc->hw_cc_ctx;
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ppt_page_id = (desc_id & DP_CC_DESC_ID_PPT_PAGE_OS_MASK) >>
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DP_CC_DESC_ID_PPT_PAGE_OS_SHIFT;
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@@ -355,7 +390,7 @@ static inline uintptr_t dp_cc_desc_find(struct dp_soc *soc,
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* entry size in DDR page is 64 bits, for 32 bits system,
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* only lower 32 bits VA value is needed.
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*/
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spt_page_va = cc_ctx->page_desc_base[ppt_page_id].page_v_addr;
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spt_page_va = be_soc->page_desc_base[ppt_page_id].page_v_addr;
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return (*((uintptr_t *)(spt_page_va +
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spt_va_id * DP_CC_HW_READ_BYTES)));
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@@ -471,4 +506,21 @@ _dp_srng_test_and_update_nf_params(struct dp_soc *soc,
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}
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#endif
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static inline
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uint32_t dp_desc_pool_get_cmem_base(uint8_t chip_id, uint8_t desc_pool_id,
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enum dp_desc_type desc_type)
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{
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switch (desc_type) {
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case DP_TX_DESC_TYPE:
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return (DP_TX_DESC_CMEM_OFFSET +
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(desc_pool_id * DP_TX_DESC_POOL_CMEM_SIZE));
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case DP_RX_DESC_BUF_TYPE:
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return (DP_RX_DESC_CMEM_OFFSET +
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((chip_id * MAX_RXDESC_POOLS) + desc_pool_id) *
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DP_RX_DESC_POOL_CMEM_SIZE);
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default:
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QDF_BUG(0);
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}
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return 0;
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}
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#endif
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