qcacmn: hal: Initialize hal_hw_txrx_ops for 9000

Change hal_hw_txrx_ops struct to designated initializer syntax for
structs for qcn9000.

Change-Id: I3144d5f184d196365e49d6afae843316fef0f1e2
CRs-Fixed: 2837917

hal/wifi3.0/qcn9000/hal_9000.c

@@ -1734,125 +1734,123 @@ void hal_compute_reo_remap_ix2_ix3_9000(uint32_t *ring, uint32_t num_rings,
 struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
 
 	/* init and setup */
-	hal_srng_dst_hw_init_generic,
-	hal_srng_src_hw_init_generic,
-	hal_get_hw_hptp_generic,
-	hal_reo_setup_generic,
-	hal_setup_link_idle_list_generic,
-	hal_get_window_address_9000,
-	NULL,
+	.hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic,
+	.hal_srng_src_hw_init = hal_srng_src_hw_init_generic,
+	.hal_get_hw_hptp = hal_get_hw_hptp_generic,
+	.hal_reo_setup = hal_reo_setup_generic,
+	.hal_setup_link_idle_list = hal_setup_link_idle_list_generic,
+	.hal_get_window_address = hal_get_window_address_9000,
 
 	/* tx */
-	hal_tx_desc_set_dscp_tid_table_id_9000,
-	hal_tx_set_dscp_tid_map_9000,
-	hal_tx_update_dscp_tid_9000,
-	hal_tx_desc_set_lmac_id_9000,
-	hal_tx_desc_set_buf_addr_generic,
-	hal_tx_desc_set_search_type_generic,
-	hal_tx_desc_set_search_index_generic,
-	hal_tx_desc_set_cache_set_num_generic,
-	hal_tx_comp_get_status_generic,
-	hal_tx_comp_get_release_reason_generic,
-	hal_get_wbm_internal_error_generic,
-	hal_tx_desc_set_mesh_en_9000,
-	hal_tx_init_cmd_credit_ring_9000,
+	.hal_tx_desc_set_dscp_tid_table_id =
+		hal_tx_desc_set_dscp_tid_table_id_9000,
+	.hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_9000,
+	.hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_9000,
+	.hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_9000,
+	.hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic,
+	.hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic,
+	.hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic,
+	.hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic,
+	.hal_tx_comp_get_status = hal_tx_comp_get_status_generic,
+	.hal_tx_comp_get_release_reason =
+		hal_tx_comp_get_release_reason_generic,
+	.hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic,
+	.hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_9000,
+	.hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_9000,
 
 	/* rx */
-	hal_rx_msdu_start_nss_get_9000,
-	hal_rx_mon_hw_desc_get_mpdu_status_9000,
-	hal_rx_get_tlv_9000,
-	hal_rx_proc_phyrx_other_receive_info_tlv_9000,
-	hal_rx_dump_msdu_start_tlv_9000,
-	hal_rx_dump_msdu_end_tlv_9000,
-	hal_get_link_desc_size_9000,
-	hal_rx_mpdu_start_tid_get_9000,
-	hal_rx_msdu_start_reception_type_get_9000,
-	hal_rx_msdu_end_da_idx_get_9000,
-	hal_rx_msdu_desc_info_get_ptr_9000,
-	hal_rx_link_desc_msdu0_ptr_9000,
-	hal_reo_status_get_header_9000,
-	hal_rx_status_get_tlv_info_generic,
-	hal_rx_wbm_err_info_get_generic,
-	hal_rx_dump_mpdu_start_tlv_generic,
-
-	hal_tx_set_pcp_tid_map_generic,
-	hal_tx_update_pcp_tid_generic,
-	hal_tx_update_tidmap_prty_generic,
-	hal_rx_get_rx_fragment_number_9000,
-	hal_rx_msdu_end_da_is_mcbc_get_9000,
-	hal_rx_msdu_end_sa_is_valid_get_9000,
-	hal_rx_msdu_end_sa_idx_get_9000,
-	hal_rx_desc_is_first_msdu_9000,
+	.hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_9000,
+	.hal_rx_mon_hw_desc_get_mpdu_status =
+		hal_rx_mon_hw_desc_get_mpdu_status_9000,
+	.hal_rx_get_tlv = hal_rx_get_tlv_9000,
+	.hal_rx_proc_phyrx_other_receive_info_tlv =
+		hal_rx_proc_phyrx_other_receive_info_tlv_9000,
+	.hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_9000,
+	.hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_9000,
+	.hal_get_link_desc_size = hal_get_link_desc_size_9000,
+	.hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_9000,
+	.hal_rx_msdu_start_reception_type_get =
+		hal_rx_msdu_start_reception_type_get_9000,
+	.hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_9000,
+	.hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_9000,
+	.hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_9000,
+	.hal_reo_status_get_header = hal_reo_status_get_header_9000,
+	.hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic,
+	.hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic,
+	.hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic,
+
+	.hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic,
+	.hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic,
+	.hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic,
+	.hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_9000,
+	.hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_9000,
+	.hal_rx_msdu_end_sa_is_valid_get = hal_rx_msdu_end_sa_is_valid_get_9000,
+	.hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_9000,
+	.hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_9000,
+	.hal_rx_msdu_end_l3_hdr_padding_get =
 	hal_rx_msdu_end_l3_hdr_padding_get_9000,
-	hal_rx_encryption_info_valid_9000,
-	hal_rx_print_pn_9000,
-	hal_rx_msdu_end_first_msdu_get_9000,
-	hal_rx_msdu_end_da_is_valid_get_9000,
-	hal_rx_msdu_end_last_msdu_get_9000,
-	hal_rx_get_mpdu_mac_ad4_valid_9000,
-	hal_rx_mpdu_start_sw_peer_id_get_9000,
-	hal_rx_mpdu_get_to_ds_9000,
-	hal_rx_mpdu_get_fr_ds_9000,
-	hal_rx_get_mpdu_frame_control_valid_9000,
-	hal_rx_mpdu_get_addr1_9000,
-	hal_rx_mpdu_get_addr2_9000,
-	hal_rx_mpdu_get_addr3_9000,
-	hal_rx_mpdu_get_addr4_9000,
-	hal_rx_get_mpdu_sequence_control_valid_9000,
-	hal_rx_is_unicast_9000,
-	hal_rx_tid_get_9000,
-	hal_rx_hw_desc_get_ppduid_get_9000,
-	hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000,
-	hal_rx_msdu_end_sa_sw_peer_id_get_9000,
-	hal_rx_msdu0_buffer_addr_lsb_9000,
-	hal_rx_msdu_desc_info_ptr_get_9000,
-	hal_ent_mpdu_desc_info_9000,
-	hal_dst_mpdu_desc_info_9000,
-	hal_rx_get_fc_valid_9000,
-	hal_rx_get_to_ds_flag_9000,
-	hal_rx_get_mac_addr2_valid_9000,
-	hal_rx_get_filter_category_9000,
-	hal_rx_get_ppdu_id_9000,
-	hal_reo_config_9000,
-	hal_rx_msdu_flow_idx_get_9000,
-	hal_rx_msdu_flow_idx_invalid_9000,
-	hal_rx_msdu_flow_idx_timeout_9000,
-	hal_rx_msdu_fse_metadata_get_9000,
-	hal_rx_msdu_cce_metadata_get_9000,
-	hal_rx_msdu_get_flow_params_9000,
-	hal_rx_tlv_get_tcp_chksum_9000,
-	hal_rx_get_rx_sequence_9000,
+	.hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_9000,
+	.hal_rx_print_pn = hal_rx_print_pn_9000,
+	.hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_9000,
+	.hal_rx_msdu_end_da_is_valid_get = hal_rx_msdu_end_da_is_valid_get_9000,
+	.hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_9000,
+	.hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_9000,
+	.hal_rx_mpdu_start_sw_peer_id_get =
+		hal_rx_mpdu_start_sw_peer_id_get_9000,
+	.hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_9000,
+	.hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_9000,
+	.hal_rx_get_mpdu_frame_control_valid =
+		hal_rx_get_mpdu_frame_control_valid_9000,
+	.hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_9000,
+	.hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_9000,
+	.hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_9000,
+	.hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_9000,
+	.hal_rx_get_mpdu_sequence_control_valid =
+		hal_rx_get_mpdu_sequence_control_valid_9000,
+	.hal_rx_is_unicast = hal_rx_is_unicast_9000,
+	.hal_rx_tid_get = hal_rx_tid_get_9000,
+	.hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_9000,
+	.hal_rx_mpdu_start_mpdu_qos_control_valid_get =
+		hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000,
+	.hal_rx_msdu_end_sa_sw_peer_id_get =
+		hal_rx_msdu_end_sa_sw_peer_id_get_9000,
+	.hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_9000,
+	.hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_9000,
+	.hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_9000,
+	.hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_9000,
+	.hal_rx_get_fc_valid = hal_rx_get_fc_valid_9000,
+	.hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_9000,
+	.hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_9000,
+	.hal_rx_get_filter_category = hal_rx_get_filter_category_9000,
+	.hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_9000,
+	.hal_reo_config = hal_reo_config_9000,
+	.hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_9000,
+	.hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_9000,
+	.hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_9000,
+	.hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_9000,
+	.hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_9000,
+	.hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_9000,
+	.hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_9000,
+	.hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_9000,
 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
-	hal_rx_get_bb_info_9000,
-	hal_rx_get_rtt_info_9000,
-#else
-	NULL,
-	NULL,
+	.hal_rx_get_bb_info = hal_rx_get_bb_info_9000,
+	.hal_rx_get_rtt_info = hal_rx_get_rtt_info_9000,
 #endif
 	/* rx - msdu fast path info fields */
-	hal_rx_msdu_packet_metadata_get_9000,
-	NULL,
-	NULL,
-	NULL,
-	NULL,
-	NULL,
-	NULL,
-	hal_rx_mpdu_start_tlv_tag_valid_9000,
-	hal_rx_sw_mon_desc_info_get_9000,
-	hal_rx_wbm_err_msdu_continuation_get_9000,
+	.hal_rx_msdu_packet_metadata_get = hal_rx_msdu_packet_metadata_get_9000,
+	.hal_rx_mpdu_start_tlv_tag_valid = hal_rx_mpdu_start_tlv_tag_valid_9000,
+	.hal_rx_sw_mon_desc_info_get = hal_rx_sw_mon_desc_info_get_9000,
+	.hal_rx_wbm_err_msdu_continuation_get =
+		hal_rx_wbm_err_msdu_continuation_get_9000,
 
 	/* rx - TLV struct offsets */
-	hal_rx_msdu_end_offset_get_generic,
-	hal_rx_attn_offset_get_generic,
-	hal_rx_msdu_start_offset_get_generic,
-	hal_rx_mpdu_start_offset_get_generic,
-	hal_rx_mpdu_end_offset_get_generic,
-	hal_rx_flow_setup_fse_9000,
-	hal_compute_reo_remap_ix2_ix3_9000,
-	NULL,
-	NULL,
-	NULL,
-	NULL
+	.hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic,
+	.hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic,
+	.hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic,
+	.hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic,
+	.hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic,
+	.hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_9000,
+	.hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_9000,
 };
 
 struct hal_hw_srng_config hw_srng_table_9000[] = {