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@@ -86,6 +86,7 @@ enum country_code {
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CTRY_GEORGIA = 268,
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CTRY_GERMANY = 276,
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CTRY_GHANA = 288,
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+ CTRY_GIBRALTAR = 292,
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CTRY_GREECE = 300,
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CTRY_GREENLAND = 304,
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CTRY_GRENADA = 308,
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@@ -99,6 +100,7 @@ enum country_code {
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CTRY_HUNGARY = 348,
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CTRY_ICELAND = 352,
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CTRY_INDIA = 356,
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+ CTRY_INDIA2 = 5006,
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CTRY_INDONESIA = 360,
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CTRY_IRELAND = 372,
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CTRY_ISRAEL = 376,
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@@ -202,38 +204,11 @@ enum country_code {
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CTRY_WALLIS_AND_FUTUNA = 876,
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CTRY_YEMEN = 887,
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CTRY_ZIMBABWE = 716,
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- CTRY_JAPAN7 = 4007,
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- CTRY_JAPAN8 = 4008,
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- CTRY_JAPAN9 = 4009,
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- CTRY_JAPAN10 = 4010,
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- CTRY_JAPAN11 = 4011,
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- CTRY_JAPAN12 = 4012,
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- CTRY_JAPAN13 = 4013,
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- CTRY_JAPAN14 = 4014,
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CTRY_JAPAN15 = 4015,
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- CTRY_JAPAN25 = 4025,
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- CTRY_JAPAN26 = 4026,
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- CTRY_JAPAN27 = 4027,
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- CTRY_JAPAN28 = 4028,
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- CTRY_JAPAN29 = 4029,
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- CTRY_JAPAN34 = 4034,
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- CTRY_JAPAN35 = 4035,
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- CTRY_JAPAN36 = 4036,
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- CTRY_JAPAN37 = 4037,
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- CTRY_JAPAN38 = 4038,
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- CTRY_JAPAN39 = 4039,
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- CTRY_JAPAN40 = 4040,
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- CTRY_JAPAN41 = 4041,
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- CTRY_JAPAN42 = 4042,
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- CTRY_JAPAN43 = 4043,
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- CTRY_JAPAN44 = 4044,
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- CTRY_JAPAN45 = 4045,
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- CTRY_JAPAN46 = 4046,
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- CTRY_JAPAN47 = 4047,
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+ CTRY_JAPAN9 = 4009,
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CTRY_JAPAN48 = 4048,
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- CTRY_JAPAN49 = 4049,
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CTRY_JAPAN55 = 4055,
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- CTRY_JAPAN56 = 4056,
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+ CTRY_JAPAN60 = 4060,
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CTRY_XA = 4100,
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};
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@@ -252,6 +227,8 @@ enum reg_domain {
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FCC6_FCCA = 0x14,
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FCC8_FCCA = 0x16,
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FCC11_WORLD = 0x19,
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+ FCC13_WORLD = 0xE4,
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+ FCC14_FCCB = 0xE6,
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ETSI1_WORLD = 0x37,
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ETSI3_WORLD = 0x36,
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@@ -269,33 +246,22 @@ enum reg_domain {
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APL8_WORLD = 0x5D,
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APL9_WORLD = 0x5E,
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APL10_WORLD = 0x5F,
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+ APL11_FCCA = 0x4F,
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APL12_WORLD = 0x51,
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APL13_WORLD = 0x5A,
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APL14_WORLD = 0x57,
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APL15_WORLD = 0x59,
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APL16_WORLD = 0x70,
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+ APL17_ETSID = 0xE0,
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+ APL19_ETSIC = 0x71,
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+ APL20_WORLD = 0xE5,
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+ APL23_WORLD = 0xE3,
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- MKK3_MKKA = 0xF0,
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- MKK3_MKKB = 0x80,
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MKK3_MKKC = 0x82,
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- MKK3_FCCA = 0xF2,
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- MKK4_MKKA = 0xF3,
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- MKK4_MKKB = 0x83,
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- MKK4_MKKC = 0x85,
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- MKK4_FCCA = 0xF5,
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MKK5_MKKA = 0x99,
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- MKK5_MKKB = 0x86,
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MKK5_MKKC = 0x88,
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- MKK5_FCCA = 0x9A,
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- MKK9_MKKA = 0xF6,
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- MKK9_MKKC = 0xFE,
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- MKK9_FCCA = 0xFC,
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- MKK10_MKKA = 0xF7,
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- MKK10_MKKC = 0xD2,
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- MKK10_FCCA = 0xD0,
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- MKK11_MKKA = 0xD4,
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- MKK11_FCCA = 0xD5,
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MKK11_MKKC = 0xD7,
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+ MKK16_MKKC = 0xDF,
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WORLD_60 = 0x60,
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WORLD_61 = 0x61,
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@@ -371,6 +337,7 @@ const struct country_code_to_reg_domain g_all_countries[] = {
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{CTRY_GEORGIA, ETSI4_WORLD, "GE", "GE", 40, 160, 0},
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{CTRY_GERMANY, ETSI1_WORLD, "DE", "DE", 40, 160, 0},
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{CTRY_GHANA, FCC3_WORLD, "GH", "GH", 40, 160, 0},
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+ {CTRY_GIBRALTAR, ETSI1_WORLD, "GI", "GI", 40, 160, 0},
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{CTRY_GREECE, ETSI1_WORLD, "GR", "GR", 40, 160, 0},
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{CTRY_GREENLAND, ETSI1_WORLD, "GL", "GL", 40, 160, 0},
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{CTRY_GRENADA, FCC3_FCCA, "GD", "GD", 40, 160, 0},
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@@ -384,6 +351,7 @@ const struct country_code_to_reg_domain g_all_countries[] = {
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{CTRY_HUNGARY, ETSI1_WORLD, "HU", "HU" , 40, 160, 0},
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{CTRY_ICELAND, ETSI1_WORLD, "IS", "IS" , 40, 160, 0},
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{CTRY_INDIA, APL15_WORLD, "IN", "IN", 40, 160, 0},
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+ {CTRY_INDIA2, APL19_ETSIC, "IN", "IN", 40, 160, 0},
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{CTRY_INDONESIA, APL2_ETSIC, "ID", "ID", 40, 20, 0},
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{CTRY_IRELAND, ETSI1_WORLD, "IE", "IE", 40, 160, 0},
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{CTRY_ISRAEL, ETSI3_WORLD, "IL", "IL", 40, 160, 0},
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@@ -430,7 +398,7 @@ const struct country_code_to_reg_domain g_all_countries[] = {
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{CTRY_OMAN, ETSI1_WORLD, "OM", "OM", 40, 160, 0},
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{CTRY_PAKISTAN, APL1_ETSIC, "PK", "PK", 40, 160, 0},
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{CTRY_PALAU, FCC3_FCCA, "PW", "PW", 40, 160, 0},
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- {CTRY_PANAMA, FCC1_FCCA, "PA", "PA", 40, 160, 0},
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+ {CTRY_PANAMA, FCC14_FCCB, "PA", "PA", 40, 160, 0},
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{CTRY_PAPUA_NEW_GUINEA, FCC3_WORLD, "PG", "PG", 40, 160, 0},
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{CTRY_PARAGUAY, FCC3_WORLD, "PY", "PY", 40, 160, 0},
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{CTRY_PERU, FCC3_WORLD, "PE", "PE", 40, 160, 0},
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@@ -488,47 +456,22 @@ const struct country_code_to_reg_domain g_all_countries[] = {
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{CTRY_WALLIS_AND_FUTUNA, ETSI1_WORLD, "WF", "WF", 40, 160, 0},
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{CTRY_YEMEN, NULL1_WORLD, "YE", "YE", 40, 0, 0},
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{CTRY_ZIMBABWE, ETSI1_WORLD, "ZW", "ZW", 40, 160, 0},
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- {CTRY_JAPAN7, MKK3_MKKB, "J7", "JP" , 40, 160, 0},
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- {CTRY_JAPAN8, MKK3_MKKA, "J8", "JP" , 40, 160, 0},
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- {CTRY_JAPAN9, MKK3_MKKC, "J9", "JP" , 40, 160, 0},
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- {CTRY_JAPAN10, MKK4_MKKB, "J10", "JP" , 40, 160, 0},
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- {CTRY_JAPAN11, MKK4_MKKA, "J11", "JP" , 40, 160, 0},
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- {CTRY_JAPAN12, MKK4_MKKC, "J12", "JP" , 40, 160, 0},
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- {CTRY_JAPAN13, MKK5_MKKB, "J13", "JP" , 40, 160, 0},
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- {CTRY_JAPAN14, MKK5_MKKA, "JP", "JP" , 40, 160, 0},
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{CTRY_JAPAN15, MKK5_MKKC, "J15", "JP" , 40, 160, 0},
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- {CTRY_JAPAN25, MKK3_MKKA, "J25", "JP" , 40, 160, 0},
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- {CTRY_JAPAN26, MKK3_MKKA, "J26", "JP" , 40, 160, 0},
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- {CTRY_JAPAN27, MKK3_FCCA, "J27", "JP" , 40, 160, 0},
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- {CTRY_JAPAN28, MKK4_MKKA, "J28", "JP" , 40, 160, 0},
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- {CTRY_JAPAN29, MKK4_FCCA, "J29", "JP" , 40, 160, 0},
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- {CTRY_JAPAN34, MKK9_MKKA, "J34", "JP" , 40, 160, 0},
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- {CTRY_JAPAN35, MKK10_MKKA, "J35", "JP" , 40, 160, 0},
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- {CTRY_JAPAN36, MKK4_MKKA, "J36", "JP" , 40, 160, 0},
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- {CTRY_JAPAN37, MKK9_FCCA, "J37", "JP" , 40, 160, 0},
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- {CTRY_JAPAN38, MKK9_MKKA, "J38", "JP" , 40, 160, 0},
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- {CTRY_JAPAN39, MKK9_MKKC, "J39", "JP" , 40, 160, 0},
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- {CTRY_JAPAN40, MKK9_MKKA, "J40", "JP" , 40, 160, 0},
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- {CTRY_JAPAN41, MKK10_FCCA, "J41", "JP" , 40, 160, 0},
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- {CTRY_JAPAN42, MKK10_MKKA, "J42", "JP" , 40, 160, 0},
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- {CTRY_JAPAN43, MKK10_MKKC, "J43", "JP" , 40, 160, 0},
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- {CTRY_JAPAN44, MKK10_MKKA, "J44", "JP" , 40, 160, 0},
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- {CTRY_JAPAN45, MKK11_MKKA, "J45", "JP" , 40, 160, 0},
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- {CTRY_JAPAN46, MKK11_FCCA, "J46", "JP" , 40, 160, 0},
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- {CTRY_JAPAN47, MKK11_MKKA, "J47", "JP" , 40, 160, 0},
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- {CTRY_JAPAN48, MKK11_MKKC, "J48", "JP" , 40, 160, 0},
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- {CTRY_JAPAN49, MKK11_MKKA, "J49", "JP" , 40, 160, 0},
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- {CTRY_JAPAN55, MKK5_MKKA, "J55", "JP" , 40, 160, 0},
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- {CTRY_JAPAN56, MKK5_FCCA, "J56", "JP" , 40, 160, 0},
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+ {CTRY_JAPAN9, MKK3_MKKC, "J9", "JP", 40, 160, 0},
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+ {CTRY_JAPAN48, MKK11_MKKC, "J48", "JP", 40, 160, 0},
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+ {CTRY_JAPAN55, MKK5_MKKA, "J55", "JP", 40, 160, 0},
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+ {CTRY_JAPAN60, MKK16_MKKC, "J60", "JP", 40, 160, 0},
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{CTRY_XA, MKK5_MKKA, "XA", "XA", 40, 160, 0},
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};
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enum reg_domains_2g {
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FCCA,
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+ FCCB,
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WORLD,
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MKKA,
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MKKC,
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ETSIC,
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+ ETSID,
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WORLD_2G_1,
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WORLD_2G_2,
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WORLD_2G_3,
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@@ -543,6 +486,8 @@ enum reg_domains_5g {
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FCC6,
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FCC8,
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FCC11,
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+ FCC13,
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+ FCC14,
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ETSI1,
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ETSI3,
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ETSI4,
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@@ -556,17 +501,23 @@ enum reg_domains_5g {
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APL8,
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APL9,
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APL10,
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+ APL11,
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APL12,
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APL13,
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APL14,
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APL15,
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APL16,
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+ APL17,
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+ APL19,
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+ APL20,
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+ APL23,
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MKK3,
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MKK4,
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MKK5,
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MKK9,
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MKK10,
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MKK11,
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+ MKK16,
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WORLD_5G_1,
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WORLD_5G_2,
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};
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@@ -587,6 +538,8 @@ const struct reg_domain_pair g_reg_dmn_pairs[] = {
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{FCC6_FCCA, FCC6, FCCA},
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{FCC8_FCCA, FCC8, FCCA},
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{FCC11_WORLD, FCC11, WORLD},
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+ {FCC13_WORLD, FCC13, WORLD},
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+ {FCC14_FCCB, FCC14, FCCB},
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{ETSI1_WORLD, ETSI1, WORLD},
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{ETSI3_WORLD, ETSI3, WORLD},
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@@ -604,30 +557,22 @@ const struct reg_domain_pair g_reg_dmn_pairs[] = {
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{APL8_WORLD, APL8, WORLD},
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{APL9_WORLD, APL9, WORLD},
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{APL10_WORLD, APL10, WORLD},
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+ {APL11_FCCA, APL11, FCCA},
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{APL12_WORLD, APL12, WORLD},
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{APL13_WORLD, APL13, WORLD},
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{APL14_WORLD, APL14, WORLD},
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{APL15_WORLD, APL15, WORLD},
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{APL16_WORLD, APL16, WORLD},
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+ {APL17_ETSID, APL17, ETSID},
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+ {APL19_ETSIC, APL19, ETSIC},
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+ {APL20_WORLD, APL20, WORLD},
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+ {APL23_WORLD, APL23, WORLD},
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- {MKK3_MKKA, MKK3, MKKA},
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{MKK3_MKKC, MKK3, MKKC},
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- {MKK3_FCCA, MKK3, FCCA},
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- {MKK4_MKKA, MKK4, MKKA},
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- {MKK4_MKKC, MKK4, MKKC},
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- {MKK4_FCCA, MKK4, FCCA},
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{MKK5_MKKA, MKK5, MKKA},
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{MKK5_MKKC, MKK5, MKKC},
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- {MKK5_FCCA, MKK5, FCCA},
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- {MKK9_MKKA, MKK9, MKKA},
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- {MKK9_MKKC, MKK9, MKKC},
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- {MKK9_FCCA, MKK9, FCCA},
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- {MKK10_MKKA, MKK10, MKKA},
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- {MKK10_MKKC, MKK10, MKKC},
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- {MKK10_FCCA, MKK10, FCCA},
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- {MKK11_MKKA, MKK11, MKKA},
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- {MKK11_FCCA, MKK11, FCCA},
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{MKK11_MKKC, MKK11, MKKC},
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+ {MKK16_MKKC, MKK16, MKKC},
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{WORLD_60, WORLD_5G_2, WORLD_2G_3},
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{WORLD_61, WORLD_5G_2, WORLD_2G_3},
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@@ -647,8 +592,10 @@ enum reg_rules_2g {
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CHAN_1_11_1,
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CHAN_1_11_2,
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+ CHAN_1_11_3,
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CHAN_1_13_1,
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CHAN_1_13_2,
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+ CHAN_1_13_3,
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CHAN_12_13_1,
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CHAN_14_1,
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CHAN_14_2,
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@@ -658,8 +605,10 @@ const struct regulatory_rule reg_rules_2g[] = {
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[CHAN_1_11_1] = {2402, 2472, 40, 30, 0},
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[CHAN_1_11_2] = {2402, 2472, 40, 20, 0},
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+ [CHAN_1_11_3] = {2402, 2472, 40, 36, 0},
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[CHAN_1_13_1] = {2402, 2482, 40, 20, 0},
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[CHAN_1_13_2] = {2402, 2482, 40, 30, 0},
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+ [CHAN_1_13_3] = {2402, 2482, 40, 36, 0},
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[CHAN_12_13_1] = {2457, 2482, 40, 30, REGULATORY_CHAN_NO_IR},
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[CHAN_14_1] = {2474, 2494, 20, 20, REGULATORY_CHAN_NO_OFDM},
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[CHAN_14_2] = {2474, 2494, 20, 20,
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@@ -670,10 +619,12 @@ const struct regulatory_rule reg_rules_2g[] = {
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const struct regdomain regdomains_2g[] = {
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[FCCA] = {CTL_FCC, DFS_UNINIT_REG, 0, 6, 1, {CHAN_1_11_1} },
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+ [FCCB] = {CTL_FCC, DFS_UNINIT_REG, 0, 6, 1, {CHAN_1_11_3} },
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[WORLD] = {CTL_ETSI, DFS_UNINIT_REG, 0, 0, 1, {CHAN_1_13_1} },
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[MKKA] = {CTL_MKK, DFS_UNINIT_REG, 0, 0, 2, {CHAN_1_13_1, CHAN_14_1} },
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[MKKC] = {CTL_MKK, DFS_UNINIT_REG, 0, 0, 1, {CHAN_1_13_1} },
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[ETSIC] = {CTL_ETSI, DFS_UNINIT_REG, 0, 0, 1, {CHAN_1_13_2} },
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+ [ETSID] = {CTL_ETSI, DFS_UNINIT_REG, 0, 0, 1, {CHAN_1_13_3} },
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[WORLD_2G_1] = {CTL_NONE, DFS_UNINIT_REG, 0, 0, 1, {CHAN_1_11_2} },
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[WORLD_2G_2] = {CTL_NONE, DFS_UNINIT_REG, 0, 0, 2,
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{CHAN_1_11_2, CHAN_12_13_1} },
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@@ -693,7 +644,11 @@ enum reg_rules_5g {
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CHAN_5170_5250_4,
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CHAN_5170_5250_5,
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CHAN_5170_5250_6,
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+ CHAN_5170_5250_7,
|
|
|
+ CHAN_5170_5250_8,
|
|
|
+ CHAN_5170_5250_9,
|
|
|
CHAN_5170_5330_1,
|
|
|
+ CHAN_5170_5330_2,
|
|
|
CHAN_5250_5330_1,
|
|
|
CHAN_5250_5330_2,
|
|
|
CHAN_5250_5330_3,
|
|
@@ -701,14 +656,24 @@ enum reg_rules_5g {
|
|
|
CHAN_5250_5330_5,
|
|
|
CHAN_5250_5330_6,
|
|
|
CHAN_5250_5330_7,
|
|
|
+ CHAN_5250_5330_8,
|
|
|
+ CHAN_5250_5330_9,
|
|
|
+ CHAN_5250_5330_10,
|
|
|
+ CHAN_5250_5330_11,
|
|
|
+ CHAN_5250_5330_12,
|
|
|
+ CHAN_5250_5330_13,
|
|
|
CHAN_5490_5730_1,
|
|
|
CHAN_5490_5730_2,
|
|
|
CHAN_5490_5730_3,
|
|
|
+ CHAN_5490_5730_4,
|
|
|
+ CHAN_5490_5730_5,
|
|
|
CHAN_5490_5710_1,
|
|
|
CHAN_5490_5710_2,
|
|
|
CHAN_5490_5710_3,
|
|
|
+ CHAN_5490_5710_4,
|
|
|
CHAN_5490_5590_1,
|
|
|
CHAN_5490_5590_2,
|
|
|
+ CHAN_5490_5590_3,
|
|
|
CHAN_5490_5570_1,
|
|
|
CHAN_5490_5650_1,
|
|
|
CHAN_5490_5650_2,
|
|
@@ -716,15 +681,21 @@ enum reg_rules_5g {
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CHAN_5490_5630_1,
|
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|
CHAN_5650_5730_1,
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|
CHAN_5650_5730_2,
|
|
|
+ CHAN_5650_5730_3,
|
|
|
CHAN_5735_5835_1,
|
|
|
CHAN_5735_5835_2,
|
|
|
CHAN_5735_5835_3,
|
|
|
CHAN_5735_5835_4,
|
|
|
CHAN_5735_5835_5,
|
|
|
CHAN_5735_5835_6,
|
|
|
+ CHAN_5735_5835_7,
|
|
|
CHAN_5735_5875_1,
|
|
|
+ CHAN_5735_5875_2,
|
|
|
+ CHAN_5735_5875_3,
|
|
|
CHAN_5735_5815_1,
|
|
|
CHAN_5735_5775_1,
|
|
|
+ CHAN_5835_5855_1,
|
|
|
+ CHAN_5855_5875_1,
|
|
|
};
|
|
|
|
|
|
const struct regulatory_rule reg_rules_5g[] = {
|
|
@@ -738,7 +709,11 @@ const struct regulatory_rule reg_rules_5g[] = {
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|
|
[CHAN_5170_5250_4] = {5170, 5250, 80, 30, 0},
|
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|
[CHAN_5170_5250_5] = {5170, 5250, 80, 24, 0},
|
|
|
[CHAN_5170_5250_6] = {5170, 5250, 80, 18, 0},
|
|
|
+ [CHAN_5170_5250_7] = {5170, 5250, 80, 20, REGULATORY_CHAN_INDOOR_ONLY},
|
|
|
+ [CHAN_5170_5250_8] = {5170, 5250, 80, 23, REGULATORY_CHAN_INDOOR_ONLY},
|
|
|
+ [CHAN_5170_5250_9] = {5170, 5250, 40, 30, 0},
|
|
|
[CHAN_5170_5330_1] = {5170, 5330, 160, 20, REGULATORY_CHAN_NO_IR},
|
|
|
+ [CHAN_5170_5330_2] = {5170, 5330, 160, 24, 0},
|
|
|
[CHAN_5250_5330_1] = {5250, 5330, 80, 23, REGULATORY_CHAN_RADAR},
|
|
|
[CHAN_5250_5330_2] = {5250, 5330, 80, 20, REGULATORY_CHAN_RADAR},
|
|
|
[CHAN_5250_5330_3] = {5250, 5330, 80, 18, REGULATORY_CHAN_RADAR},
|
|
@@ -746,14 +721,25 @@ const struct regulatory_rule reg_rules_5g[] = {
|
|
|
[CHAN_5250_5330_5] = {5250, 5330, 80, 23, 0},
|
|
|
[CHAN_5250_5330_6] = {5250, 5330, 80, 30, 0},
|
|
|
[CHAN_5250_5330_7] = {5250, 5330, 80, 24, REGULATORY_CHAN_RADAR},
|
|
|
+ [CHAN_5250_5330_8] = {5250, 5330, 80, 36, 0},
|
|
|
+ [CHAN_5250_5330_9] = {5250, 5330, 80, 20, 0},
|
|
|
+ [CHAN_5250_5330_10] = {5250, 5330, 80, 24, 0},
|
|
|
+ [CHAN_5250_5330_11] = {5250, 5330, 80, 20, REGULATORY_CHAN_INDOOR_ONLY},
|
|
|
+ [CHAN_5250_5330_12] = {5250, 5330, 80, 23, REGULATORY_CHAN_RADAR |
|
|
|
+ REGULATORY_CHAN_INDOOR_ONLY},
|
|
|
+ [CHAN_5250_5330_13] = {5250, 5330, 40, 30, REGULATORY_CHAN_RADAR},
|
|
|
[CHAN_5490_5730_1] = {5490, 5730, 160, 24, REGULATORY_CHAN_RADAR},
|
|
|
- [CHAN_5490_5730_2] = {5490, 5730, 160, 30, REGULATORY_CHAN_RADAR},
|
|
|
- [CHAN_5490_5730_3] = {5490, 5730, 160, 20, REGULATORY_CHAN_NO_IR},
|
|
|
+ [CHAN_5490_5730_2] = {5490, 5730, 160, 20, REGULATORY_CHAN_NO_IR},
|
|
|
+ [CHAN_5490_5730_3] = {5490, 5730, 160, 30, 0},
|
|
|
+ [CHAN_5490_5730_4] = {5490, 5730, 160, 24, 0},
|
|
|
+ [CHAN_5490_5730_5] = {5490, 5730, 160, 30, REGULATORY_CHAN_RADAR},
|
|
|
[CHAN_5490_5710_1] = {5490, 5710, 160, 30, REGULATORY_CHAN_RADAR},
|
|
|
[CHAN_5490_5710_2] = {5490, 5710, 160, 20, REGULATORY_CHAN_RADAR},
|
|
|
[CHAN_5490_5710_3] = {5490, 5710, 160, 27, REGULATORY_CHAN_RADAR},
|
|
|
+ [CHAN_5490_5710_4] = {5490, 5710, 40, 30, REGULATORY_CHAN_RADAR},
|
|
|
[CHAN_5490_5590_1] = {5490, 5590, 80, 24, REGULATORY_CHAN_RADAR},
|
|
|
[CHAN_5490_5590_2] = {5490, 5590, 80, 30, 0},
|
|
|
+ [CHAN_5490_5590_3] = {5490, 5590, 80, 36, 0},
|
|
|
[CHAN_5490_5570_1] = {5490, 5570, 80, 30, REGULATORY_CHAN_RADAR},
|
|
|
[CHAN_5490_5650_1] = {5490, 5650, 160, 23, REGULATORY_CHAN_RADAR},
|
|
|
[CHAN_5490_5650_2] = {5490, 5650, 160, 24, REGULATORY_CHAN_RADAR},
|
|
@@ -761,15 +747,21 @@ const struct regulatory_rule reg_rules_5g[] = {
|
|
|
[CHAN_5490_5630_1] = {5490, 5630, 80, 30, REGULATORY_CHAN_RADAR},
|
|
|
[CHAN_5650_5730_1] = {5650, 5730, 80, 24, REGULATORY_CHAN_RADAR},
|
|
|
[CHAN_5650_5730_2] = {5650, 5730, 80, 30, 0},
|
|
|
+ [CHAN_5650_5730_3] = {5650, 5730, 80, 36, 0},
|
|
|
[CHAN_5735_5835_1] = {5735, 5835, 80, 23, 0},
|
|
|
[CHAN_5735_5835_2] = {5735, 5835, 80, 30, 0},
|
|
|
[CHAN_5735_5835_3] = {5735, 5835, 80, 20, 0},
|
|
|
- [CHAN_5735_5835_4] = {5735, 5835, 80, 27, 0},
|
|
|
+ [CHAN_5735_5835_4] = {5735, 5835, 80, 33, 0},
|
|
|
[CHAN_5735_5835_5] = {5735, 5835, 80, 20, REGULATORY_CHAN_NO_IR},
|
|
|
[CHAN_5735_5835_6] = {5735, 5835, 80, 24, 0},
|
|
|
+ [CHAN_5735_5835_7] = {5735, 5835, 80, 36, 0},
|
|
|
[CHAN_5735_5875_1] = {5735, 5875, 20, 27, 0},
|
|
|
+ [CHAN_5735_5875_2] = {5735, 5875, 20, 30, 0},
|
|
|
+ [CHAN_5735_5875_3] = {5735, 5875, 80, 30, 0},
|
|
|
[CHAN_5735_5815_1] = {5735, 5815, 80, 30, 0},
|
|
|
[CHAN_5735_5775_1] = {5735, 5775, 40, 23, 0},
|
|
|
+ [CHAN_5835_5855_1] = {5835, 5855, 20, 30, 0},
|
|
|
+ [CHAN_5855_5875_1] = {5855, 5875, 20, 30, 0},
|
|
|
};
|
|
|
|
|
|
|
|
@@ -806,19 +798,28 @@ const struct regdomain regdomains_5g[] = {
|
|
|
CHAN_5490_5650_2,
|
|
|
CHAN_5735_5835_6} },
|
|
|
|
|
|
- [ETSI1] = {CTL_ETSI, DFS_ETSI_REG, 5, 0, 3, {CHAN_5170_5250_2,
|
|
|
+ [FCC13] = {CTL_FCC, DFS_UNINIT_REG, 2, 0, 4, {CHAN_5170_5330_2,
|
|
|
+ CHAN_5250_5330_10,
|
|
|
+ CHAN_5490_5730_4,
|
|
|
+ CHAN_5735_5835_2} },
|
|
|
+
|
|
|
+ [FCC14] = {CTL_FCC, DFS_UNINIT_REG, 2, 0, 3, {CHAN_5170_5250_2,
|
|
|
+ CHAN_5250_5330_6,
|
|
|
+ CHAN_5735_5835_7} },
|
|
|
+
|
|
|
+ [ETSI1] = {CTL_ETSI, DFS_ETSI_REG, 2, 0, 3, {CHAN_5170_5250_2,
|
|
|
CHAN_5250_5330_1,
|
|
|
CHAN_5490_5710_1} },
|
|
|
|
|
|
- [ETSI3] = {CTL_ETSI, DFS_ETSI_REG, 5, 0, 2, {CHAN_5170_5250_3,
|
|
|
- CHAN_5250_5330_2} },
|
|
|
+ [ETSI3] = {CTL_ETSI, DFS_ETSI_REG, 5, 0, 2, {CHAN_5170_5250_2,
|
|
|
+ CHAN_5250_5330_1} },
|
|
|
|
|
|
- [ETSI4] = {CTL_ETSI, DFS_ETSI_REG, 5, 0, 2, {CHAN_5170_5250_6,
|
|
|
+ [ETSI4] = {CTL_ETSI, DFS_ETSI_REG, 2, 0, 2, {CHAN_5170_5250_6,
|
|
|
CHAN_5250_5330_3} },
|
|
|
|
|
|
- [ETSI8] = {CTL_ETSI, DFS_ETSI_REG, 20, 0, 4, {CHAN_5170_5250_3,
|
|
|
- CHAN_5250_5330_2,
|
|
|
- CHAN_5490_5730_2,
|
|
|
+ [ETSI8] = {CTL_ETSI, DFS_UNINIT_REG, 20, 0, 4, {CHAN_5170_5250_2,
|
|
|
+ CHAN_5250_5330_5,
|
|
|
+ CHAN_5490_5730_3,
|
|
|
CHAN_5735_5835_2} },
|
|
|
|
|
|
[ETSI9] = {CTL_ETSI, DFS_ETSI_REG, 20, 0, 4, {CHAN_5170_5250_3,
|
|
@@ -847,14 +848,19 @@ const struct regdomain regdomains_5g[] = {
|
|
|
|
|
|
[APL9] = {CTL_ETSI, DFS_KR_REG, 2, 6, 4, {CHAN_5170_5250_3,
|
|
|
CHAN_5250_5330_2,
|
|
|
- CHAN_5490_5730_2,
|
|
|
+ CHAN_5490_5730_5,
|
|
|
CHAN_5735_5835_2} },
|
|
|
|
|
|
- [APL10] = {CTL_ETSI, DFS_FCC_REG, 2, 6, 4, {CHAN_5170_5250_3,
|
|
|
- CHAN_5250_5330_2,
|
|
|
+ [APL10] = {CTL_ETSI, DFS_FCC_REG, 2, 6, 4, {CHAN_5170_5250_2,
|
|
|
+ CHAN_5250_5330_4,
|
|
|
CHAN_5490_5710_1,
|
|
|
CHAN_5735_5815_1} },
|
|
|
|
|
|
+ [APL11] = { CTL_ETSI, DFS_ETSI_REG, 2, 0, 4, {CHAN_5170_5250_9,
|
|
|
+ CHAN_5250_5330_13,
|
|
|
+ CHAN_5490_5710_4,
|
|
|
+ CHAN_5735_5875_2} },
|
|
|
+
|
|
|
[APL12] = {CTL_ETSI, DFS_ETSI_REG, 2, 0, 3, {CHAN_5170_5250_2,
|
|
|
CHAN_5490_5570_1,
|
|
|
CHAN_5735_5775_1} },
|
|
@@ -869,7 +875,7 @@ const struct regdomain regdomains_5g[] = {
|
|
|
|
|
|
[APL15] = {CTL_FCC, DFS_UNINIT_REG, 2, 0, 3, {CHAN_5170_5250_2,
|
|
|
CHAN_5250_5330_5,
|
|
|
- CHAN_5735_5835_2} },
|
|
|
+ CHAN_5735_5835_4} },
|
|
|
|
|
|
[APL16] = {CTL_FCC, DFS_UNINIT_REG, 2, 0, 5, {CHAN_5170_5250_1,
|
|
|
CHAN_5250_5330_6,
|
|
@@ -877,35 +883,44 @@ const struct regdomain regdomains_5g[] = {
|
|
|
CHAN_5650_5730_2,
|
|
|
CHAN_5735_5835_2} },
|
|
|
|
|
|
- [MKK3] = {CTL_MKK, DFS_UNINIT_REG, 2, 0, 1, {CHAN_5170_5250_3} },
|
|
|
+ [APL17] = {CTL_FCC, DFS_UNINIT_REG, 2, 0, 5, {CHAN_5170_5250_2,
|
|
|
+ CHAN_5250_5330_8,
|
|
|
+ CHAN_5490_5590_3,
|
|
|
+ CHAN_5650_5730_3,
|
|
|
+ CHAN_5735_5835_7} },
|
|
|
|
|
|
- [MKK4] = {CTL_MKK, DFS_MKK_REG, 2, 0, 2, {CHAN_5170_5250_3,
|
|
|
- CHAN_5250_5330_2} },
|
|
|
+ [APL19] = {CTL_FCC, DFS_UNINIT_REG, 2, 0, 3, {CHAN_5170_5250_2,
|
|
|
+ CHAN_5250_5330_5,
|
|
|
+ CHAN_5735_5875_3} },
|
|
|
+
|
|
|
+ [APL20] = {CTL_ETSI, DFS_ETSI_REG, 2, 0, 4, {CHAN_5170_5250_8,
|
|
|
+ CHAN_5250_5330_12,
|
|
|
+ CHAN_5490_5730_5,
|
|
|
+ CHAN_5735_5835_4} },
|
|
|
+
|
|
|
+ [APL23] = {CTL_ETSI, DFS_UNINIT_REG, 2, 0, 3, {CHAN_5170_5250_7,
|
|
|
+ CHAN_5250_5330_11,
|
|
|
+ CHAN_5735_5835_3} },
|
|
|
+
|
|
|
+ [MKK3] = {CTL_MKK, DFS_UNINIT_REG, 2, 0, 1, {CHAN_5170_5250_3} },
|
|
|
|
|
|
[MKK5] = {CTL_MKK, DFS_MKK_REG, 2, 0, 3, {CHAN_5170_5250_3,
|
|
|
CHAN_5250_5330_2,
|
|
|
CHAN_5490_5710_2} },
|
|
|
|
|
|
- [MKK9] = {CTL_MKK, DFS_UNINIT_REG, 2, 0, 3, {CHAN_5170_5250_3,
|
|
|
- CHAN_4910_4990_1,
|
|
|
- CHAN_5030_5090_1} },
|
|
|
-
|
|
|
- [MKK10] = {CTL_MKK, DFS_MKK_REG, 2, 0, 4, {CHAN_5170_5250_3,
|
|
|
- CHAN_5250_5330_2,
|
|
|
- CHAN_4910_4990_1,
|
|
|
- CHAN_5030_5090_1} },
|
|
|
-
|
|
|
[MKK11] = {CTL_MKK, DFS_MKK_REG, 2, 0, 5, {CHAN_5170_5250_3,
|
|
|
CHAN_5250_5330_2,
|
|
|
CHAN_5490_5710_2,
|
|
|
CHAN_4910_4990_1,
|
|
|
CHAN_5030_5090_1} },
|
|
|
|
|
|
+ [MKK16] = {CTL_MKK, DFS_MKK_REG, 2, 0, 1, {CHAN_5490_5710_2} },
|
|
|
+
|
|
|
[WORLD_5G_1] = {CTL_NONE, DFS_UNINIT_REG, 2, 0, 2, {CHAN_5170_5330_1,
|
|
|
CHAN_5735_5835_5} },
|
|
|
|
|
|
[WORLD_5G_2] = {CTL_NONE, DFS_UNINIT_REG, 2, 0, 3, {CHAN_5170_5330_1,
|
|
|
- CHAN_5490_5730_3,
|
|
|
+ CHAN_5490_5730_2,
|
|
|
CHAN_5735_5835_5} },
|
|
|
};
|
|
|
|