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qcacmn: Add HAL APIs for Lithium targets

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Add hal soc API handlers for existing Lithium targets.

Change-Id: I2ca25c94702759eb8329eb24048c9f5732caa3cc
CRs-Fixed: 2891049
This commit is contained in:
Rakesh Pillai
2021-02-16 23:34:38 -08:00
committed by Manjunathappa Prakash
parent acd7abc01b
commit 59ea466ca4
13 changed files with 1028 additions and 514 deletions
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152
hal/wifi3.0/qca5018/hal_5018.c
View File

@@ -15,7 +15,7 @@
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#include "hal_hw_headers.h"
#include "hal_li_hw_headers.h"
#include "hal_internal.h"
#include "hal_api.h"
#include "target_type.h"
@@ -120,7 +120,9 @@
#include <hal_5018_tx.h>
#include <hal_5018_rx.h>
#include <hal_generic_api.h>
#include <hal_wbm.h>
#include "hal_li_rx.h"
#include "hal_li_api.h"
#include "hal_li_generic_api.h"
/**
* hal_rx_msdu_start_nss_get_5018(): API to get the NSS
@@ -1103,19 +1105,26 @@ static uint32_t hal_rx_hw_desc_get_ppduid_get_5018(void *rx_tlv_hdr,
/**
* hal_reo_status_get_header_5018 - Process reo desc info
* @d - Pointer to reo descriptior
* @ring_desc: REO status ring descriptor
* @b - tlv type info
* @h1 - Pointer to hal_reo_status_header where info to be stored
*
* Return - none.
*
*/
static void hal_reo_status_get_header_5018(uint32_t *d, int b, void *h1)
static void hal_reo_status_get_header_5018(hal_ring_desc_t ring_desc, int b,
void *h1)
{
uint32_t *d = (uint32_t *)ring_desc;
uint32_t val1 = 0;
struct hal_reo_status_header *h =
(struct hal_reo_status_header *)h1;
/* Offsets of descriptor fields defined in HW headers start
* from the field after TLV header
*/
d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr));
switch (b) {
case HAL_REO_QUEUE_STATS_STATUS_TLV:
val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
@@ -1656,8 +1665,7 @@ static void hal_hw_txrx_ops_attach_qca5018(struct hal_soc *hal_soc)
hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic;
hal_soc->ops->hal_setup_link_idle_list = hal_setup_link_idle_list_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li;
hal_soc->ops->hal_get_window_address = hal_get_window_address_5018;
/* tx */
@@ -1666,54 +1674,84 @@ static void hal_hw_txrx_ops_attach_qca5018(struct hal_soc *hal_soc)
hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_5018;
hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_5018;
hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_5018;
hal_soc->ops->hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic;
hal_soc->ops->hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic;
hal_soc->ops->hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic;
hal_soc->ops->hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic;
hal_soc->ops->hal_tx_comp_get_status = hal_tx_comp_get_status_generic;
hal_soc->ops->hal_tx_desc_set_buf_addr =
hal_tx_desc_set_buf_addr_generic_li;
hal_soc->ops->hal_tx_desc_set_search_type =
hal_tx_desc_set_search_type_generic_li;
hal_soc->ops->hal_tx_desc_set_search_index =
hal_tx_desc_set_search_index_generic_li;
hal_soc->ops->hal_tx_desc_set_cache_set_num =
hal_tx_desc_set_cache_set_num_generic_li;
hal_soc->ops->hal_tx_comp_get_status =
hal_tx_comp_get_status_generic_li;
hal_soc->ops->hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic;
hal_soc->ops->hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic;
hal_tx_comp_get_release_reason_generic_li;
hal_soc->ops->hal_get_wbm_internal_error =
hal_get_wbm_internal_error_generic_li;
hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_5018;
hal_soc->ops->hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_5018;
hal_soc->ops->hal_tx_init_cmd_credit_ring =
hal_tx_init_cmd_credit_ring_5018;
/* rx */
hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_5018;
hal_soc->ops->hal_rx_msdu_start_nss_get =
hal_rx_msdu_start_nss_get_5018;
hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_5018;
hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_5018;
hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_5018;
hal_soc->ops->hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_5018;
hal_soc->ops->hal_rx_dump_msdu_start_tlv =
hal_rx_dump_msdu_start_tlv_5018;
hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_5018;
hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_5018;
hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_5018;
hal_soc->ops->hal_rx_mpdu_start_tid_get =
hal_rx_mpdu_start_tid_get_5018;
hal_soc->ops->hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_5018;
hal_soc->ops->hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_5018;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_5018;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_5018;
hal_soc->ops->hal_reo_status_get_header = hal_reo_status_get_header_5018;
hal_soc->ops->hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic;
hal_soc->ops->hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic;
hal_soc->ops->hal_rx_msdu_end_da_idx_get =
hal_rx_msdu_end_da_idx_get_5018;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
hal_rx_msdu_desc_info_get_ptr_5018;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
hal_rx_link_desc_msdu0_ptr_5018;
hal_soc->ops->hal_reo_status_get_header =
hal_reo_status_get_header_5018;
hal_soc->ops->hal_rx_status_get_tlv_info =
hal_rx_status_get_tlv_info_generic_li;
hal_soc->ops->hal_rx_wbm_err_info_get =
hal_rx_wbm_err_info_get_generic_li;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
hal_rx_dump_mpdu_start_tlv_generic_li;
hal_soc->ops->hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic;
hal_soc->ops->hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic;
hal_soc->ops->hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic;
hal_soc->ops->hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_5018;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_5018;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = hal_rx_msdu_end_sa_is_valid_get_5018;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_5018;
hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_5018;
hal_soc->ops->hal_tx_set_pcp_tid_map =
hal_tx_set_pcp_tid_map_generic_li;
hal_soc->ops->hal_tx_update_pcp_tid_map =
hal_tx_update_pcp_tid_generic_li;
hal_soc->ops->hal_tx_set_tidmap_prty =
hal_tx_update_tidmap_prty_generic_li;
hal_soc->ops->hal_rx_get_rx_fragment_number =
hal_rx_get_rx_fragment_number_5018;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
hal_rx_msdu_end_da_is_mcbc_get_5018;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
hal_rx_msdu_end_sa_is_valid_get_5018;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
hal_rx_msdu_end_sa_idx_get_5018;
hal_soc->ops->hal_rx_desc_is_first_msdu =
hal_rx_desc_is_first_msdu_5018;
hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_5018;
hal_soc->ops->hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_5018;
hal_soc->ops->hal_rx_encryption_info_valid =
hal_rx_encryption_info_valid_5018;
hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_5018;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_5018;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = hal_rx_msdu_end_da_is_valid_get_5018;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_5018;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_5018;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
hal_rx_msdu_end_first_msdu_get_5018;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
hal_rx_msdu_end_da_is_valid_get_5018;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
hal_rx_msdu_end_last_msdu_get_5018;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
hal_rx_get_mpdu_mac_ad4_valid_5018;
hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_5018;
hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_5018;
@@ -1728,36 +1766,49 @@ static void hal_hw_txrx_ops_attach_qca5018(struct hal_soc *hal_soc)
hal_rx_get_mpdu_sequence_control_valid_5018;
hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_5018;
hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_5018;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_5018;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
hal_rx_hw_desc_get_ppduid_get_5018;
hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018;
hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
hal_rx_msdu_end_sa_sw_peer_id_get_5018;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_5018;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_5018;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
hal_rx_msdu0_buffer_addr_lsb_5018;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
hal_rx_msdu_desc_info_ptr_get_5018;
hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_5018;
hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_5018;
hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_5018;
hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_5018;
hal_soc->ops->hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_5018;
hal_soc->ops->hal_rx_get_filter_category = hal_rx_get_filter_category_5018;
hal_soc->ops->hal_rx_get_mac_addr2_valid =
hal_rx_get_mac_addr2_valid_5018;
hal_soc->ops->hal_rx_get_filter_category =
hal_rx_get_filter_category_5018;
hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_5018;
hal_soc->ops->hal_reo_config = hal_reo_config_5018;
hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_5018;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_5018;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_5018;
hal_soc->ops->hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_5018;
hal_soc->ops->hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_5018;
hal_soc->ops->hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_5018;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_5018;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
hal_rx_msdu_flow_idx_invalid_5018;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
hal_rx_msdu_flow_idx_timeout_5018;
hal_soc->ops->hal_rx_msdu_fse_metadata_get =
hal_rx_msdu_fse_metadata_get_5018;
hal_soc->ops->hal_rx_msdu_cce_metadata_get =
hal_rx_msdu_cce_metadata_get_5018;
hal_soc->ops->hal_rx_msdu_get_flow_params =
hal_rx_msdu_get_flow_params_5018;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
hal_rx_tlv_get_tcp_chksum_5018;
hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_5018;
#if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_5018;
hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_5018;
#endif
/* rx - msdu fast path info fields */
hal_soc->ops->hal_rx_msdu_packet_metadata_get = hal_rx_msdu_packet_metadata_get_5018;
hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = hal_rx_mpdu_start_tlv_tag_valid_5018;
hal_soc->ops->hal_rx_msdu_packet_metadata_get =
hal_rx_msdu_packet_metadata_get_5018;
hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
hal_rx_mpdu_start_tlv_tag_valid_5018;
hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get =
hal_rx_wbm_err_msdu_continuation_get_5018;
@@ -2226,5 +2277,6 @@ void hal_qca5018_attach(struct hal_soc *hal_soc)
{
hal_soc->hw_srng_table = hw_srng_table_5018;
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca5018;
hal_hw_txrx_default_ops_attach_li(hal_soc);
hal_hw_txrx_ops_attach_qca5018(hal_soc);
}

176
hal/wifi3.0/qca6290/hal_6290.c
View File

@@ -21,7 +21,7 @@
#include "qdf_lock.h"
#include "qdf_mem.h"
#include "qdf_nbuf.h"
#include "hal_hw_headers.h"
#include "hal_li_hw_headers.h"
#include "hal_internal.h"
#include "hal_api.h"
#include "target_type.h"
@@ -108,7 +108,9 @@
#include "hal_6290_tx.h"
#include "hal_6290_rx.h"
#include <hal_generic_api.h>
#include <hal_wbm.h>
#include "hal_li_rx.h"
#include "hal_li_api.h"
#include "hal_li_generic_api.h"
/**
* hal_rx_get_rx_fragment_number_6290(): Function to retrieve rx fragment number
@@ -614,19 +616,26 @@ static uint32_t hal_rx_hw_desc_get_ppduid_get_6290(void *rx_tlv_hdr,
/**
* hal_reo_status_get_header_6290 - Process reo desc info
* @d - Pointer to reo descriptior
* @ring_desc: REO status ring descriptor
* @b - tlv type info
* @h1 - Pointer to hal_reo_status_header where info to be stored
*
* Return - none.
*
*/
static void hal_reo_status_get_header_6290(uint32_t *d, int b, void *h1)
static void hal_reo_status_get_header_6290(hal_ring_desc_t ring_desc, int b,
void *h1)
{
uint32_t *d = (uint32_t *)ring_desc;
uint32_t val1 = 0;
struct hal_reo_status_header *h =
(struct hal_reo_status_header *)h1;
/* Offsets of descriptor fields defined in HW headers start
* from the field after TLV header
*/
d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr));
switch (b) {
case HAL_REO_QUEUE_STATS_STATUS_TLV:
val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
@@ -1044,8 +1053,7 @@ static void hal_hw_txrx_ops_attach_6290(struct hal_soc *hal_soc)
hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic;
hal_soc->ops->hal_setup_link_idle_list = hal_setup_link_idle_list_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li;
hal_soc->ops->hal_get_window_address = hal_get_window_address_6290;
/* tx */
@@ -1054,104 +1062,152 @@ static void hal_hw_txrx_ops_attach_6290(struct hal_soc *hal_soc)
hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6290;
hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6290;
hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6290;
hal_soc->ops->hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic;
hal_soc->ops->hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic;
hal_soc->ops->hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic;
hal_soc->ops->hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic;
hal_soc->ops->hal_tx_comp_get_status = hal_tx_comp_get_status_generic;
hal_soc->ops->hal_tx_desc_set_buf_addr =
hal_tx_desc_set_buf_addr_generic_li;
hal_soc->ops->hal_tx_desc_set_search_type =
hal_tx_desc_set_search_type_generic_li;
hal_soc->ops->hal_tx_desc_set_search_index =
hal_tx_desc_set_search_index_generic_li;
hal_soc->ops->hal_tx_desc_set_cache_set_num =
hal_tx_desc_set_cache_set_num_generic_li;
hal_soc->ops->hal_tx_comp_get_status =
hal_tx_comp_get_status_generic_li;
hal_soc->ops->hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic;
hal_soc->ops->hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic;
hal_tx_comp_get_release_reason_generic_li;
hal_soc->ops->hal_get_wbm_internal_error =
hal_get_wbm_internal_error_generic_li;
hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6290;
hal_soc->ops->hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_6290;
hal_soc->ops->hal_tx_init_cmd_credit_ring =
hal_tx_init_cmd_credit_ring_6290;
/* rx */
hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_6290;
hal_soc->ops->hal_rx_msdu_start_nss_get =
hal_rx_msdu_start_nss_get_6290;
hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_6290;
hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6290;
hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_6290;
hal_soc->ops->hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_6290;
hal_soc->ops->hal_rx_dump_msdu_start_tlv =
hal_rx_dump_msdu_start_tlv_6290;
hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6290;
hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6290;
hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_6290;
hal_soc->ops->hal_rx_mpdu_start_tid_get =
hal_rx_mpdu_start_tid_get_6290;
hal_soc->ops->hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_6290;
hal_soc->ops->hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_6290;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_6290;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_6290;
hal_soc->ops->hal_reo_status_get_header = hal_reo_status_get_header_6290;
hal_soc->ops->hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic;
hal_soc->ops->hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic;
hal_soc->ops->hal_rx_msdu_end_da_idx_get =
hal_rx_msdu_end_da_idx_get_6290;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
hal_rx_msdu_desc_info_get_ptr_6290;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
hal_rx_link_desc_msdu0_ptr_6290;
hal_soc->ops->hal_reo_status_get_header =
hal_reo_status_get_header_6290;
hal_soc->ops->hal_rx_status_get_tlv_info =
hal_rx_status_get_tlv_info_generic_li;
hal_soc->ops->hal_rx_wbm_err_info_get =
hal_rx_wbm_err_info_get_generic_li;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
hal_rx_dump_mpdu_start_tlv_generic_li;
hal_soc->ops->hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic;
hal_soc->ops->hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic;
hal_soc->ops->hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic;
hal_soc->ops->hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_6290;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_6290;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = hal_rx_msdu_end_sa_is_valid_get_6290;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_6290;
hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_6290;
hal_soc->ops->hal_tx_set_pcp_tid_map =
hal_tx_set_pcp_tid_map_generic_li;
hal_soc->ops->hal_tx_update_pcp_tid_map =
hal_tx_update_pcp_tid_generic_li;
hal_soc->ops->hal_tx_set_tidmap_prty =
hal_tx_update_tidmap_prty_generic_li;
hal_soc->ops->hal_rx_get_rx_fragment_number =
hal_rx_get_rx_fragment_number_6290;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
hal_rx_msdu_end_da_is_mcbc_get_6290;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
hal_rx_msdu_end_sa_is_valid_get_6290;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
hal_rx_msdu_end_sa_idx_get_6290;
hal_soc->ops->hal_rx_desc_is_first_msdu =
hal_rx_desc_is_first_msdu_6290;
hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_6290;
hal_soc->ops->hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_6290;
hal_rx_msdu_end_l3_hdr_padding_get_6290;
hal_soc->ops->hal_rx_encryption_info_valid =
hal_rx_encryption_info_valid_6290;
hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6290;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_6290;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = hal_rx_msdu_end_da_is_valid_get_6290;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_6290;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_6290;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
hal_rx_msdu_end_first_msdu_get_6290;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
hal_rx_msdu_end_da_is_valid_get_6290;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
hal_rx_msdu_end_last_msdu_get_6290;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
hal_rx_get_mpdu_mac_ad4_valid_6290;
hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_6290;
hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6290;
hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6290;
hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_6290;
hal_rx_get_mpdu_frame_control_valid_6290;
hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6290;
hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6290;
hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6290;
hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6290;
hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
hal_rx_get_mpdu_sequence_control_valid_6290;
hal_rx_get_mpdu_sequence_control_valid_6290;
hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6290;
hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6290;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_6290;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
hal_rx_hw_desc_get_ppduid_get_6290;
hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290;
hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
hal_rx_msdu_end_sa_sw_peer_id_get_6290;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_6290;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_6290;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
hal_rx_msdu0_buffer_addr_lsb_6290;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
hal_rx_msdu_desc_info_ptr_get_6290;
hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6290;
hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6290;
hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6290;
hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6290;
hal_soc->ops->hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_6290;
hal_soc->ops->hal_rx_get_filter_category = hal_rx_get_filter_category_6290;
hal_soc->ops->hal_rx_get_mac_addr2_valid =
hal_rx_get_mac_addr2_valid_6290;
hal_soc->ops->hal_rx_get_filter_category =
hal_rx_get_filter_category_6290;
hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6290;
hal_soc->ops->hal_reo_config = hal_reo_config_6290;
hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6290;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_6290;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_6290;
hal_soc->ops->hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_6290;
hal_soc->ops->hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_6290;
hal_soc->ops->hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_6290;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_6290;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
hal_rx_msdu_flow_idx_invalid_6290;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
hal_rx_msdu_flow_idx_timeout_6290;
hal_soc->ops->hal_rx_msdu_fse_metadata_get =
hal_rx_msdu_fse_metadata_get_6290;
hal_soc->ops->hal_rx_msdu_cce_metadata_get =
hal_rx_msdu_cce_metadata_get_6290;
hal_soc->ops->hal_rx_msdu_get_flow_params =
hal_rx_msdu_get_flow_params_6290;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
hal_rx_tlv_get_tcp_chksum_6290;
hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6290;
/* rx - msdu end fast path info fields */
hal_soc->ops->hal_rx_msdu_packet_metadata_get =
hal_rx_msdu_packet_metadata_get_generic;
hal_rx_msdu_packet_metadata_get_generic_li;
/* rx - TLV struct offsets */
hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic;
hal_soc->ops->hal_rx_msdu_end_offset_get =
hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_attn_offset_get =
hal_rx_attn_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get =
hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get =
hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get =
hal_rx_mpdu_end_offset_get_generic;
#ifndef NO_RX_PKT_HDR_TLV
hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic;
hal_soc->ops->hal_rx_pkt_tlv_offset_get =
hal_rx_pkt_tlv_offset_get_generic;
#endif
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_6290;
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
hal_compute_reo_remap_ix2_ix3_6290;
};
struct hal_hw_srng_config hw_srng_table_6290[] = {
@@ -1601,5 +1657,7 @@ void hal_qca6290_attach(struct hal_soc *hal_soc)
{
hal_soc->hw_srng_table = hw_srng_table_6290;
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6290;
hal_hw_txrx_default_ops_attach_li(hal_soc);
hal_hw_txrx_ops_attach_6290(hal_soc);
}

4
hal/wifi3.0/qca6290/hal_6290_rx.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@@ -29,7 +29,7 @@
#include "hal_internal.h"
#include "cdp_txrx_mon_struct.h"
#include "qdf_trace.h"
#include "hal_rx.h"
#include "hal_li_rx.h"
#include "hal_tx.h"
#include "dp_types.h"
#include "hal_api_mon.h"

172
hal/wifi3.0/qca6390/hal_6390.c
View File

@@ -21,7 +21,7 @@
#include "qdf_lock.h"
#include "qdf_mem.h"
#include "qdf_nbuf.h"
#include "hal_hw_headers.h"
#include "hal_li_hw_headers.h"
#include "hal_internal.h"
#include "hal_api.h"
#include "target_type.h"
@@ -108,7 +108,9 @@
#include "hal_6390_tx.h"
#include "hal_6390_rx.h"
#include <hal_generic_api.h>
#include <hal_wbm.h>
#include "hal_li_rx.h"
#include "hal_li_api.h"
#include "hal_li_generic_api.h"
/**
* hal_rx_get_rx_fragment_number_6390(): Function to retrieve rx fragment number
@@ -612,19 +614,26 @@ static uint32_t hal_rx_hw_desc_get_ppduid_get_6390(void *rx_tlv_hdr,
/**
* hal_reo_status_get_header_6390 - Process reo desc info
* @d - Pointer to reo descriptior
* @ring_desc: REO status ring descriptor
* @b - tlv type info
* @h1 - Pointer to hal_reo_status_header where info to be stored
*
* Return - none.
*
*/
static void hal_reo_status_get_header_6390(uint32_t *d, int b, void *h1)
static void hal_reo_status_get_header_6390(hal_ring_desc_t ring_desc, int b,
void *h1)
{
uint32_t *d = (uint32_t *)ring_desc;
uint32_t val1 = 0;
struct hal_reo_status_header *h =
(struct hal_reo_status_header *)h1;
/* Offsets of descriptor fields defined in HW headers start
* from the field after TLV header
*/
d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr));
switch (b) {
case HAL_REO_QUEUE_STATS_STATUS_TLV:
val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
@@ -1096,10 +1105,10 @@ static void hal_hw_txrx_ops_attach_qca6390(struct hal_soc *hal_soc)
hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic;
hal_soc->ops->hal_setup_link_idle_list = hal_setup_link_idle_list_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li;
hal_soc->ops->hal_get_window_address = hal_get_window_address_6390;
hal_soc->ops->hal_reo_set_err_dst_remap = hal_reo_set_err_dst_remap_6390;
hal_soc->ops->hal_reo_set_err_dst_remap =
hal_reo_set_err_dst_remap_6390;
/* tx */
hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
@@ -1107,54 +1116,84 @@ static void hal_hw_txrx_ops_attach_qca6390(struct hal_soc *hal_soc)
hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6390;
hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6390;
hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6390;
hal_soc->ops->hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic;
hal_soc->ops->hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic;
hal_soc->ops->hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic;
hal_soc->ops->hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic;
hal_soc->ops->hal_tx_comp_get_status = hal_tx_comp_get_status_generic;
hal_soc->ops->hal_tx_desc_set_buf_addr =
hal_tx_desc_set_buf_addr_generic_li;
hal_soc->ops->hal_tx_desc_set_search_type =
hal_tx_desc_set_search_type_generic_li;
hal_soc->ops->hal_tx_desc_set_search_index =
hal_tx_desc_set_search_index_generic_li;
hal_soc->ops->hal_tx_desc_set_cache_set_num =
hal_tx_desc_set_cache_set_num_generic_li;
hal_soc->ops->hal_tx_comp_get_status =
hal_tx_comp_get_status_generic_li;
hal_soc->ops->hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic;
hal_soc->ops->hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic;
hal_tx_comp_get_release_reason_generic_li;
hal_soc->ops->hal_get_wbm_internal_error =
hal_get_wbm_internal_error_generic_li;
hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6390;
hal_soc->ops->hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_6390;
hal_soc->ops->hal_tx_init_cmd_credit_ring =
hal_tx_init_cmd_credit_ring_6390;
/* rx */
hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_6390;
hal_soc->ops->hal_rx_msdu_start_nss_get =
hal_rx_msdu_start_nss_get_6390;
hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_6390;
hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6390;
hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_6390;
hal_soc->ops->hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_6390;
hal_soc->ops->hal_rx_dump_msdu_start_tlv =
hal_rx_dump_msdu_start_tlv_6390;
hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6390;
hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6390;
hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_6390;
hal_soc->ops->hal_rx_mpdu_start_tid_get =
hal_rx_mpdu_start_tid_get_6390;
hal_soc->ops->hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_6390;
hal_soc->ops->hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_6390;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_6390;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_6390;
hal_soc->ops->hal_reo_status_get_header = hal_reo_status_get_header_6390;
hal_soc->ops->hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic;
hal_soc->ops->hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic;
hal_soc->ops->hal_rx_msdu_end_da_idx_get =
hal_rx_msdu_end_da_idx_get_6390;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
hal_rx_msdu_desc_info_get_ptr_6390;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
hal_rx_link_desc_msdu0_ptr_6390;
hal_soc->ops->hal_reo_status_get_header =
hal_reo_status_get_header_6390;
hal_soc->ops->hal_rx_status_get_tlv_info =
hal_rx_status_get_tlv_info_generic_li;
hal_soc->ops->hal_rx_wbm_err_info_get =
hal_rx_wbm_err_info_get_generic_li;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
hal_rx_dump_mpdu_start_tlv_generic_li;
hal_soc->ops->hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic;
hal_soc->ops->hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic;
hal_soc->ops->hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic;
hal_soc->ops->hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_6390;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_6390;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = hal_rx_msdu_end_sa_is_valid_get_6390;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_6390;
hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_6390;
hal_soc->ops->hal_tx_set_pcp_tid_map =
hal_tx_set_pcp_tid_map_generic_li;
hal_soc->ops->hal_tx_update_pcp_tid_map =
hal_tx_update_pcp_tid_generic_li;
hal_soc->ops->hal_tx_set_tidmap_prty =
hal_tx_update_tidmap_prty_generic_li;
hal_soc->ops->hal_rx_get_rx_fragment_number =
hal_rx_get_rx_fragment_number_6390;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
hal_rx_msdu_end_da_is_mcbc_get_6390;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
hal_rx_msdu_end_sa_is_valid_get_6390;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
hal_rx_msdu_end_sa_idx_get_6390;
hal_soc->ops->hal_rx_desc_is_first_msdu =
hal_rx_desc_is_first_msdu_6390;
hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_6390;
hal_soc->ops->hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_6390;
hal_soc->ops->hal_rx_encryption_info_valid =
hal_rx_encryption_info_valid_6390;
hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6390;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_6390;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = hal_rx_msdu_end_da_is_valid_get_6390;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_6390;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_6390;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
hal_rx_msdu_end_first_msdu_get_6390;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
hal_rx_msdu_end_da_is_valid_get_6390;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
hal_rx_msdu_end_last_msdu_get_6390;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
hal_rx_get_mpdu_mac_ad4_valid_6390;
hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_6390;
hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6390;
@@ -1169,44 +1208,62 @@ static void hal_hw_txrx_ops_attach_qca6390(struct hal_soc *hal_soc)
hal_rx_get_mpdu_sequence_control_valid_6390;
hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6390;
hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6390;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_6390;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
hal_rx_hw_desc_get_ppduid_get_6390;
hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390;
hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
hal_rx_msdu_end_sa_sw_peer_id_get_6390;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_6390;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_6390;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
hal_rx_msdu0_buffer_addr_lsb_6390;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
hal_rx_msdu_desc_info_ptr_get_6390;
hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6390;
hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6390;
hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6390;
hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6390;
hal_soc->ops->hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_6390;
hal_soc->ops->hal_rx_get_filter_category = hal_rx_get_filter_category_6390;
hal_soc->ops->hal_rx_get_mac_addr2_valid =
hal_rx_get_mac_addr2_valid_6390;
hal_soc->ops->hal_rx_get_filter_category =
hal_rx_get_filter_category_6390;
hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6390;
hal_soc->ops->hal_reo_config = hal_reo_config_6390;
hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6390;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_6390;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_6390;
hal_soc->ops->hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_6390;
hal_soc->ops->hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_6390;
hal_soc->ops->hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_6390;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_6390;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
hal_rx_msdu_flow_idx_invalid_6390;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
hal_rx_msdu_flow_idx_timeout_6390;
hal_soc->ops->hal_rx_msdu_fse_metadata_get =
hal_rx_msdu_fse_metadata_get_6390;
hal_soc->ops->hal_rx_msdu_cce_metadata_get =
hal_rx_msdu_cce_metadata_get_6390;
hal_soc->ops->hal_rx_msdu_get_flow_params =
hal_rx_msdu_get_flow_params_6390;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
hal_rx_tlv_get_tcp_chksum_6390;
hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6390;
/* rx - msdu end fast path info fields */
hal_soc->ops->hal_rx_msdu_packet_metadata_get =
hal_rx_msdu_packet_metadata_get_generic;
hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = hal_rx_mpdu_start_tlv_tag_valid_6390;
hal_rx_msdu_packet_metadata_get_generic_li;
hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
hal_rx_mpdu_start_tlv_tag_valid_6390;
/* rx - TLV struct offsets */
hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_msdu_end_offset_get =
hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get =
hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get =
hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get =
hal_rx_mpdu_end_offset_get_generic;
#ifndef NO_RX_PKT_HDR_TLV
hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic;
hal_soc->ops->hal_rx_pkt_tlv_offset_get =
hal_rx_pkt_tlv_offset_get_generic;
#endif
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_6390;
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
hal_compute_reo_remap_ix2_ix3_6390;
};
struct hal_hw_srng_config hw_srng_table_6390[] = {
@@ -1668,5 +1725,6 @@ void hal_qca6390_attach(struct hal_soc *hal_soc)
{
hal_soc->hw_srng_table = hw_srng_table_6390;
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6390;
hal_hw_txrx_default_ops_attach_li(hal_soc);
hal_hw_txrx_ops_attach_qca6390(hal_soc);
}

4
hal/wifi3.0/qca6390/hal_6390_rx.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@@ -29,7 +29,7 @@
#include "hal_internal.h"
#include "cdp_txrx_mon_struct.h"
#include "qdf_trace.h"
#include "hal_rx.h"
#include "hal_li_rx.h"
#include "hal_tx.h"
#include "dp_types.h"
#include "hal_api_mon.h"

171
hal/wifi3.0/qca6490/hal_6490.c
View File

@@ -22,7 +22,7 @@
#include "qdf_lock.h"
#include "qdf_mem.h"
#include "qdf_nbuf.h"
#include "hal_hw_headers.h"
#include "hal_li_hw_headers.h"
#include "hal_internal.h"
#include "hal_api.h"
#include "target_type.h"
@@ -113,7 +113,9 @@
#include "hal_6490_tx.h"
#include "hal_6490_rx.h"
#include <hal_generic_api.h>
#include <hal_wbm.h>
#include "hal_li_rx.h"
#include "hal_li_api.h"
#include "hal_li_generic_api.h"
/*
* hal_rx_msdu_start_nss_get_6490(): API to get the NSS
@@ -995,19 +997,26 @@ static uint32_t hal_rx_hw_desc_get_ppduid_get_6490(void *rx_tlv_hdr,
/**
* hal_reo_status_get_header_6490 - Process reo desc info
* @d - Pointer to reo descriptior
* @ring_desc: REO status ring descriptor
* @b - tlv type info
* @h1 - Pointer to hal_reo_status_header where info to be stored
*
* Return - none.
*
*/
static void hal_reo_status_get_header_6490(uint32_t *d, int b, void *h1)
static void hal_reo_status_get_header_6490(hal_ring_desc_t ring_desc, int b,
void *h1)
{
uint32_t *d = (uint32_t *)ring_desc;
uint32_t val1 = 0;
struct hal_reo_status_header *h =
(struct hal_reo_status_header *)h1;
/* Offsets of descriptor fields defined in HW headers start
* from the field after TLV header
*/
d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr));
switch (b) {
case HAL_REO_QUEUE_STATS_STATUS_TLV:
val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
@@ -1672,10 +1681,10 @@ static void hal_hw_txrx_ops_attach_qca6490(struct hal_soc *hal_soc)
hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic;
hal_soc->ops->hal_setup_link_idle_list = hal_setup_link_idle_list_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li;
hal_soc->ops->hal_get_window_address = hal_get_window_address_6490;
hal_soc->ops->hal_reo_set_err_dst_remap = hal_reo_set_err_dst_remap_6490;
hal_soc->ops->hal_reo_set_err_dst_remap =
hal_reo_set_err_dst_remap_6490;
/* tx */
hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
@@ -1683,56 +1692,84 @@ static void hal_hw_txrx_ops_attach_qca6490(struct hal_soc *hal_soc)
hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6490;
hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6490;
hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6490;
hal_soc->ops->hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic;
hal_soc->ops->hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic;
hal_soc->ops->hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic;
hal_soc->ops->hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic;
hal_soc->ops->hal_tx_comp_get_status = hal_tx_comp_get_status_generic;
hal_soc->ops->hal_tx_desc_set_buf_addr =
hal_tx_desc_set_buf_addr_generic_li;
hal_soc->ops->hal_tx_desc_set_search_type =
hal_tx_desc_set_search_type_generic_li;
hal_soc->ops->hal_tx_desc_set_search_index =
hal_tx_desc_set_search_index_generic_li;
hal_soc->ops->hal_tx_desc_set_cache_set_num =
hal_tx_desc_set_cache_set_num_generic_li;
hal_soc->ops->hal_tx_comp_get_status =
hal_tx_comp_get_status_generic_li;
hal_soc->ops->hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic;
hal_soc->ops->hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic;
hal_tx_comp_get_release_reason_generic_li;
hal_soc->ops->hal_get_wbm_internal_error =
hal_get_wbm_internal_error_generic_li;
hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6490;
hal_soc->ops->hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_6490;
hal_soc->ops->hal_tx_init_cmd_credit_ring =
hal_tx_init_cmd_credit_ring_6490;
/* rx */
hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_6490;
hal_soc->ops->hal_rx_msdu_start_nss_get =
hal_rx_msdu_start_nss_get_6490;
hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_6490;
hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6490;
hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_6490;
hal_soc->ops->hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_6490;
hal_soc->ops->hal_rx_dump_msdu_start_tlv =
hal_rx_dump_msdu_start_tlv_6490;
hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6490;
hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6490;
hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_6490;
hal_soc->ops->hal_rx_mpdu_start_tid_get =
hal_rx_mpdu_start_tid_get_6490;
hal_soc->ops->hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_6490;
hal_soc->ops->hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_6490;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_6490;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_6490;
hal_soc->ops->hal_reo_status_get_header = hal_reo_status_get_header_6490;
hal_soc->ops->hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic;
hal_soc->ops->hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic;
hal_soc->ops->hal_rx_msdu_end_da_idx_get =
hal_rx_msdu_end_da_idx_get_6490;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
hal_rx_msdu_desc_info_get_ptr_6490;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
hal_rx_link_desc_msdu0_ptr_6490;
hal_soc->ops->hal_reo_status_get_header =
hal_reo_status_get_header_6490;
hal_soc->ops->hal_rx_status_get_tlv_info =
hal_rx_status_get_tlv_info_generic_li;
hal_soc->ops->hal_rx_wbm_err_info_get =
hal_rx_wbm_err_info_get_generic_li;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
hal_rx_dump_mpdu_start_tlv_generic_li;
hal_soc->ops->hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic;
hal_soc->ops->hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic;
hal_soc->ops->hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic;
hal_soc->ops->hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_6490;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_6490;
hal_soc->ops->hal_tx_set_pcp_tid_map =
hal_tx_set_pcp_tid_map_generic_li;
hal_soc->ops->hal_tx_update_pcp_tid_map =
hal_tx_update_pcp_tid_generic_li;
hal_soc->ops->hal_tx_set_tidmap_prty =
hal_tx_update_tidmap_prty_generic_li;
hal_soc->ops->hal_rx_get_rx_fragment_number =
hal_rx_get_rx_fragment_number_6490;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
hal_rx_msdu_end_da_is_mcbc_get_6490;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
hal_rx_msdu_end_sa_is_valid_get_6490;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_6490;
hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_6490;
hal_rx_msdu_end_sa_is_valid_get_6490;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
hal_rx_msdu_end_sa_idx_get_6490;
hal_soc->ops->hal_rx_desc_is_first_msdu =
hal_rx_desc_is_first_msdu_6490;
hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_6490;
hal_soc->ops->hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_6490;
hal_soc->ops->hal_rx_encryption_info_valid =
hal_rx_encryption_info_valid_6490;
hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6490;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_6490;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
hal_rx_msdu_end_first_msdu_get_6490;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
hal_rx_msdu_end_da_is_valid_get_6490;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_6490;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_6490;
hal_rx_msdu_end_da_is_valid_get_6490;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
hal_rx_msdu_end_last_msdu_get_6490;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
hal_rx_get_mpdu_mac_ad4_valid_6490;
hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_6490;
hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6490;
@@ -1747,24 +1784,35 @@ static void hal_hw_txrx_ops_attach_qca6490(struct hal_soc *hal_soc)
hal_rx_get_mpdu_sequence_control_valid_6490;
hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6490;
hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6490;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_6490;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_6490;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_6490;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
hal_rx_hw_desc_get_ppduid_get_6490;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
hal_rx_msdu0_buffer_addr_lsb_6490;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
hal_rx_msdu_desc_info_ptr_get_6490;
hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6490;
hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6490;
hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6490;
hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6490;
hal_soc->ops->hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_6490;
hal_soc->ops->hal_rx_get_filter_category = hal_rx_get_filter_category_6490;
hal_soc->ops->hal_rx_get_mac_addr2_valid =
hal_rx_get_mac_addr2_valid_6490;
hal_soc->ops->hal_rx_get_filter_category =
hal_rx_get_filter_category_6490;
hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6490;
hal_soc->ops->hal_reo_config = hal_reo_config_6490;
hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6490;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_6490;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_6490;
hal_soc->ops->hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_6490;
hal_soc->ops->hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_6490;
hal_soc->ops->hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_6490;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_6490;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
hal_rx_msdu_flow_idx_invalid_6490;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
hal_rx_msdu_flow_idx_timeout_6490;
hal_soc->ops->hal_rx_msdu_fse_metadata_get =
hal_rx_msdu_fse_metadata_get_6490;
hal_soc->ops->hal_rx_msdu_cce_metadata_get =
hal_rx_msdu_cce_metadata_get_6490;
hal_soc->ops->hal_rx_msdu_get_flow_params =
hal_rx_msdu_get_flow_params_6490;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
hal_rx_tlv_get_tcp_chksum_6490;
hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6490;
#if defined(QCA_WIFI_QCA6490) && defined(WLAN_CFR_ENABLE) && \
defined(WLAN_ENH_CFR_ENABLE)
@@ -1773,7 +1821,7 @@ static void hal_hw_txrx_ops_attach_qca6490(struct hal_soc *hal_soc)
#endif
/* rx - msdu end fast path info fields */
hal_soc->ops->hal_rx_msdu_packet_metadata_get =
hal_rx_msdu_packet_metadata_get_generic;
hal_rx_msdu_packet_metadata_get_generic_li;
hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum =
hal_rx_get_fisa_cumulative_l4_checksum_6490;
hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length =
@@ -1781,22 +1829,29 @@ static void hal_hw_txrx_ops_attach_qca6490(struct hal_soc *hal_soc)
hal_soc->ops->hal_rx_get_udp_proto = hal_rx_get_udp_proto_6490;
hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation =
hal_rx_get_flow_agg_continuation_6490;
hal_soc->ops->hal_rx_get_fisa_flow_agg_count = hal_rx_get_flow_agg_count_6490;
hal_soc->ops->hal_rx_get_fisa_flow_agg_count =
hal_rx_get_flow_agg_count_6490;
hal_soc->ops->hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_6490;
hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
hal_rx_mpdu_start_tlv_tag_valid_6490;
/* rx - TLV struct offsets */
hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_msdu_end_offset_get =
hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get =
hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get =
hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get =
hal_rx_mpdu_end_offset_get_generic;
#ifndef NO_RX_PKT_HDR_TLV
hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic;
hal_soc->ops->hal_rx_pkt_tlv_offset_get =
hal_rx_pkt_tlv_offset_get_generic;
#endif
hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6490;
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_6490;
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
hal_compute_reo_remap_ix2_ix3_6490;
hal_soc->ops->hal_rx_msdu_get_reo_destination_indication =
hal_rx_msdu_get_reo_destination_indication_6490;
};
@@ -2260,5 +2315,7 @@ void hal_qca6490_attach(struct hal_soc *hal_soc)
{
hal_soc->hw_srng_table = hw_srng_table_6490;
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6490;
hal_hw_txrx_default_ops_attach_li(hal_soc);
hal_hw_txrx_ops_attach_qca6490(hal_soc);
}

178
hal/wifi3.0/qca6750/hal_6750.c
View File

@@ -22,7 +22,7 @@
#include "qdf_lock.h"
#include "qdf_mem.h"
#include "qdf_nbuf.h"
#include "hal_hw_headers.h"
#include "hal_li_hw_headers.h"
#include "hal_internal.h"
#include "hal_api.h"
#include "target_type.h"
@@ -113,7 +113,9 @@
#include "hal_6750_tx.h"
#include "hal_6750_rx.h"
#include <hal_generic_api.h>
#include <hal_wbm.h>
#include "hal_li_rx.h"
#include "hal_li_api.h"
#include "hal_li_generic_api.h"
/*
* hal_rx_msdu_start_nss_get_6750(): API to get the NSS
@@ -990,19 +992,26 @@ static uint32_t hal_rx_hw_desc_get_ppduid_get_6750(void *rx_tlv_hdr,
/**
* hal_reo_status_get_header_6750 - Process reo desc info
* @d - Pointer to reo descriptior
* @ring_desc: REO status ring descriptor
* @b - tlv type info
* @h1 - Pointer to hal_reo_status_header where info to be stored
*
* Return - none.
*
*/
static void hal_reo_status_get_header_6750(uint32_t *d, int b, void *h1)
static void hal_reo_status_get_header_6750(hal_ring_desc_t ring_desc, int b,
void *h1)
{
uint32_t *d = (uint32_t *)ring_desc;
uint32_t val1 = 0;
struct hal_reo_status_header *h =
(struct hal_reo_status_header *)h1;
/* Offsets of descriptor fields defined in HW headers start
* from the field after TLV header
*/
d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr));
switch (b) {
case HAL_REO_QUEUE_STATS_STATUS_TLV:
val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
@@ -1830,8 +1839,7 @@ static void hal_hw_txrx_ops_attach_qca6750(struct hal_soc *hal_soc)
hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic;
hal_soc->ops->hal_setup_link_idle_list = hal_setup_link_idle_list_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li;
hal_soc->ops->hal_get_window_address = hal_get_window_address_6750;
hal_soc->ops->hal_reo_set_err_dst_remap = hal_reo_set_err_dst_remap_6750;
@@ -1841,54 +1849,84 @@ static void hal_hw_txrx_ops_attach_qca6750(struct hal_soc *hal_soc)
hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6750;
hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6750;
hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6750;
hal_soc->ops->hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic;
hal_soc->ops->hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic;
hal_soc->ops->hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic;
hal_soc->ops->hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic;
hal_soc->ops->hal_tx_comp_get_status = hal_tx_comp_get_status_generic;
hal_soc->ops->hal_tx_desc_set_buf_addr =
hal_tx_desc_set_buf_addr_generic_li;
hal_soc->ops->hal_tx_desc_set_search_type =
hal_tx_desc_set_search_type_generic_li;
hal_soc->ops->hal_tx_desc_set_search_index =
hal_tx_desc_set_search_index_generic_li;
hal_soc->ops->hal_tx_desc_set_cache_set_num =
hal_tx_desc_set_cache_set_num_generic_li;
hal_soc->ops->hal_tx_comp_get_status =
hal_tx_comp_get_status_generic_li;
hal_soc->ops->hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic;
hal_soc->ops->hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic;
hal_tx_comp_get_release_reason_generic_li;
hal_soc->ops->hal_get_wbm_internal_error =
hal_get_wbm_internal_error_generic_li;
hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6750;
hal_soc->ops->hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_6750;
hal_soc->ops->hal_tx_init_cmd_credit_ring =
hal_tx_init_cmd_credit_ring_6750;
/* rx */
hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_6750;
hal_soc->ops->hal_rx_msdu_start_nss_get =
hal_rx_msdu_start_nss_get_6750;
hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_6750;
hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6750;
hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_6750;
hal_soc->ops->hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_6750;
hal_soc->ops->hal_rx_dump_msdu_start_tlv =
hal_rx_dump_msdu_start_tlv_6750;
hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6750;
hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6750;
hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_6750;
hal_soc->ops->hal_rx_mpdu_start_tid_get =
hal_rx_mpdu_start_tid_get_6750;
hal_soc->ops->hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_6750;
hal_soc->ops->hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_6750;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_6750;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_6750;
hal_soc->ops->hal_reo_status_get_header = hal_reo_status_get_header_6750;
hal_soc->ops->hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic;
hal_soc->ops->hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic;
hal_soc->ops->hal_rx_msdu_end_da_idx_get =
hal_rx_msdu_end_da_idx_get_6750;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
hal_rx_msdu_desc_info_get_ptr_6750;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
hal_rx_link_desc_msdu0_ptr_6750;
hal_soc->ops->hal_reo_status_get_header =
hal_reo_status_get_header_6750;
hal_soc->ops->hal_rx_status_get_tlv_info =
hal_rx_status_get_tlv_info_generic_li;
hal_soc->ops->hal_rx_wbm_err_info_get =
hal_rx_wbm_err_info_get_generic_li;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
hal_rx_dump_mpdu_start_tlv_generic_li;
hal_soc->ops->hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic;
hal_soc->ops->hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic;
hal_soc->ops->hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic;
hal_soc->ops->hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_6750;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_6750;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = hal_rx_msdu_end_sa_is_valid_get_6750;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_6750;
hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_6750;
hal_soc->ops->hal_tx_set_pcp_tid_map =
hal_tx_set_pcp_tid_map_generic_li;
hal_soc->ops->hal_tx_update_pcp_tid_map =
hal_tx_update_pcp_tid_generic_li;
hal_soc->ops->hal_tx_set_tidmap_prty =
hal_tx_update_tidmap_prty_generic_li;
hal_soc->ops->hal_rx_get_rx_fragment_number =
hal_rx_get_rx_fragment_number_6750;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
hal_rx_msdu_end_da_is_mcbc_get_6750;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
hal_rx_msdu_end_sa_is_valid_get_6750;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
hal_rx_msdu_end_sa_idx_get_6750;
hal_soc->ops->hal_rx_desc_is_first_msdu =
hal_rx_desc_is_first_msdu_6750;
hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_6750;
hal_soc->ops->hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_6750;
hal_soc->ops->hal_rx_encryption_info_valid =
hal_rx_encryption_info_valid_6750;
hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6750;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_6750;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = hal_rx_msdu_end_da_is_valid_get_6750;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_6750;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_6750;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
hal_rx_msdu_end_first_msdu_get_6750;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
hal_rx_msdu_end_da_is_valid_get_6750;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
hal_rx_msdu_end_last_msdu_get_6750;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
hal_rx_get_mpdu_mac_ad4_valid_6750;
hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_6750;
hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6750;
@@ -1903,24 +1941,35 @@ static void hal_hw_txrx_ops_attach_qca6750(struct hal_soc *hal_soc)
hal_rx_get_mpdu_sequence_control_valid_6750;
hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6750;
hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6750;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_6750;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_6750;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_6750;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
hal_rx_hw_desc_get_ppduid_get_6750;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
hal_rx_msdu0_buffer_addr_lsb_6750;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
hal_rx_msdu_desc_info_ptr_get_6750;
hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6750;
hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6750;
hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6750;
hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6750;
hal_soc->ops->hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_6750;
hal_soc->ops->hal_rx_get_filter_category = hal_rx_get_filter_category_6750;
hal_soc->ops->hal_rx_get_mac_addr2_valid =
hal_rx_get_mac_addr2_valid_6750;
hal_soc->ops->hal_rx_get_filter_category =
hal_rx_get_filter_category_6750;
hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6750;
hal_soc->ops->hal_reo_config = hal_reo_config_6750;
hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6750;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_6750;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_6750;
hal_soc->ops->hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_6750;
hal_soc->ops->hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_6750;
hal_soc->ops->hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_6750;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_6750;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
hal_rx_msdu_flow_idx_invalid_6750;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
hal_rx_msdu_flow_idx_timeout_6750;
hal_soc->ops->hal_rx_msdu_fse_metadata_get =
hal_rx_msdu_fse_metadata_get_6750;
hal_soc->ops->hal_rx_msdu_cce_metadata_get =
hal_rx_msdu_cce_metadata_get_6750;
hal_soc->ops->hal_rx_msdu_get_flow_params =
hal_rx_msdu_get_flow_params_6750;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
hal_rx_tlv_get_tcp_chksum_6750;
hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6750;
#if defined(QCA_WIFI_QCA6750) && defined(WLAN_CFR_ENABLE) && \
defined(WLAN_ENH_CFR_ENABLE)
@@ -1929,7 +1978,7 @@ static void hal_hw_txrx_ops_attach_qca6750(struct hal_soc *hal_soc)
#endif
/* rx - msdu end fast path info fields */
hal_soc->ops->hal_rx_msdu_packet_metadata_get =
hal_rx_msdu_packet_metadata_get_generic;
hal_rx_msdu_packet_metadata_get_generic_li;
hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum =
hal_rx_get_fisa_cumulative_l4_checksum_6750;
hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length =
@@ -1937,25 +1986,35 @@ static void hal_hw_txrx_ops_attach_qca6750(struct hal_soc *hal_soc)
hal_soc->ops->hal_rx_get_udp_proto = hal_rx_get_udp_proto_6750;
hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation =
hal_rx_get_flow_agg_continuation_6750;
hal_soc->ops->hal_rx_get_fisa_flow_agg_count = hal_rx_get_flow_agg_count_6750;
hal_soc->ops->hal_rx_get_fisa_flow_agg_count =
hal_rx_get_flow_agg_count_6750;
hal_soc->ops->hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_6750;
hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = hal_rx_mpdu_start_tlv_tag_valid_6750;
hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
hal_rx_mpdu_start_tlv_tag_valid_6750;
/* rx - TLV struct offsets */
hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_msdu_end_offset_get =
hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get =
hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get =
hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get =
hal_rx_mpdu_end_offset_get_generic;
#ifndef NO_RX_PKT_HDR_TLV
hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic;
hal_soc->ops->hal_rx_pkt_tlv_offset_get =
hal_rx_pkt_tlv_offset_get_generic;
#endif
hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6750;
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_6750;
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
hal_compute_reo_remap_ix2_ix3_6750;
/* CMEM FSE */
hal_soc->ops->hal_rx_flow_setup_cmem_fse = hal_rx_flow_setup_cmem_fse_6750;
hal_soc->ops->hal_rx_flow_get_cmem_fse_ts = hal_rx_flow_get_cmem_fse_ts_6750;
hal_soc->ops->hal_rx_flow_setup_cmem_fse =
hal_rx_flow_setup_cmem_fse_6750;
hal_soc->ops->hal_rx_flow_get_cmem_fse_ts =
hal_rx_flow_get_cmem_fse_ts_6750;
hal_soc->ops->hal_rx_flow_get_cmem_fse = hal_rx_flow_get_cmem_fse_6750;
hal_soc->ops->hal_rx_msdu_get_reo_destination_indication =
hal_rx_msdu_get_reo_destination_indication_6750;
@@ -2410,5 +2469,6 @@ void hal_qca6750_attach(struct hal_soc *hal_soc)
{
hal_soc->hw_srng_table = hw_srng_table_6750;
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6750;
hal_hw_txrx_default_ops_attach_li(hal_soc);
hal_hw_txrx_ops_attach_qca6750(hal_soc);
}

167
hal/wifi3.0/qca8074v1/hal_8074v1.c
View File

@@ -15,7 +15,7 @@
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#include "hal_hw_headers.h"
#include "hal_li_hw_headers.h"
#include "hal_internal.h"
#include "hal_api.h"
#include "target_type.h"
@@ -105,7 +105,9 @@
#include "hal_8074v1_tx.h"
#include "hal_8074v1_rx.h"
#include <hal_generic_api.h>
#include <hal_wbm.h>
#include "hal_li_rx.h"
#include "hal_li_api.h"
#include "hal_li_generic_api.h"
/**
* hal_get_window_address_8074(): Function to get hp/tp address
@@ -625,19 +627,26 @@ static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v1(void *rx_tlv_hdr,
/**
* hal_reo_status_get_header_8074v1 - Process reo desc info
* @d - Pointer to reo descriptior
* @ring_desc: REO status ring descriptor
* @b - tlv type info
* @h1 - Pointer to hal_reo_status_header where info to be stored
*
* Return - none.
*
*/
static void hal_reo_status_get_header_8074v1(uint32_t *d, int b, void *h1)
static void hal_reo_status_get_header_8074v1(hal_ring_desc_t ring_desc, int b,
void *h1)
{
uint32_t *d = (uint32_t *)ring_desc;
uint32_t val1 = 0;
struct hal_reo_status_header *h =
(struct hal_reo_status_header *)h1;
/* Offsets of descriptor fields defined in HW headers start
* from the field after TLV header
*/
d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr));
switch (b) {
case HAL_REO_QUEUE_STATS_STATUS_TLV:
val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
@@ -1219,8 +1228,7 @@ static void hal_hw_txrx_ops_attach_qca8074(struct hal_soc *hal_soc)
hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic;
hal_soc->ops->hal_setup_link_idle_list = hal_setup_link_idle_list_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li;
hal_soc->ops->hal_get_window_address = hal_get_window_address_8074;
/* tx */
@@ -1229,56 +1237,84 @@ static void hal_hw_txrx_ops_attach_qca8074(struct hal_soc *hal_soc)
hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_8074;
hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_8074;
hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_8074;
hal_soc->ops->hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic;
hal_soc->ops->hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic;
hal_soc->ops->hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic;
hal_soc->ops->hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic;
hal_soc->ops->hal_tx_comp_get_status = hal_tx_comp_get_status_generic;
hal_soc->ops->hal_tx_desc_set_buf_addr =
hal_tx_desc_set_buf_addr_generic_li;
hal_soc->ops->hal_tx_desc_set_search_type =
hal_tx_desc_set_search_type_generic_li;
hal_soc->ops->hal_tx_desc_set_search_index =
hal_tx_desc_set_search_index_generic_li;
hal_soc->ops->hal_tx_desc_set_cache_set_num =
hal_tx_desc_set_cache_set_num_generic_li;
hal_soc->ops->hal_tx_comp_get_status =
hal_tx_comp_get_status_generic_li;
hal_soc->ops->hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic;
hal_soc->ops->hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic;
hal_tx_comp_get_release_reason_generic_li;
hal_soc->ops->hal_get_wbm_internal_error =
hal_get_wbm_internal_error_generic_li;
hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_8074v1;
hal_soc->ops->hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_8074v1;
hal_soc->ops->hal_tx_init_cmd_credit_ring =
hal_tx_init_cmd_credit_ring_8074v1;
/* rx */
hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_8074;
hal_soc->ops->hal_rx_msdu_start_nss_get =
hal_rx_msdu_start_nss_get_8074;
hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_8074;
hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_8074;
hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_8074;
hal_soc->ops->hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_8074;
hal_soc->ops->hal_rx_dump_msdu_start_tlv =
hal_rx_dump_msdu_start_tlv_8074;
hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_8074;
hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_8074;
hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_8074;
hal_soc->ops->hal_rx_mpdu_start_tid_get =
hal_rx_mpdu_start_tid_get_8074;
hal_soc->ops->hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_8074;
hal_soc->ops->hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_8074;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_8074v1;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_8074v1;
hal_soc->ops->hal_reo_status_get_header = hal_reo_status_get_header_8074v1;
hal_soc->ops->hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic;
hal_soc->ops->hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic;
hal_soc->ops->hal_rx_msdu_end_da_idx_get =
hal_rx_msdu_end_da_idx_get_8074;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
hal_rx_msdu_desc_info_get_ptr_8074v1;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
hal_rx_link_desc_msdu0_ptr_8074v1;
hal_soc->ops->hal_reo_status_get_header =
hal_reo_status_get_header_8074v1;
hal_soc->ops->hal_rx_status_get_tlv_info =
hal_rx_status_get_tlv_info_generic_li;
hal_soc->ops->hal_rx_wbm_err_info_get =
hal_rx_wbm_err_info_get_generic_li;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
hal_rx_dump_mpdu_start_tlv_generic_li;
hal_soc->ops->hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic;
hal_soc->ops->hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic;
hal_soc->ops->hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic;
hal_soc->ops->hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_8074v1;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_8074v1;
hal_soc->ops->hal_tx_set_pcp_tid_map =
hal_tx_set_pcp_tid_map_generic_li;
hal_soc->ops->hal_tx_update_pcp_tid_map =
hal_tx_update_pcp_tid_generic_li;
hal_soc->ops->hal_tx_set_tidmap_prty =
hal_tx_update_tidmap_prty_generic_li;
hal_soc->ops->hal_rx_get_rx_fragment_number =
hal_rx_get_rx_fragment_number_8074v1;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
hal_rx_msdu_end_da_is_mcbc_get_8074v1;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
hal_rx_msdu_end_sa_is_valid_get_8074v1;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_8074v1;
hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_8074v1;
hal_rx_msdu_end_sa_is_valid_get_8074v1;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
hal_rx_msdu_end_sa_idx_get_8074v1;
hal_soc->ops->hal_rx_desc_is_first_msdu =
hal_rx_desc_is_first_msdu_8074v1;
hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_8074v1;
hal_soc->ops->hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_8074v1;
hal_soc->ops->hal_rx_encryption_info_valid =
hal_rx_encryption_info_valid_8074v1;
hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_8074v1;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_8074v1;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
hal_rx_msdu_end_first_msdu_get_8074v1;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
hal_rx_msdu_end_da_is_valid_get_8074v1;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_8074v1;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_8074v1;
hal_rx_msdu_end_da_is_valid_get_8074v1;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
hal_rx_msdu_end_last_msdu_get_8074v1;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
hal_rx_get_mpdu_mac_ad4_valid_8074v1;
hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_8074v1;
hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_8074v1;
@@ -1293,46 +1329,64 @@ static void hal_hw_txrx_ops_attach_qca8074(struct hal_soc *hal_soc)
hal_rx_get_mpdu_sequence_control_valid_8074v1;
hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_8074v1;
hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_8074v1;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_8074v1;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
hal_rx_hw_desc_get_ppduid_get_8074v1;
hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1;
hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
hal_rx_msdu_end_sa_sw_peer_id_get_8074v1;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_8074v1;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_8074v1;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
hal_rx_msdu0_buffer_addr_lsb_8074v1;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
hal_rx_msdu_desc_info_ptr_get_8074v1;
hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_8074v1;
hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_8074v1;
hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_8074v1;
hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_8074v1;
hal_soc->ops->hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_8074v1;
hal_soc->ops->hal_rx_get_filter_category = hal_rx_get_filter_category_8074v1;
hal_soc->ops->hal_rx_get_mac_addr2_valid =
hal_rx_get_mac_addr2_valid_8074v1;
hal_soc->ops->hal_rx_get_filter_category =
hal_rx_get_filter_category_8074v1;
hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_8074v1;
hal_soc->ops->hal_reo_config = hal_reo_config_8074v1;
hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_8074v1;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_8074v1;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_8074v1;
hal_soc->ops->hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_8074v1;
hal_soc->ops->hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_8074v1;
hal_soc->ops->hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_8074v1;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_8074v1;
hal_soc->ops->hal_rx_msdu_flow_idx_get =
hal_rx_msdu_flow_idx_get_8074v1;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
hal_rx_msdu_flow_idx_invalid_8074v1;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
hal_rx_msdu_flow_idx_timeout_8074v1;
hal_soc->ops->hal_rx_msdu_fse_metadata_get =
hal_rx_msdu_fse_metadata_get_8074v1;
hal_soc->ops->hal_rx_msdu_cce_metadata_get =
hal_rx_msdu_cce_metadata_get_8074v1;
hal_soc->ops->hal_rx_msdu_get_flow_params =
hal_rx_msdu_get_flow_params_8074v1;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
hal_rx_tlv_get_tcp_chksum_8074v1;
hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_8074v1;
/* rx - msdu fast path info fields */
hal_soc->ops->hal_rx_msdu_packet_metadata_get =
hal_rx_msdu_packet_metadata_get_generic;
hal_rx_msdu_packet_metadata_get_generic_li;
hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
hal_rx_mpdu_start_tlv_tag_valid_8074v1;
/* rx - TLV struct offsets */
hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_msdu_end_offset_get =
hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get =
hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get =
hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get =
hal_rx_mpdu_end_offset_get_generic;
#ifndef NO_RX_PKT_HDR_TLV
hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic;
hal_soc->ops->hal_rx_pkt_tlv_offset_get =
hal_rx_pkt_tlv_offset_get_generic;
#endif
hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_8074v1;
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_8074v1;
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
hal_compute_reo_remap_ix2_ix3_8074v1;
};
struct hal_hw_srng_config hw_srng_table_8074[] = {
@@ -1785,5 +1839,6 @@ void hal_qca8074_attach(struct hal_soc *hal_soc)
{
hal_soc->hw_srng_table = hw_srng_table_8074;
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074;
hal_hw_txrx_default_ops_attach_li(hal_soc);
hal_hw_txrx_ops_attach_qca8074(hal_soc);
}

4
hal/wifi3.0/qca8074v1/hal_8074v1_rx.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@@ -19,7 +19,7 @@
#include "hal_internal.h"
#include "cdp_txrx_mon_struct.h"
#include "qdf_trace.h"
#include "hal_rx.h"
#include "hal_li_rx.h"
#include "hal_tx.h"
#include "dp_types.h"
#include "hal_api_mon.h"

165
hal/wifi3.0/qca8074v2/hal_8074v2.c
View File

@@ -15,7 +15,7 @@
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#include "hal_hw_headers.h"
#include "hal_li_hw_headers.h"
#include "hal_internal.h"
#include "hal_api.h"
#include "target_type.h"
@@ -103,10 +103,13 @@
WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET
#define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB
#include "hal_8074v2_tx.h"
#include "hal_8074v2_rx.h"
#include <hal_generic_api.h>
#include <hal_wbm.h>
#include "hal_li_rx.h"
#include "hal_li_api.h"
#include "hal_li_generic_api.h"
/**
* hal_rx_get_rx_fragment_number_8074v2(): Function to retrieve
@@ -610,19 +613,26 @@ static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v2(void *rx_tlv_hdr,
/**
* hal_reo_status_get_header_8074v2 - Process reo desc info
* @d - Pointer to reo descriptior
* @ring_desc: REO status ring descriptor
* @b - tlv type info
* @h1 - Pointer to hal_reo_status_header where info to be stored
*
* Return - none.
*
*/
static void hal_reo_status_get_header_8074v2(uint32_t *d, int b, void *h1)
static void hal_reo_status_get_header_8074v2(hal_ring_desc_t ring_desc, int b,
void *h1)
{
uint32_t *d = (uint32_t *)ring_desc;
uint32_t val1 = 0;
struct hal_reo_status_header *h =
(struct hal_reo_status_header *)h1;
/* Offsets of descriptor fields defined in HW headers start
* from the field after TLV header
*/
d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr));
switch (b) {
case HAL_REO_QUEUE_STATS_STATUS_TLV:
val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
@@ -1216,8 +1226,7 @@ static void hal_hw_txrx_ops_attach_qca8074v2(struct hal_soc *hal_soc)
hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic;
hal_soc->ops->hal_setup_link_idle_list = hal_setup_link_idle_list_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li;
hal_soc->ops->hal_get_window_address = hal_get_window_address_8074v2;
/* tx */
@@ -1226,56 +1235,84 @@ static void hal_hw_txrx_ops_attach_qca8074v2(struct hal_soc *hal_soc)
hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_8074v2;
hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_8074v2;
hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_8074v2;
hal_soc->ops->hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic;
hal_soc->ops->hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic;
hal_soc->ops->hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic;
hal_soc->ops->hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic;
hal_soc->ops->hal_tx_comp_get_status = hal_tx_comp_get_status_generic;
hal_soc->ops->hal_tx_desc_set_buf_addr =
hal_tx_desc_set_buf_addr_generic_li;
hal_soc->ops->hal_tx_desc_set_search_type =
hal_tx_desc_set_search_type_generic_li;
hal_soc->ops->hal_tx_desc_set_search_index =
hal_tx_desc_set_search_index_generic_li;
hal_soc->ops->hal_tx_desc_set_cache_set_num =
hal_tx_desc_set_cache_set_num_generic_li;
hal_soc->ops->hal_tx_comp_get_status =
hal_tx_comp_get_status_generic_li;
hal_soc->ops->hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic;
hal_soc->ops->hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic;
hal_tx_comp_get_release_reason_generic_li;
hal_soc->ops->hal_get_wbm_internal_error =
hal_get_wbm_internal_error_generic_li;
hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_8074v2;
hal_soc->ops->hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_8074v2;
hal_soc->ops->hal_tx_init_cmd_credit_ring =
hal_tx_init_cmd_credit_ring_8074v2;
/* rx */
hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_8074v2;
hal_soc->ops->hal_rx_msdu_start_nss_get =
hal_rx_msdu_start_nss_get_8074v2;
hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_8074v2;
hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_8074v2;
hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_8074v2;
hal_soc->ops->hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_8074v2;
hal_soc->ops->hal_rx_dump_msdu_start_tlv =
hal_rx_dump_msdu_start_tlv_8074v2;
hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_8074v2;
hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_8074v2;
hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_8074v2;
hal_soc->ops->hal_rx_mpdu_start_tid_get =
hal_rx_mpdu_start_tid_get_8074v2;
hal_soc->ops->hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_8074v2;
hal_soc->ops->hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_8074v2;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_8074v2;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_8074v2;
hal_soc->ops->hal_reo_status_get_header = hal_reo_status_get_header_8074v2;
hal_soc->ops->hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic;
hal_soc->ops->hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic;
hal_soc->ops->hal_rx_msdu_end_da_idx_get =
hal_rx_msdu_end_da_idx_get_8074v2;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
hal_rx_msdu_desc_info_get_ptr_8074v2;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
hal_rx_link_desc_msdu0_ptr_8074v2;
hal_soc->ops->hal_reo_status_get_header =
hal_reo_status_get_header_8074v2;
hal_soc->ops->hal_rx_status_get_tlv_info =
hal_rx_status_get_tlv_info_generic_li;
hal_soc->ops->hal_rx_wbm_err_info_get =
hal_rx_wbm_err_info_get_generic_li;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
hal_rx_dump_mpdu_start_tlv_generic_li;
hal_soc->ops->hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic;
hal_soc->ops->hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic;
hal_soc->ops->hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic;
hal_soc->ops->hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_8074v2;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_8074v2;
hal_soc->ops->hal_tx_set_pcp_tid_map =
hal_tx_set_pcp_tid_map_generic_li;
hal_soc->ops->hal_tx_update_pcp_tid_map =
hal_tx_update_pcp_tid_generic_li;
hal_soc->ops->hal_tx_set_tidmap_prty =
hal_tx_update_tidmap_prty_generic_li;
hal_soc->ops->hal_rx_get_rx_fragment_number =
hal_rx_get_rx_fragment_number_8074v2;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
hal_rx_msdu_end_da_is_mcbc_get_8074v2;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
hal_rx_msdu_end_sa_is_valid_get_8074v2;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_8074v2;
hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_8074v2;
hal_rx_msdu_end_sa_is_valid_get_8074v2;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
hal_rx_msdu_end_sa_idx_get_8074v2;
hal_soc->ops->hal_rx_desc_is_first_msdu =
hal_rx_desc_is_first_msdu_8074v2;
hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_8074v2;
hal_soc->ops->hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_8074v2;
hal_soc->ops->hal_rx_encryption_info_valid =
hal_rx_encryption_info_valid_8074v2;
hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_8074v2;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_8074v2;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
hal_rx_msdu_end_first_msdu_get_8074v2;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
hal_rx_msdu_end_da_is_valid_get_8074v2;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_8074v2;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_8074v2;
hal_rx_msdu_end_da_is_valid_get_8074v2;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
hal_rx_msdu_end_last_msdu_get_8074v2;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
hal_rx_get_mpdu_mac_ad4_valid_8074v2;
hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_8074v2;
hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_8074v2;
@@ -1290,28 +1327,39 @@ static void hal_hw_txrx_ops_attach_qca8074v2(struct hal_soc *hal_soc)
hal_rx_get_mpdu_sequence_control_valid_8074v2;
hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_8074v2;
hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_8074v2;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_8074v2;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
hal_rx_hw_desc_get_ppduid_get_8074v2;
hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2;
hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
hal_rx_msdu_end_sa_sw_peer_id_get_8074v2;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_8074v2;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_8074v2;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
hal_rx_msdu0_buffer_addr_lsb_8074v2;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
hal_rx_msdu_desc_info_ptr_get_8074v2;
hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_8074v2;
hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_8074v2;
hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_8074v2;
hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_8074v2;
hal_soc->ops->hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_8074v2;
hal_soc->ops->hal_rx_get_filter_category = hal_rx_get_filter_category_8074v2;
hal_soc->ops->hal_rx_get_mac_addr2_valid =
hal_rx_get_mac_addr2_valid_8074v2;
hal_soc->ops->hal_rx_get_filter_category =
hal_rx_get_filter_category_8074v2;
hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_8074v2;
hal_soc->ops->hal_reo_config = hal_reo_config_8074v2;
hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_8074v2;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_8074v2;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_8074v2;
hal_soc->ops->hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_8074v2;
hal_soc->ops->hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_8074v2;
hal_soc->ops->hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_8074v2;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_8074v2;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
hal_rx_msdu_flow_idx_invalid_8074v2;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
hal_rx_msdu_flow_idx_timeout_8074v2;
hal_soc->ops->hal_rx_msdu_fse_metadata_get =
hal_rx_msdu_fse_metadata_get_8074v2;
hal_soc->ops->hal_rx_msdu_cce_metadata_get =
hal_rx_msdu_cce_metadata_get_8074v2;
hal_soc->ops->hal_rx_msdu_get_flow_params =
hal_rx_msdu_get_flow_params_8074v2;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
hal_rx_tlv_get_tcp_chksum_8074v2;
hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_8074v2;
#if defined(QCA_WIFI_QCA6018) && defined(WLAN_CFR_ENABLE) && \
defined(WLAN_ENH_CFR_ENABLE)
@@ -1320,21 +1368,27 @@ static void hal_hw_txrx_ops_attach_qca8074v2(struct hal_soc *hal_soc)
#endif
/* rx - msdu fast path info fields */
hal_soc->ops->hal_rx_msdu_packet_metadata_get =
hal_rx_msdu_packet_metadata_get_generic;
hal_rx_msdu_packet_metadata_get_generic_li;
hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
hal_rx_mpdu_start_tlv_tag_valid_8074v2;
/* rx - TLV struct offsets */
hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_msdu_end_offset_get =
hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get =
hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get =
hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get =
hal_rx_mpdu_end_offset_get_generic;
#ifndef NO_RX_PKT_HDR_TLV
hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic;
hal_soc->ops->hal_rx_pkt_tlv_offset_get =
hal_rx_pkt_tlv_offset_get_generic;
#endif
hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_8074v2;
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_8074v2;
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
hal_compute_reo_remap_ix2_ix3_8074v2;
};
struct hal_hw_srng_config hw_srng_table_8074v2[] = {
@@ -1790,5 +1844,6 @@ void hal_qca8074v2_attach(struct hal_soc *hal_soc)
{
hal_soc->hw_srng_table = hw_srng_table_8074v2;
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074v2;
hal_hw_txrx_default_ops_attach_li(hal_soc);
hal_hw_txrx_ops_attach_qca8074v2(hal_soc);
}

2
hal/wifi3.0/qca8074v2/hal_8074v2_rx.h
View File

@@ -19,7 +19,7 @@
#include "hal_internal.h"
#include "cdp_txrx_mon_struct.h"
#include "qdf_trace.h"
#include "hal_rx.h"
#include "hal_li_rx.h"
#include "hal_tx.h"
#include "dp_types.h"
#include "hal_api_mon.h"

174
hal/wifi3.0/qcn6122/hal_qcn6122.c
View File

@@ -14,7 +14,7 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "hal_hw_headers.h"
#include "hal_li_hw_headers.h"
#include "hal_internal.h"
#include "hal_api.h"
#include "target_type.h"
@@ -118,7 +118,9 @@
#include <hal_qcn6122_tx.h>
#include <hal_generic_api.h>
#include <hal_wbm.h>
#include "hal_li_rx.h"
#include "hal_li_api.h"
#include "hal_li_generic_api.h"
/**
* hal_rx_sw_mon_desc_info_get_6122(): API to read the
@@ -1071,19 +1073,26 @@ static uint32_t hal_rx_hw_desc_get_ppduid_get_6122(void *rx_tlv_hdr,
/**
* hal_reo_status_get_header_6122 - Process reo desc info
* @d - Pointer to reo descriptior
* @ring_desc: REO status ring descriptor
* @b - tlv type info
* @h1 - Pointer to hal_reo_status_header where info to be stored
*
* Return - none.
*
*/
static void hal_reo_status_get_header_6122(uint32_t *d, int b, void *h1)
static void hal_reo_status_get_header_6122(hal_ring_desc_t ring_desc, int b,
void *h1)
{
uint32_t *d = (uint32_t *)ring_desc;
uint32_t val1 = 0;
struct hal_reo_status_header *h =
(struct hal_reo_status_header *)h1;
/* Offsets of descriptor fields defined in HW headers start
* from the field after TLV header
*/
d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr));
switch (b) {
case HAL_REO_QUEUE_STATS_STATUS_TLV:
val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
@@ -1713,8 +1722,7 @@ static void hal_hw_txrx_ops_attach_qcn6122(struct hal_soc *hal_soc)
hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic;
hal_soc->ops->hal_setup_link_idle_list = hal_setup_link_idle_list_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li;
hal_soc->ops->hal_get_window_address = hal_get_window_address_6122;
/* tx */
@@ -1723,54 +1731,84 @@ static void hal_hw_txrx_ops_attach_qcn6122(struct hal_soc *hal_soc)
hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6122;
hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6122;
hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6122;
hal_soc->ops->hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic;
hal_soc->ops->hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic;
hal_soc->ops->hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic;
hal_soc->ops->hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic;
hal_soc->ops->hal_tx_comp_get_status = hal_tx_comp_get_status_generic;
hal_soc->ops->hal_tx_desc_set_buf_addr =
hal_tx_desc_set_buf_addr_generic_li;
hal_soc->ops->hal_tx_desc_set_search_type =
hal_tx_desc_set_search_type_generic_li;
hal_soc->ops->hal_tx_desc_set_search_index =
hal_tx_desc_set_search_index_generic_li;
hal_soc->ops->hal_tx_desc_set_cache_set_num =
hal_tx_desc_set_cache_set_num_generic_li;
hal_soc->ops->hal_tx_comp_get_status =
hal_tx_comp_get_status_generic_li;
hal_soc->ops->hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic;
hal_soc->ops->hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic;
hal_tx_comp_get_release_reason_generic_li;
hal_soc->ops->hal_get_wbm_internal_error =
hal_get_wbm_internal_error_generic_li;
hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6122;
hal_soc->ops->hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_6122;
hal_soc->ops->hal_tx_init_cmd_credit_ring =
hal_tx_init_cmd_credit_ring_6122;
/* rx */
hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_6122;
hal_soc->ops->hal_rx_msdu_start_nss_get =
hal_rx_msdu_start_nss_get_6122;
hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_6122;
hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6122;
hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_6122;
hal_soc->ops->hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_6122;
hal_soc->ops->hal_rx_dump_msdu_start_tlv =
hal_rx_dump_msdu_start_tlv_6122;
hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6122;
hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6122;
hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_6122;
hal_soc->ops->hal_rx_mpdu_start_tid_get =
hal_rx_mpdu_start_tid_get_6122;
hal_soc->ops->hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_6122;
hal_soc->ops->hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_6122;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_6122;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_6122;
hal_soc->ops->hal_reo_status_get_header = hal_reo_status_get_header_6122;
hal_soc->ops->hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic;
hal_soc->ops->hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic;
hal_soc->ops->hal_rx_msdu_end_da_idx_get =
hal_rx_msdu_end_da_idx_get_6122;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
hal_rx_msdu_desc_info_get_ptr_6122;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
hal_rx_link_desc_msdu0_ptr_6122;
hal_soc->ops->hal_reo_status_get_header =
hal_reo_status_get_header_6122;
hal_soc->ops->hal_rx_status_get_tlv_info =
hal_rx_status_get_tlv_info_generic_li;
hal_soc->ops->hal_rx_wbm_err_info_get =
hal_rx_wbm_err_info_get_generic_li;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
hal_rx_dump_mpdu_start_tlv_generic_li;
hal_soc->ops->hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic;
hal_soc->ops->hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic;
hal_soc->ops->hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic;
hal_soc->ops->hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_6122;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_6122;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = hal_rx_msdu_end_sa_is_valid_get_6122;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_6122;
hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_6122;
hal_soc->ops->hal_tx_set_pcp_tid_map =
hal_tx_set_pcp_tid_map_generic_li;
hal_soc->ops->hal_tx_update_pcp_tid_map =
hal_tx_update_pcp_tid_generic_li;
hal_soc->ops->hal_tx_set_tidmap_prty =
hal_tx_update_tidmap_prty_generic_li;
hal_soc->ops->hal_rx_get_rx_fragment_number =
hal_rx_get_rx_fragment_number_6122;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
hal_rx_msdu_end_da_is_mcbc_get_6122;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
hal_rx_msdu_end_sa_is_valid_get_6122;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
hal_rx_msdu_end_sa_idx_get_6122;
hal_soc->ops->hal_rx_desc_is_first_msdu =
hal_rx_desc_is_first_msdu_6122;
hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_6122;
hal_soc->ops->hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_6122;
hal_soc->ops->hal_rx_encryption_info_valid =
hal_rx_encryption_info_valid_6122;
hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6122;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_6122;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = hal_rx_msdu_end_da_is_valid_get_6122;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_6122;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_6122;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
hal_rx_msdu_end_first_msdu_get_6122;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
hal_rx_msdu_end_da_is_valid_get_6122;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
hal_rx_msdu_end_last_msdu_get_6122;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
hal_rx_get_mpdu_mac_ad4_valid_6122;
hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_6122;
hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6122;
@@ -1785,51 +1823,71 @@ static void hal_hw_txrx_ops_attach_qcn6122(struct hal_soc *hal_soc)
hal_rx_get_mpdu_sequence_control_valid_6122;
hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6122;
hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6122;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_6122;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
hal_rx_hw_desc_get_ppduid_get_6122;
hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_6122;
hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
hal_rx_msdu_end_sa_sw_peer_id_get_6122;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_6122;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_6122;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
hal_rx_msdu0_buffer_addr_lsb_6122;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
hal_rx_msdu_desc_info_ptr_get_6122;
hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6122;
hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6122;
hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6122;
hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6122;
hal_soc->ops->hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_6122;
hal_soc->ops->hal_rx_get_filter_category = hal_rx_get_filter_category_6122;
hal_soc->ops->hal_rx_get_mac_addr2_valid =
hal_rx_get_mac_addr2_valid_6122;
hal_soc->ops->hal_rx_get_filter_category =
hal_rx_get_filter_category_6122;
hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6122;
hal_soc->ops->hal_reo_config = hal_reo_config_6122;
hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6122;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_6122;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_6122;
hal_soc->ops->hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_6122;
hal_soc->ops->hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_6122;
hal_soc->ops->hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_6122;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_6122;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
hal_rx_msdu_flow_idx_invalid_6122;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
hal_rx_msdu_flow_idx_timeout_6122;
hal_soc->ops->hal_rx_msdu_fse_metadata_get =
hal_rx_msdu_fse_metadata_get_6122;
hal_soc->ops->hal_rx_msdu_cce_metadata_get =
hal_rx_msdu_cce_metadata_get_6122;
hal_soc->ops->hal_rx_msdu_get_flow_params =
hal_rx_msdu_get_flow_params_6122;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
hal_rx_tlv_get_tcp_chksum_6122;
hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6122;
#if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_6122;
hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_6122;
#endif
/* rx - msdu fast path info fields */
hal_soc->ops->hal_rx_msdu_packet_metadata_get = hal_rx_msdu_packet_metadata_get_6122;
hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = hal_rx_mpdu_start_tlv_tag_valid_6122;
hal_soc->ops->hal_rx_sw_mon_desc_info_get = hal_rx_sw_mon_desc_info_get_6122;
hal_soc->ops->hal_rx_msdu_packet_metadata_get =
hal_rx_msdu_packet_metadata_get_6122;
hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
hal_rx_mpdu_start_tlv_tag_valid_6122;
hal_soc->ops->hal_rx_sw_mon_desc_info_get =
hal_rx_sw_mon_desc_info_get_6122;
hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get =
hal_rx_wbm_err_msdu_continuation_get_6122;
/* rx - TLV struct offsets */
hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_msdu_end_offset_get =
hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get =
hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get =
hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get =
hal_rx_mpdu_end_offset_get_generic;
#ifndef NO_RX_PKT_HDR_TLV
hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic;
hal_soc->ops->hal_rx_pkt_tlv_offset_get =
hal_rx_pkt_tlv_offset_get_generic;
#endif
hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6122;
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_6122;
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
hal_compute_reo_remap_ix2_ix3_6122;
};
struct hal_hw_srng_config hw_srng_table_6122[] = {
@@ -2285,6 +2343,8 @@ void hal_qcn6122_attach(struct hal_soc *hal_soc)
{
hal_soc->hw_srng_table = hw_srng_table_6122;
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qcn6122;
hal_hw_txrx_default_ops_attach_li(hal_soc);
hal_hw_txrx_ops_attach_qcn6122(hal_soc);
if (hal_soc->static_window_map)
hal_write_window_register(hal_soc);

173
hal/wifi3.0/qcn9000/hal_9000.c
View File

@@ -15,7 +15,7 @@
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#include "hal_hw_headers.h"
#include "hal_li_hw_headers.h"
#include "hal_internal.h"
#include "hal_api.h"
#include "target_type.h"
@@ -120,7 +120,9 @@
#include <hal_9000_tx.h>
#include <hal_9000_rx.h>
#include <hal_generic_api.h>
#include <hal_wbm.h>
#include "hal_li_rx.h"
#include "hal_li_api.h"
#include "hal_li_generic_api.h"
/**
* hal_rx_sw_mon_desc_info_get_9000(): API to read the
@@ -1098,19 +1100,26 @@ static uint32_t hal_rx_hw_desc_get_ppduid_get_9000(void *rx_tlv_hdr,
/**
* hal_reo_status_get_header_9000 - Process reo desc info
* @d - Pointer to reo descriptior
* @ring_desc: REO status ring descriptor
* @b - tlv type info
* @h1 - Pointer to hal_reo_status_header where info to be stored
*
* Return - none.
*
*/
static void hal_reo_status_get_header_9000(uint32_t *d, int b, void *h1)
static void hal_reo_status_get_header_9000(hal_ring_desc_t ring_desc, int b,
void *h1)
{
uint32_t *d = (uint32_t *)ring_desc;
uint32_t val1 = 0;
struct hal_reo_status_header *h =
(struct hal_reo_status_header *)h1;
/* Offsets of descriptor fields defined in HW headers start
* from the field after TLV header
*/
d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr));
switch (b) {
case HAL_REO_QUEUE_STATS_STATUS_TLV:
val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
@@ -1739,8 +1748,7 @@ static void hal_hw_txrx_ops_attach_qcn9000(struct hal_soc *hal_soc)
hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic;
hal_soc->ops->hal_setup_link_idle_list = hal_setup_link_idle_list_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li;
hal_soc->ops->hal_get_window_address = hal_get_window_address_9000;
/* tx */
@@ -1749,54 +1757,84 @@ static void hal_hw_txrx_ops_attach_qcn9000(struct hal_soc *hal_soc)
hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_9000;
hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_9000;
hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_9000;
hal_soc->ops->hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic;
hal_soc->ops->hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic;
hal_soc->ops->hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic;
hal_soc->ops->hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic;
hal_soc->ops->hal_tx_comp_get_status = hal_tx_comp_get_status_generic;
hal_soc->ops->hal_tx_desc_set_buf_addr =
hal_tx_desc_set_buf_addr_generic_li;
hal_soc->ops->hal_tx_desc_set_search_type =
hal_tx_desc_set_search_type_generic_li;
hal_soc->ops->hal_tx_desc_set_search_index =
hal_tx_desc_set_search_index_generic_li;
hal_soc->ops->hal_tx_desc_set_cache_set_num =
hal_tx_desc_set_cache_set_num_generic_li;
hal_soc->ops->hal_tx_comp_get_status =
hal_tx_comp_get_status_generic_li;
hal_soc->ops->hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic;
hal_soc->ops->hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic;
hal_tx_comp_get_release_reason_generic_li;
hal_soc->ops->hal_get_wbm_internal_error =
hal_get_wbm_internal_error_generic_li;
hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_9000;
hal_soc->ops->hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_9000;
hal_soc->ops->hal_tx_init_cmd_credit_ring =
hal_tx_init_cmd_credit_ring_9000;
/* rx */
hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_9000;
hal_soc->ops->hal_rx_msdu_start_nss_get =
hal_rx_msdu_start_nss_get_9000;
hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_9000;
hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_9000;
hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_9000;
hal_soc->ops->hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_9000;
hal_soc->ops->hal_rx_dump_msdu_start_tlv =
hal_rx_dump_msdu_start_tlv_9000;
hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_9000;
hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_9000;
hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_9000;
hal_soc->ops->hal_rx_mpdu_start_tid_get =
hal_rx_mpdu_start_tid_get_9000;
hal_soc->ops->hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_9000;
hal_soc->ops->hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_9000;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_9000;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_9000;
hal_soc->ops->hal_reo_status_get_header = hal_reo_status_get_header_9000;
hal_soc->ops->hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic;
hal_soc->ops->hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic;
hal_soc->ops->hal_rx_msdu_end_da_idx_get =
hal_rx_msdu_end_da_idx_get_9000;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
hal_rx_msdu_desc_info_get_ptr_9000;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
hal_rx_link_desc_msdu0_ptr_9000;
hal_soc->ops->hal_reo_status_get_header =
hal_reo_status_get_header_9000;
hal_soc->ops->hal_rx_status_get_tlv_info =
hal_rx_status_get_tlv_info_generic_li;
hal_soc->ops->hal_rx_wbm_err_info_get =
hal_rx_wbm_err_info_get_generic_li;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
hal_rx_dump_mpdu_start_tlv_generic_li;
hal_soc->ops->hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic;
hal_soc->ops->hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic;
hal_soc->ops->hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic;
hal_soc->ops->hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_9000;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_9000;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = hal_rx_msdu_end_sa_is_valid_get_9000;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_9000;
hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_9000;
hal_soc->ops->hal_tx_set_pcp_tid_map =
hal_tx_set_pcp_tid_map_generic_li;
hal_soc->ops->hal_tx_update_pcp_tid_map =
hal_tx_update_pcp_tid_generic_li;
hal_soc->ops->hal_tx_set_tidmap_prty =
hal_tx_update_tidmap_prty_generic_li;
hal_soc->ops->hal_rx_get_rx_fragment_number =
hal_rx_get_rx_fragment_number_9000;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
hal_rx_msdu_end_da_is_mcbc_get_9000;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
hal_rx_msdu_end_sa_is_valid_get_9000;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
hal_rx_msdu_end_sa_idx_get_9000;
hal_soc->ops->hal_rx_desc_is_first_msdu =
hal_rx_desc_is_first_msdu_9000;
hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_9000;
hal_soc->ops->hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_9000;
hal_soc->ops->hal_rx_encryption_info_valid =
hal_rx_encryption_info_valid_9000;
hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_9000;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_9000;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = hal_rx_msdu_end_da_is_valid_get_9000;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_9000;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_9000;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
hal_rx_msdu_end_first_msdu_get_9000;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
hal_rx_msdu_end_da_is_valid_get_9000;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
hal_rx_msdu_end_last_msdu_get_9000;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
hal_rx_get_mpdu_mac_ad4_valid_9000;
hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_9000;
hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_9000;
@@ -1811,51 +1849,71 @@ static void hal_hw_txrx_ops_attach_qcn9000(struct hal_soc *hal_soc)
hal_rx_get_mpdu_sequence_control_valid_9000;
hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_9000;
hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_9000;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_9000;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
hal_rx_hw_desc_get_ppduid_get_9000;
hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000;
hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
hal_rx_msdu_end_sa_sw_peer_id_get_9000;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_9000;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_9000;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
hal_rx_msdu0_buffer_addr_lsb_9000;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
hal_rx_msdu_desc_info_ptr_get_9000;
hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_9000;
hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_9000;
hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_9000;
hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_9000;
hal_soc->ops->hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_9000;
hal_soc->ops->hal_rx_get_filter_category = hal_rx_get_filter_category_9000;
hal_soc->ops->hal_rx_get_mac_addr2_valid =
hal_rx_get_mac_addr2_valid_9000;
hal_soc->ops->hal_rx_get_filter_category =
hal_rx_get_filter_category_9000;
hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_9000;
hal_soc->ops->hal_reo_config = hal_reo_config_9000;
hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_9000;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_9000;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_9000;
hal_soc->ops->hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_9000;
hal_soc->ops->hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_9000;
hal_soc->ops->hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_9000;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_9000;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
hal_rx_msdu_flow_idx_invalid_9000;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
hal_rx_msdu_flow_idx_timeout_9000;
hal_soc->ops->hal_rx_msdu_fse_metadata_get =
hal_rx_msdu_fse_metadata_get_9000;
hal_soc->ops->hal_rx_msdu_cce_metadata_get =
hal_rx_msdu_cce_metadata_get_9000;
hal_soc->ops->hal_rx_msdu_get_flow_params =
hal_rx_msdu_get_flow_params_9000;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
hal_rx_tlv_get_tcp_chksum_9000;
hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_9000;
#if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_9000;
hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_9000;
#endif
/* rx - msdu fast path info fields */
hal_soc->ops->hal_rx_msdu_packet_metadata_get = hal_rx_msdu_packet_metadata_get_9000;
hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = hal_rx_mpdu_start_tlv_tag_valid_9000;
hal_soc->ops->hal_rx_sw_mon_desc_info_get = hal_rx_sw_mon_desc_info_get_9000;
hal_soc->ops->hal_rx_msdu_packet_metadata_get =
hal_rx_msdu_packet_metadata_get_9000;
hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
hal_rx_mpdu_start_tlv_tag_valid_9000;
hal_soc->ops->hal_rx_sw_mon_desc_info_get =
hal_rx_sw_mon_desc_info_get_9000;
hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get =
hal_rx_wbm_err_msdu_continuation_get_9000;
/* rx - TLV struct offsets */
hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_msdu_end_offset_get =
hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get =
hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get =
hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get =
hal_rx_mpdu_end_offset_get_generic;
#ifndef NO_RX_PKT_HDR_TLV
hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic;
hal_soc->ops->hal_rx_pkt_tlv_offset_get =
hal_rx_pkt_tlv_offset_get_generic;
#endif
hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_9000;
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_9000;
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
hal_compute_reo_remap_ix2_ix3_9000;
};
struct hal_hw_srng_config hw_srng_table_9000[] = {
@@ -2311,6 +2369,7 @@ void hal_qcn9000_attach(struct hal_soc *hal_soc)
{
hal_soc->hw_srng_table = hw_srng_table_9000;
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qcn9000;
hal_hw_txrx_default_ops_attach_li(hal_soc);
hal_hw_txrx_ops_attach_qcn9000(hal_soc);
if (hal_soc->static_window_map)
hal_write_window_register(hal_soc);