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Merge "video: driver: replace V4l2 macros with availble upstream macros"

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This commit is contained in:
qctecmdr
2023-03-16 10:56:49 -07:00
committed by Gerrit - the friendly Code Review server
parent f00fe9f305 1cf504b165
commit 59a8ab6758
4 changed files with 16 additions and 26 deletions
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4
driver/platform/common/src/msm_vidc_platform_ext.c
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@@ -175,7 +175,7 @@ int msm_vidc_set_ir_period(void *instance,
core = inst->core; core = inst->core;
if (inst->capabilities->cap[IR_TYPE].value == if (inst->capabilities->cap[IR_TYPE].value ==
V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_RANDOM) { V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM) {
if (inst->bufq[OUTPUT_PORT].vb2q->streaming) { if (inst->bufq[OUTPUT_PORT].vb2q->streaming) {
i_vpr_h(inst, "%s: dynamic random intra refresh not allowed\n", i_vpr_h(inst, "%s: dynamic random intra refresh not allowed\n",
__func__); __func__);
@@ -183,7 +183,7 @@ int msm_vidc_set_ir_period(void *instance,
} }
ir_type = HFI_PROP_IR_RANDOM_PERIOD; ir_type = HFI_PROP_IR_RANDOM_PERIOD;
} else if (inst->capabilities->cap[IR_TYPE].value == } else if (inst->capabilities->cap[IR_TYPE].value ==
V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_CYCLIC) { V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC) {
ir_type = HFI_PROP_IR_CYCLIC_PERIOD; ir_type = HFI_PROP_IR_CYCLIC_PERIOD;
} else { } else {
i_vpr_e(inst, "%s: invalid ir_type %d\n", i_vpr_e(inst, "%s: invalid ir_type %d\n",

14
driver/platform/kalama/src/msm_vidc_kalama.c
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@@ -832,18 +832,18 @@ static struct msm_platform_inst_capability instance_cap_data_kalama[] = {
CAP_FLAG_OUTPUT_PORT}, CAP_FLAG_OUTPUT_PORT},
{IR_TYPE, ENC, H264|HEVC, {IR_TYPE, ENC, H264|HEVC,
V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_RANDOM, V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM,
V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_CYCLIC, V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC,
BIT(V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_RANDOM) | BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM) |
BIT(V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_CYCLIC), BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC),
V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_RANDOM, V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM,
V4L2_CID_MPEG_VIDEO_VIDC_INTRA_REFRESH_TYPE, V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE,
0, 0,
CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU},
{IR_PERIOD, ENC, H264|HEVC, {IR_PERIOD, ENC, H264|HEVC,
0, INT_MAX, 1, 0, 0, INT_MAX, 1, 0,
V4L2_CID_MPEG_VIDC_INTRA_REFRESH_PERIOD, V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD,
0, 0,
CAP_FLAG_INPUT_PORT | CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | CAP_FLAG_OUTPUT_PORT |
CAP_FLAG_DYNAMIC_ALLOWED}, CAP_FLAG_DYNAMIC_ALLOWED},

14
driver/platform/pineapple/src/msm_vidc_pineapple.c
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@@ -902,18 +902,18 @@ static struct msm_platform_inst_capability instance_cap_data_pineapple[] = {
CAP_FLAG_OUTPUT_PORT}, CAP_FLAG_OUTPUT_PORT},
{IR_TYPE, ENC, H264|HEVC, {IR_TYPE, ENC, H264|HEVC,
V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_RANDOM, V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM,
V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_CYCLIC, V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC,
BIT(V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_RANDOM) | BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM) |
BIT(V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_CYCLIC), BIT(V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC),
V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_RANDOM, V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM,
V4L2_CID_MPEG_VIDEO_VIDC_INTRA_REFRESH_TYPE, V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE,
0, 0,
CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU}, CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU},
{IR_PERIOD, ENC, H264|HEVC, {IR_PERIOD, ENC, H264|HEVC,
0, INT_MAX, 1, 0, 0, INT_MAX, 1, 0,
V4L2_CID_MPEG_VIDC_INTRA_REFRESH_PERIOD, V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD,
0, 0,
CAP_FLAG_INPUT_PORT | CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | CAP_FLAG_OUTPUT_PORT |
CAP_FLAG_DYNAMIC_ALLOWED}, CAP_FLAG_DYNAMIC_ALLOWED},

10
include/uapi/vidc/media/v4l2_vidc_extensions.h
View File

@@ -81,16 +81,6 @@
#define V4L2_CID_MPEG_VIDC_FRAME_RATE (V4L2_CID_MPEG_VIDC_BASE + 0x5) #define V4L2_CID_MPEG_VIDC_FRAME_RATE (V4L2_CID_MPEG_VIDC_BASE + 0x5)
#define V4L2_CID_MPEG_VIDC_OPERATING_RATE (V4L2_CID_MPEG_VIDC_BASE + 0x6) #define V4L2_CID_MPEG_VIDC_OPERATING_RATE (V4L2_CID_MPEG_VIDC_BASE + 0x6)
/* Encoder Intra refresh period */
#define V4L2_CID_MPEG_VIDC_INTRA_REFRESH_PERIOD (V4L2_CID_MPEG_VIDC_BASE + 0xB)
/* Encoder Intra refresh type */
#define V4L2_CID_MPEG_VIDEO_VIDC_INTRA_REFRESH_TYPE \
(V4L2_CID_MPEG_VIDC_BASE + 0xC)
enum v4l2_mpeg_vidc_ir_type {
V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_RANDOM = 0x0,
V4L2_MPEG_VIDEO_VIDC_INTRA_REFRESH_CYCLIC = 0x1,
};
#define V4L2_CID_MPEG_VIDC_TIME_DELTA_BASED_RC (V4L2_CID_MPEG_VIDC_BASE + 0xD) #define V4L2_CID_MPEG_VIDC_TIME_DELTA_BASED_RC (V4L2_CID_MPEG_VIDC_BASE + 0xD)
/* Encoder quality controls */ /* Encoder quality controls */
#define V4L2_CID_MPEG_VIDC_CONTENT_ADAPTIVE_CODING \ #define V4L2_CID_MPEG_VIDC_CONTENT_ADAPTIVE_CODING \