qcacld-3.0: Enable emergency reaping for wmi pipe.

Since management frames have been added to the wmi pipe,
the wmi pipe may fill up before the driver schedules the
tx completion processing.

Make tx completion processing use the DDR ce index to
avoid register access durring reaping.

Change-Id: I213aa0274d3c66e583bcdb700ced1133c2c30ebc
CRs-Fixed: 945831

core/hif/src/ce/ce_main.c

@@ -2343,6 +2343,7 @@ inline uint32_t DEBUG_CE_DEST_RING_READ_IDX_GET(struct ol_softc *scn,
 
 #endif
 
+#ifdef ADRASTEA_RRI_ON_DDR
 /**
  * hif_get_src_ring_read_index(): Called to get the SRRI
  *
@@ -2392,7 +2393,6 @@ inline unsigned int hif_get_dst_ring_read_index(struct ol_softc *scn,
 				(CE_ctrl_addr) + CURRENT_DRRI_ADDRESS);
 }
 
-#ifdef ADRASTEA_RRI_ON_DDR
 /**
  * hif_config_rri_on_ddr(): Configure the RRI on DDR mechanism
  *

core/hif/src/ce/ce_reg.h

@@ -264,6 +264,7 @@ uint32_t DEBUG_CE_DEST_RING_READ_IDX_GET(struct ol_softc *scn,
 #define SRRI_FROM_DDR_ADDR(addr) ((*(addr)) & 0xFFFF)
 #define DRRI_FROM_DDR_ADDR(addr) (((*(addr))>>16) & 0xFFFF)
 
+#ifdef ADRASTEA_RRI_ON_DDR
 #ifdef SHADOW_REG_DEBUG
 #define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
 	DEBUG_CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr)
@@ -276,13 +277,11 @@ uint32_t DEBUG_CE_DEST_RING_READ_IDX_GET(struct ol_softc *scn,
 	DRRI_FROM_DDR_ADDR(VADDR_FOR_CE(scn, CE_ctrl_addr))
 #endif
 
-
 unsigned int hif_get_src_ring_read_index(struct ol_softc *scn,
 		uint32_t CE_ctrl_addr);
 unsigned int hif_get_dst_ring_read_index(struct ol_softc *scn,
 		uint32_t CE_ctrl_addr);
 
-#ifdef ADRASTEA_RRI_ON_DDR
 #define CE_SRC_RING_READ_IDX_GET(scn, CE_ctrl_addr)\
 	hif_get_src_ring_read_index(scn, CE_ctrl_addr)
 #define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\
@@ -292,6 +291,15 @@ unsigned int hif_get_dst_ring_read_index(struct ol_softc *scn,
 	A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS)
 #define CE_DEST_RING_READ_IDX_GET(scn, CE_ctrl_addr)\
 	A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_DRRI_ADDRESS)
+
+/**
+ * if RRI on DDR is not enabled, get idx from ddr defaults to
+ * using the register value & force wake must be used for
+ * non interrupt processing.
+ */
+#define CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, CE_ctrl_addr)\
+	A_TARGET_READ(scn, (CE_ctrl_addr) + CURRENT_SRRI_ADDRESS)
+
 #endif
 
 #define CE_SRC_RING_BASE_ADDR_SET(scn, CE_ctrl_addr, addr) \

core/hif/src/ce/ce_service.c

@@ -903,7 +903,7 @@ ce_completed_send_next_nolock(struct CE_state *CE_state,
 		 */
 		A_TARGET_ACCESS_BEGIN_RET(scn);
 		src_ring->hw_index =
-			CE_SRC_RING_READ_IDX_GET(scn, ctrl_addr);
+			CE_SRC_RING_READ_IDX_GET_FROM_DDR(scn, ctrl_addr);
 		A_TARGET_ACCESS_END_RET(scn);
 	}
 	read_index = src_ring->hw_index;

core/htc/htc_send.c

@@ -532,6 +532,7 @@ static A_STATUS htc_issue_packets(HTC_TARGET *target,
 		pEndpoint->ul_outstanding_cnt++;
 		UNLOCK_HTC_TX(target);
 
+		hif_send_complete_check(target->hif_dev, pEndpoint->UL_PipeID, false);
 		status = hif_send_head(target->hif_dev,
 				       pEndpoint->UL_PipeID, pEndpoint->Id,
 				       HTC_HDR_LENGTH + pPacket->ActualLength,