Merge "msm: camera: isp: Add support of SFE HW for v780" into camera-kernel.lnx.5.0

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe680.h

@@ -10,7 +10,8 @@
 #include "cam_sfe_bus_rd.h"
 #include "cam_sfe_bus_wr.h"
 
-static struct cam_sfe_top_module_desc sfe_mod_desc[] = {
+
+static struct cam_sfe_top_module_desc sfe_680_mod_desc[] = {
 	{
 		.id = 0,
 		.desc = "CRC_ZSL",
@@ -109,7 +110,7 @@ static struct cam_sfe_top_module_desc sfe_mod_desc[] = {
 	},
 };
 
-static struct cam_sfe_wr_client_desc sfe_wr_client_desc[] = {
+static struct cam_sfe_wr_client_desc sfe_680_wr_client_desc[] = {
 	{
 		.wm_id = 0,
 		.desc = "REMOSAIC",
@@ -130,7 +131,8 @@ static struct cam_sfe_wr_client_desc sfe_wr_client_desc[] = {
 		.wm_id = 4,
 		.desc = "STATS_BE1",
 	},
-	{ .wm_id = 5,
+	{
+		.wm_id = 5,
 		.desc = "STATS_BHIST1",
 	},
 	{
@@ -163,6 +165,132 @@ static struct cam_sfe_wr_client_desc sfe_wr_client_desc[] = {
 	},
 };
 
+static struct cam_sfe_mode sfe_680_mode[] = {
+	{
+		.value = 0x1,
+		.desc = "FS Mode",
+	},
+	{
+		.value = 0x3,
+		.desc = "Offline Mode",
+	},
+	{
+		.value = 0x4,
+		.desc = "sHDR mode",
+	},
+};
+
+static struct cam_sfe_top_err_irq_desc sfe_680_top_irq_err_desc[] = {
+	{
+		.bitmask = BIT(14),
+		.err_name = "PP_VIOLATION",
+		.desc = "CCIF protocol violation within any of the modules in pixel pipeline",
+	},
+	{
+		.bitmask = BIT(15),
+		.err_name = "DIAG_VIOLATION",
+		.desc = "HBI is less than the minimum required HBI",
+	},
+	{
+		.bitmask = BIT(16),
+		.err_name = "LINE_SMOOTH_VIOLATION",
+		.desc = "Line Smoothner IRQ fire",
+	},
+};
+
+static struct cam_sfe_top_debug_info sfe680_clc_dbg_module_info[CAM_SFE_TOP_DBG_REG_MAX][8] = {
+	SFE_DBG_INFO_ARRAY_4bit(
+		"test_bus_reserved",
+		"test_bus_reserved",
+		"test_bus_reserved",
+		"test_bus_reserved",
+		"test_bus_reserved",
+		"test_bus_reserved",
+		"test_bus_reserved",
+		"test_bus_reserved"
+	),
+	SFE_DBG_INFO_ARRAY_4bit(
+		"zsl_throttle",
+		"crc_zsl",
+		"comp_zsl",
+		"crc_prev",
+		"hdrc_ch2",
+		"hdrc_ch1",
+		"hdrc_ch0",
+		"stats_bhist_ch0"
+	),
+	SFE_DBG_INFO_ARRAY_4bit(
+		"stats_bg_ch0",
+		"lsc_ch0",
+		"crc_ch0",
+		"ccif_2x2_to_2x1",
+		"decomp",
+		"msb_align_ch0",
+		"bpc_pdpc",
+		"ch0_gain"
+	),
+	SFE_DBG_INFO_ARRAY_4bit(
+		"bhist_ch1",
+		"stats_bg_ch1",
+		"lsc_ch1",
+		"crc_ch1",
+		"msb_align_ch1",
+		"ch1_gain",
+		"bhist_ch2",
+		"stats_bg_ch2"
+	),
+	SFE_DBG_INFO_ARRAY_4bit(
+		"lsc_ch2",
+		"crc_ch2",
+		"msb_align_ch2",
+		"ch2_gain",
+		"lcr_throttle",
+		"lcr",
+		"demux_fetch2",
+		"demux_fetch1"
+	),
+	SFE_DBG_INFO_ARRAY_4bit(
+		"demux_fetch0",
+		"csid_ccif",
+		"RDI4",
+		"RDI3",
+		"RDI2",
+		"RDI1",
+		"RDI0",
+		"bhist2_bus_wr"
+	),
+	SFE_DBG_INFO_ARRAY_4bit(
+		"bg2_bus_wr",
+		"bhist1_bus_wr",
+		"bg1_bus_wr",
+		"bhist0_bus_wr",
+		"bg0_bus_wr",
+		"lcr_bus_wr",
+		"zsl_bus_wr",
+		"sfe_op_throttle"
+	),
+	SFE_DBG_INFO_ARRAY_4bit(
+		"line_smooth",
+		"pp",
+		"bus_conv_ch2",
+		"bus_conv_ch1",
+		"bus_conv_ch0",
+		"fe_ch2",
+		"fe_ch1",
+		"fe_ch0"
+	),
+	SFE_DBG_INFO_ARRAY_4bit(
+		"rdi4",
+		"rdi3",
+		"rdi2",
+		"rdi1",
+		"rdi0",
+		"pixel",
+		"reserved",
+		"reserved"
+	),
+};
+
 static struct cam_sfe_top_common_reg_offset  sfe680_top_commong_reg  = {
 	.hw_version                    = 0x00000000,
 	.hw_capability                 = 0x00000004,
@@ -170,7 +298,7 @@ static struct cam_sfe_top_common_reg_offset  sfe680_top_commong_reg  = {
 	.core_cgc_ctrl                 = 0x00000010,
 	.ahb_clk_ovd                   = 0x00000014,
 	.core_cfg                      = 0x00000018,
-	.violation_status              = 0x00000030,
+	.ipp_violation_status          = 0x00000030,
 	.diag_config                   = 0x00000034,
 	.diag_sensor_status_0          = 0x00000038,
 	.diag_sensor_status_1          = 0x0000003C,
@@ -184,6 +312,13 @@ static struct cam_sfe_top_common_reg_offset  sfe680_top_commong_reg  = {
 	.sfe_op_throttle_cfg           = 0x000000C4,
 	.bus_overflow_status           = 0x00000868,
 	.top_debug_cfg                 = 0x0000007C,
+	.lcr_supported                 = true,
+	.ir_supported                  = false,
+	.qcfa_only                     = true,
+	.num_sfe_mode                  = ARRAY_SIZE(sfe_680_mode),
+	.sfe_mode                      = sfe_680_mode,
+	.ipp_violation_mask            = 0x4000,
+	.num_debug_registers           = 12,
 	.top_debug = {
 		0x0000004C,
 		0x00000050,
@@ -202,12 +337,12 @@ static struct cam_sfe_top_common_reg_offset  sfe680_top_commong_reg  = {
 
 static struct cam_sfe_modules_common_reg_offset sfe680_modules_common_reg = {
 	.demux_module_cfg              = 0x00003060,
-	.demux_qcfa_cfg                = 0x00003064,
+	.demux_xcfa_cfg                = 0x00003064,
 	.demux_hdr_cfg                 = 0x00003074,
 	.demux_lcr_sel                 = 0x00003078,
 	.hdrc_remo_mod_cfg             = 0x00005860,
-	.hdrc_remo_qcfa_bin_cfg        = 0x00005A78,
-	.qcfa_hdrc_remo_out_mux_cfg    = 0x00005A74,
+	.hdrc_remo_xcfa_bin_cfg        = 0x00005A78,
+	.xcfa_hdrc_remo_out_mux_cfg    = 0x00005A74,
 };
 
 static struct cam_sfe_top_common_reg_data sfe_680_top_common_reg_data = {
@@ -257,8 +392,8 @@ static struct cam_sfe_top_hw_info sfe680_top_hw_info = {
 	.common_reg = &sfe680_top_commong_reg,
 	.modules_hw_info = &sfe680_modules_common_reg,
 	.common_reg_data = &sfe_680_top_common_reg_data,
-	.module_desc     =  sfe_mod_desc,
-	.wr_client_desc  =  sfe_wr_client_desc,
+	.ipp_module_desc =  sfe_680_mod_desc,
+	.wr_client_desc  =  sfe_680_wr_client_desc,
 	.pix_reg_data    = &sfe_680_pix_reg_data,
 	.rdi_reg_data[0] = &sfe_680_rdi0_reg_data,
 	.rdi_reg_data[1] = &sfe_680_rdi1_reg_data,
@@ -274,6 +409,10 @@ static struct cam_sfe_top_hw_info sfe680_top_hw_info = {
 		CAM_SFE_RDI_VER_1_0,
 		CAM_SFE_RDI_VER_1_0,
 	},
+	.num_top_errors  = ARRAY_SIZE(sfe_680_top_irq_err_desc),
+	.top_err_desc    = sfe_680_top_irq_err_desc,
+	.num_clc_module  = 9,
+	.clc_dbg_mod_info = &sfe680_clc_dbg_module_info,
 };
 
 static struct cam_irq_register_set sfe680_bus_rd_irq_reg[1] = {
@@ -1050,7 +1189,7 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
 };
 
 static struct cam_irq_register_set sfe680_top_irq_reg_set[1] = {
-{
+	{
 	.mask_reg_offset   = 0x00000020,
 	.clear_reg_offset  = 0x00000024,
 	.status_reg_offset = 0x00000028,

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe780.h

@@ -0,0 +1,1441 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _CAM_SFE780_H_
+#define _CAM_SFE780_H_
+#include "cam_sfe_core.h"
+#include "cam_sfe_bus.h"
+#include "cam_sfe_bus_rd.h"
+#include "cam_sfe_bus_wr.h"
+
+static struct cam_sfe_top_module_desc sfe_780_mod_desc[] = {
+	{
+		.id = 0,
+		.desc = "CRC_IRC",
+	},
+	{
+		.id = 1,
+		.desc = "CRC_ZSL",
+	},
+	{
+		.id = 2,
+		.desc = "COMP",
+	},
+	{
+		.id = 3,
+		.desc = "LINE_SMOOTH",
+	},
+	{
+		.id = 4,
+		.desc = "CRC_PREV",
+	},
+	{
+		.id = 5,
+		.desc = "HDRC",
+	},
+	{
+		.id = 6,
+		.desc = "DECOMP",
+	},
+	{
+		.id = 7,
+		.desc = "BPC_PDPC",
+	},
+	{
+		.id = 8,
+		.desc = "PDPC_BPC_ID_CH0",
+	},
+	{
+		.id = 9,
+		.desc = "RS_CH0",
+	},
+	{
+		.id = 10,
+		.desc = "BHIST_CH0",
+	},
+	{
+		.id = 11,
+		.desc = "BG_CH0",
+	},
+	{
+		.id = 12,
+		.desc = "LSC_CH0",
+	},
+	{
+		.id = 13,
+		.desc = "CRC_CH0",
+	},
+	{
+		.id = 14,
+		.desc = "CCIF_2x2_2x1",
+	},
+	{
+		.id = 15,
+		.desc = "GAIN_CH0",
+	},
+	{
+		.id = 16,
+		.desc = "PDPC_BPC_ID_CH1",
+	},
+	{
+		.id = 17,
+		.desc = "RS_CH1",
+	},
+	{
+		.id = 18,
+		.desc = "BHIST_CH1",
+	},
+	{
+		.id = 19,
+		.desc = "BG_CH1",
+	},
+	{
+		.id = 20,
+		.desc = "LSC_CH1",
+	},
+	{
+		.id = 21,
+		.desc = "CRC_CH1",
+	},
+	{
+		.id = 22,
+		.desc = "GAIN_CH1",
+	},
+	{
+		.id = 23,
+		.desc = "PDPC_BPC_ID_CH2",
+	},
+	{
+		.id = 24,
+		.desc = "RS_CH2",
+	},
+	{
+		.id = 25,
+		.desc = "BHIST_CH2",
+	},
+	{
+		.id = 26,
+		.desc = "BG_CH2",
+	},
+	{
+		.id = 27,
+		.desc = "LSC_CH2",
+	},
+	{
+		.id = 28,
+		.desc = "CRC_CH2",
+	},
+	{
+		.id = 29,
+		.desc = "GAIN_CH2",
+	},
+	{
+		.id = 30,
+		.desc = "XCFA_DEMUX",
+	},
+};
+
+static struct cam_sfe_wr_client_desc sfe_780_wr_client_desc[] = {
+	{
+		.wm_id = 0,
+		.desc = "REMOSAIC",
+	},
+	{
+		.wm_id = 1,
+		.desc = "IR_OUT",
+	},
+	{
+		.wm_id = 2,
+		.desc = "STATS_BE0",
+	},
+	{
+		.wm_id = 3,
+		.desc = "STATS_BHIST0",
+	},
+	{
+		.wm_id = 4,
+		.desc = "STATS_BE1",
+	},
+	{ 	.wm_id = 5,
+		.desc = "STATS_BHIST1",
+	},
+	{
+		.wm_id = 6,
+		.desc = "STATS_BE2",
+	},
+	{
+		.wm_id = 7,
+		.desc = "STATS_BHIST2",
+	},
+	{
+		.wm_id = 8,
+		.desc = "STATS_RS0",
+	},
+	{
+		.wm_id = 9,
+		.desc = "STATS_RS1",
+	},
+	{
+		.wm_id = 10,
+		.desc = "STATS_RS2",
+	},
+	{
+		.wm_id = 11,
+		.desc = "RDI_0",
+	},
+	{
+		.wm_id = 12,
+		.desc = "RDI_1",
+	},
+	{
+		.wm_id = 13,
+		.desc = "RDI_2",
+	},
+	{
+		.wm_id = 14,
+		.desc = "RDI_3",
+	},
+	{
+		.wm_id = 15,
+		.desc = "RDI_4",
+	},
+};
+
+static struct cam_sfe_mode sfe_780_mode[] = {
+	{
+		.value = 0x0,
+		.desc = "QCFA HDR/non-HDR mode",
+	},
+	{
+		.value = 0x1,
+		.desc = "sHDR 1exp mode",
+	},
+	{
+		.value = 0x2,
+		.desc = "sHDR 2exp mode",
+	},
+	{
+		.value = 0x3,
+		.desc = "sHDR 3exp mode",
+	},
+	{
+		.value = 0x4,
+		.desc = "Bayer offline mode",
+	},
+	{
+		.value = 0x5,
+		.desc = "Bayer FS mode",
+	},
+};
+
+static struct cam_sfe_top_err_irq_desc sfe_780_top_irq_err_desc[] = {
+	{
+		.bitmask = BIT(14),
+		.err_name = "PP_VIOLATION",
+		.desc = "CCIF protocol violation within any of the modules in pixel pipeline",
+	},
+	{
+		.bitmask = BIT(15),
+		.err_name = "DIAG_VIOLATION",
+		.desc = "HBI is less than the minimum required HBI",
+	},
+	{
+		.bitmask = BIT(17),
+		.err_name = "CONTEXT_CONTROLLER_VIOLATION",
+		.desc = "HW detects that there is third context entering SFE core",
+	},
+	{
+		.bitmask = BIT(18),
+		.err_name = "CONTEXT_CONTROLLER_SWITCH_VIOLATION",
+		.desc = "The old context is not completed processing inside SFE.",
+	},
+};
+
+static struct cam_sfe_top_debug_info
+	sfe780_clc_dbg_module_info[CAM_SFE_TOP_DBG_REG_MAX][8] = {
+	SFE_DBG_INFO_ARRAY_4bit(
+		"test_bus_reserved",
+		"test_bus_reserved",
+		"test_bus_reserved",
+		"test_bus_reserved",
+		"test_bus_reserved",
+		"test_bus_reserved",
+		"test_bus_reserved",
+		"test_bus_reserved"
+	),
+	SFE_DBG_INFO_ARRAY_4bit(
+		"irc_throttle",
+		"crc_irc",
+		"zsl_throttle",
+		"crc_zsl",
+		"comp",
+		"ls",
+		"crc_prev",
+		"hdrc_ch2"
+	),
+	SFE_DBG_INFO_ARRAY_4bit(
+		"hdrc_ch1",
+		"hdrc_ch0",
+		"bayer_rs_0",
+		"stats_bhist_ch0",
+		"stats_bg_ch0",
+		"lsc_ch0",
+		"crc_ch0",
+		"bpc_pdpc_id"
+	),
+	SFE_DBG_INFO_ARRAY_4bit(
+		"2x2_2x1_ch0",
+		"decomp_ch0",
+		"msb_align_ch0",
+		"bpc_pdpc_ch0",
+		"ch_gain_ch0",
+		"bayer_rs_ch1",
+		"stats_bhist_ch1",
+		"stats_bg_ch1"
+	),
+	SFE_DBG_INFO_ARRAY_4bit(
+		"lsc_ch1",
+		"crc_ch1",
+		"msb_align_ch1",
+		"bpc_pdpc_1d_ch1",
+		"ch_gain_ch1",
+		"bayer_rs_ch2",
+		"stats_bhist_ch2",
+		"stats_bg_ch2"
+	),
+	SFE_DBG_INFO_ARRAY_4bit(
+		"lsc_ch2",
+		"crc_ch2",
+		"msb_align_ch2",
+		"bpc_pdpc_1d_ch2",
+		"ch_gain_ch2",
+		"demux_ch2",
+		"demux_ch1",
+		"demux_ch0"
+	),
+	SFE_DBG_INFO_ARRAY_4bit(
+		"sfe_demux_pp",
+		"sfe_rdi4",
+		"sfe_rdi3",
+		"sfe_rdi2",
+		"sfe_rdi1",
+		"sfe_rdi0",
+		"bayer_rs_ch2",
+		"stats_bhist_ch2"
+	),
+	SFE_DBG_INFO_ARRAY_4bit(
+		"sfe_stats_bg_ch2",
+		"sfe_bayer_rs_ch1",
+		"sfe_stats_bhist_ch1",
+		"sfe_stats_bg_ch1",
+		"sfe_bayer_rs_ch0",
+		"sfe_stats_bhist_ch0",
+		"sfe_stats_bg_ch0",
+		"sfe_irc"
+	),
+	SFE_DBG_INFO_ARRAY_4bit(
+		"sfe_zsl",
+		"sfe_throttle",
+		"sfe_pp_zsl",
+		"sfe_conv_ch12",
+		"sfe_conv_ch1",
+		"sfe_conv_ch0",
+		"sfe_fe_ch2",
+		"sfe_fe_ch1"
+	),
+	SFE_DBG_INFO_ARRAY_4bit(
+		"sfe_fe_ch0",
+		"sfe_fe_ch0",
+		"sfe_fe_ch0",
+		"sfe_fe_ch0",
+		"sfe_fe_ch0",
+		"sfe_fe_ch0",
+		"sfe_fe_ch0",
+		"sfe_fe_ch0"
+	),
+	SFE_DBG_INFO_ARRAY_4bit(
+		"rdi4",
+		"rdi3",
+		"rdi2",
+		"rdi1",
+		"rdi0",
+		"pixel",
+		"reserved",
+		"reserved"
+	),
+};
+
+static struct cam_sfe_top_common_reg_offset  sfe780_top_commong_reg  = {
+	.hw_version                    = 0x00000000,
+	.hw_capability                 = 0x00000004,
+	.stats_feature                 = 0x00000008,
+	.core_cgc_ctrl                 = 0x00000010,
+	.ahb_clk_ovd                   = 0x00000014,
+	.core_cfg                      = 0x000000CC,
+	.ipp_violation_status          = 0x00000030,
+	.diag_config                   = 0x00000034,
+	.diag_sensor_status_0          = 0x00000038,
+	.diag_sensor_status_1          = 0x0000003C,
+	.diag_sensor_frame_cnt_status0 = 0x00000040,
+	.diag_sensor_frame_cnt_status1 = 0x00000044,
+	.stats_ch2_throttle_cfg        = 0x000000B0,
+	.stats_ch1_throttle_cfg        = 0x000000B4,
+	.stats_ch0_throttle_cfg        = 0x000000B8,
+	.hdr_throttle_cfg              = 0x000000C0,
+	.sfe_op_throttle_cfg           = 0x000000C4,
+	.irc_throttle_cfg              = 0x000000C8,
+	.sfe_single_dual_cfg           = 0x000000D0,
+	.bus_overflow_status           = 0x00000868,
+	.top_debug_cfg                 = 0x0000007C,
+	.lcr_supported                 = false,
+	.ir_supported                  = true,
+	.qcfa_only                     = false,
+	.num_sfe_mode                  = ARRAY_SIZE(sfe_780_mode),
+	.sfe_mode                      = sfe_780_mode,
+	.ipp_violation_mask            = 0x4000,
+	.num_debug_registers           = 18,
+	.top_debug = {
+		0x0000004C,
+		0x00000050,
+		0x00000054,
+		0x00000058,
+		0x0000005C,
+		0x00000060,
+		0x00000064,
+		0x00000068,
+		0x0000006C,
+		0x00000070,
+		0x00000074,
+		0x00000078,
+		0x000000D4,
+		0x000000D8,
+		0x000000DC,
+		0x000000E0,
+		0x000000E4,
+		0x000000E8,
+	},
+};
+
+static struct cam_sfe_modules_common_reg_offset sfe780_modules_common_reg = {
+	.demux_module_cfg              = 0x00003060,
+	.demux_xcfa_cfg                = 0x00003064,
+	.demux_hdr_cfg                 = 0x00003074,
+	.hdrc_remo_mod_cfg             = 0x00005860,
+	.xcfa_hdrc_remo_out_mux_cfg    = 0x00005A74,
+	.hdrc_remo_xcfa_bin_cfg        = 0x00005A78,
+};
+
+static struct cam_sfe_top_common_reg_data sfe_780_top_common_reg_data = {
+	.error_irq_mask                = 0x6C000,
+	.enable_diagnostic_hw          = 0x1,
+	.top_debug_cfg_en              = 0x3,
+	.sensor_sel_shift              = 0x1,
+};
+
+static struct cam_sfe_path_common_reg_data sfe_780_pix_reg_data = {
+	.sof_irq_mask                  = 0x4,
+	.eof_irq_mask                  = 0x8,
+	.subscribe_irq_mask            = 0xC,
+};
+
+static struct cam_sfe_path_common_reg_data sfe_780_rdi0_reg_data = {
+	.sof_irq_mask                  = 0x10,
+	.eof_irq_mask                  = 0x20,
+	.subscribe_irq_mask            = 0x30,
+};
+
+static struct cam_sfe_path_common_reg_data sfe_780_rdi1_reg_data = {
+	.sof_irq_mask                  = 0x40,
+	.eof_irq_mask                  = 0x80,
+	.subscribe_irq_mask            = 0xC0,
+};
+
+static struct cam_sfe_path_common_reg_data sfe_780_rdi2_reg_data = {
+	.sof_irq_mask                  = 0x100,
+	.eof_irq_mask                  = 0x200,
+	.subscribe_irq_mask            = 0x300,
+};
+
+static struct cam_sfe_path_common_reg_data sfe_780_rdi3_reg_data = {
+	.sof_irq_mask                  = 0x400,
+	.eof_irq_mask                  = 0x800,
+	.subscribe_irq_mask            = 0xC00,
+};
+
+static struct cam_sfe_path_common_reg_data sfe_780_rdi4_reg_data = {
+	.sof_irq_mask                  = 0x1000,
+	.eof_irq_mask                  = 0x2000,
+	.subscribe_irq_mask            = 0x3000,
+};
+
+static struct cam_sfe_top_hw_info sfe780_top_hw_info = {
+	.common_reg = &sfe780_top_commong_reg,
+	.modules_hw_info = &sfe780_modules_common_reg,
+	.common_reg_data = &sfe_780_top_common_reg_data,
+	.ipp_module_desc =  sfe_780_mod_desc,
+	.wr_client_desc  =  sfe_780_wr_client_desc,
+	.pix_reg_data    = &sfe_780_pix_reg_data,
+	.rdi_reg_data[0] = &sfe_780_rdi0_reg_data,
+	.rdi_reg_data[1] = &sfe_780_rdi1_reg_data,
+	.rdi_reg_data[2] = &sfe_780_rdi2_reg_data,
+	.rdi_reg_data[3] = &sfe_780_rdi3_reg_data,
+	.rdi_reg_data[4] = &sfe_780_rdi4_reg_data,
+	.num_inputs = 6,
+	.input_type = {
+		CAM_SFE_PIX_VER_1_0,
+		CAM_SFE_RDI_VER_1_0,
+		CAM_SFE_RDI_VER_1_0,
+		CAM_SFE_RDI_VER_1_0,
+		CAM_SFE_RDI_VER_1_0,
+		CAM_SFE_RDI_VER_1_0,
+	},
+	.num_top_errors  = ARRAY_SIZE(sfe_780_top_irq_err_desc),
+	.top_err_desc    = sfe_780_top_irq_err_desc,
+	.num_clc_module  = 11,
+	.clc_dbg_mod_info = &sfe780_clc_dbg_module_info,
+};
+
+static struct cam_irq_register_set sfe780_bus_rd_irq_reg[1] = {
+	{
+		.mask_reg_offset   = 0x00000404,
+		.clear_reg_offset  = 0x00000408,
+		.status_reg_offset = 0x00000410,
+	},
+};
+
+static struct cam_sfe_bus_rd_hw_info sfe780_bus_rd_hw_info = {
+	.common_reg = {
+		.hw_version                   = 0x00000400,
+		.misr_reset                   = 0x0000041C,
+		.pwr_iso_cfg                  = 0x00000424,
+		.input_if_cmd                 = 0x00000414,
+		.test_bus_ctrl                = 0x0000042C,
+		.security_cfg                 = 0x00000420,
+		.cons_violation_status        = 0x00000434,
+		.irq_reg_info = {
+			.num_registers     = 1,
+			.irq_reg_set          = sfe780_bus_rd_irq_reg,
+			.global_clear_offset  = 0x0000040C,
+			.global_clear_bitmask = 0x00000001,
+		},
+	},
+	.num_client = 3,
+	.bus_client_reg = {
+		/* BUS Client 0 */
+		{
+			.cfg                      = 0x00000450,
+			.image_addr               = 0x00000458,
+			.buf_width                = 0x0000045C,
+			.buf_height               = 0x00000460,
+			.stride                   = 0x00000464,
+			.unpacker_cfg             = 0x00000468,
+			.latency_buf_allocation   = 0x0000047C,
+			.system_cache_cfg         = 0x0000049C,
+			.addr_cfg                 = 0x000004A4,
+		},
+		/* BUS Client 1 */
+		{
+			.cfg                      = 0x000004F0,
+			.image_addr               = 0x000004F8,
+			.buf_width                = 0x000004FC,
+			.buf_height               = 0x00000500,
+			.stride                   = 0x00000504,
+			.unpacker_cfg             = 0x00000508,
+			.latency_buf_allocation   = 0x0000051C,
+			.system_cache_cfg         = 0x0000053C,
+			.addr_cfg                 = 0x00000544,
+		},
+		/* BUS Client 2 */
+		{
+			.cfg                      = 0x00000590,
+			.image_addr               = 0x00000598,
+			.buf_width                = 0x0000059C,
+			.buf_height               = 0x000005A0,
+			.stride                   = 0x000005A4,
+			.unpacker_cfg             = 0x000005A8,
+			.latency_buf_allocation   = 0x000005BC,
+			.system_cache_cfg         = 0x000005DC,
+			.addr_cfg                 = 0x000005E4,
+		},
+	},
+	.num_bus_rd_resc = 3,
+	.sfe_bus_rd_info = {
+		{
+			.sfe_bus_rd_type = CAM_SFE_BUS_RD_RDI0,
+			.mid[0] = 0,
+			.max_width     = -1,
+			.max_height    = -1,
+		},
+		{
+			.sfe_bus_rd_type = CAM_SFE_BUS_RD_RDI1,
+			.mid[0] = 1,
+			.max_width     = -1,
+			.max_height    = -1,
+		},
+		{
+			.sfe_bus_rd_type = CAM_SFE_BUS_RD_RDI2,
+			.mid[0] = 2,
+			.max_width     = -1,
+			.max_height    = -1,
+		},
+	},
+	.top_irq_shift = 0x1,
+};
+
+static struct cam_irq_register_set sfe780_bus_wr_irq_reg[1] = {
+	{
+		.mask_reg_offset   = 0x00000818,
+		.clear_reg_offset  = 0x00000820,
+		.status_reg_offset = 0x00000828,
+	},
+};
+
+static struct cam_sfe_bus_wr_hw_info sfe780_bus_wr_hw_info = {
+	.common_reg = {
+		.hw_version                       = 0x00000800,
+		.cgc_ovd                          = 0x00000808,
+		.if_frameheader_cfg               = {
+			0x00000834,
+			0x00000838,
+			0x0000083C,
+			0x00000840,
+			0x00000844,
+			0x00000848,
+		},
+		.pwr_iso_cfg                      = 0x0000085C,
+		.overflow_status_clear            = 0x00000860,
+		.ccif_violation_status            = 0x00000864,
+		.overflow_status                  = 0x00000868,
+		.image_size_violation_status      = 0x00000870,
+		.debug_status_top_cfg             = 0x000008D4,
+		.debug_status_top                 = 0x000008D8,
+		.test_bus_ctrl                    = 0x000008DC,
+		.top_irq_mask_0                   = 0x00000020,
+		.irq_reg_info = {
+			.num_registers     = 1,
+			.irq_reg_set          = sfe780_bus_wr_irq_reg,
+			.global_clear_offset  = 0x00000830,
+			.global_clear_bitmask = 0x00000001,
+		},
+	},
+	.num_client = 16,
+	.bus_client_reg = {
+		/* BUS Client 0 REMOSAIC */
+		{
+			.cfg                      = 0x00000A00,
+			.image_addr               = 0x00000A04,
+			.frame_incr               = 0x00000A08,
+			.image_cfg_0              = 0x00000A0C,
+			.image_cfg_1              = 0x00000A10,
+			.image_cfg_2              = 0x00000A14,
+			.packer_cfg               = 0x00000A18,
+			.frame_header_addr        = 0x00000A20,
+			.frame_header_incr        = 0x00000A24,
+			.frame_header_cfg         = 0x00000A28,
+			.line_done_cfg            = 0,
+			.irq_subsample_period     = 0x00000A30,
+			.irq_subsample_pattern    = 0x00000A34,
+			.framedrop_period         = 0x00000A38,
+			.framedrop_pattern        = 0x00000A3C,
+			.system_cache_cfg         = 0x00000A68,
+			.addr_cfg                 = 0x00000A70,
+			.addr_status_0            = 0x00000A74,
+			.addr_status_1            = 0x00000A78,
+			.addr_status_2            = 0x00000A7C,
+			.addr_status_3            = 0x00000A80,
+			.debug_status_cfg         = 0x00000A84,
+			.debug_status_0           = 0x00000A88,
+			.debug_status_1           = 0x00000A8C,
+			.mmu_prefetch_cfg         = 0x00000A60,
+			.mmu_prefetch_max_offset  = 0x00000A64,
+			.bw_limiter_addr          = 0x00000A1C,
+			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_0,
+		},
+		/* BUS Client 1 IR OUT */
+		{
+			.cfg                      = 0x00000B00,
+			.image_addr               = 0x00000B04,
+			.frame_incr               = 0x00000B08,
+			.image_cfg_0              = 0x00000B0C,
+			.image_cfg_1              = 0x00000B10,
+			.image_cfg_2              = 0x00000B14,
+			.packer_cfg               = 0x00000B18,
+			.frame_header_addr        = 0x00000B20,
+			.frame_header_incr        = 0x00000B24,
+			.frame_header_cfg         = 0x00000B28,
+			.line_done_cfg            = 0,
+			.irq_subsample_period     = 0x00000B30,
+			.irq_subsample_pattern    = 0x00000B34,
+			.framedrop_period         = 0x00000B38,
+			.framedrop_pattern        = 0x00000B3C,
+			.system_cache_cfg         = 0x00000B68,
+			.addr_cfg                 = 0x00000B70,
+			.addr_status_0            = 0x00000B74,
+			.addr_status_1            = 0x00000B78,
+			.addr_status_2            = 0x00000B7C,
+			.addr_status_3            = 0x00000B80,
+			.debug_status_cfg         = 0x00000B84,
+			.debug_status_0           = 0x00000B88,
+			.debug_status_1           = 0x00000B8C,
+			.mmu_prefetch_cfg         = 0x00000B60,
+			.mmu_prefetch_max_offset  = 0x00000B64,
+			.bw_limiter_addr          = 0x00000B1C,
+			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_1,
+		},
+		/* BUS Client 2 STATS_BE_0 */
+		{
+			.cfg                      = 0x00000C00,
+			.image_addr               = 0x00000C04,
+			.frame_incr               = 0x00000C08,
+			.image_cfg_0              = 0x00000C0C,
+			.image_cfg_1              = 0x00000C10,
+			.image_cfg_2              = 0x00000C14,
+			.packer_cfg               = 0x00000C18,
+			.frame_header_addr        = 0x00000C20,
+			.frame_header_incr        = 0x00000C24,
+			.frame_header_cfg         = 0x00000C28,
+			.line_done_cfg            = 0,
+			.irq_subsample_period     = 0x00000C30,
+			.irq_subsample_pattern    = 0x00000C34,
+			.framedrop_period         = 0x00000C38,
+			.framedrop_pattern        = 0x00000C3C,
+			.system_cache_cfg         = 0x00000C68,
+			.addr_cfg                 = 0x00000C70,
+			.addr_status_0            = 0x00000C74,
+			.addr_status_1            = 0x00000C78,
+			.addr_status_2            = 0x00000C7C,
+			.addr_status_3            = 0x00000C80,
+			.debug_status_cfg         = 0x00000C84,
+			.debug_status_0           = 0x00000C88,
+			.debug_status_1           = 0x00000C8C,
+			.mmu_prefetch_cfg         = 0x00000C60,
+			.mmu_prefetch_max_offset  = 0x00000C64,
+			.bw_limiter_addr          = 0x00000C1C,
+			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_2,
+		},
+		/* BUS Client 3 STATS_BHIST_0 */
+		{
+			.cfg                      = 0x00000D00,
+			.image_addr               = 0x00000D04,
+			.frame_incr               = 0x00000D08,
+			.image_cfg_0              = 0x00000D0C,
+			.image_cfg_1              = 0x00000D10,
+			.image_cfg_2              = 0x00000D14,
+			.packer_cfg               = 0x00000D18,
+			.frame_header_addr        = 0x00000D20,
+			.frame_header_incr        = 0x00000D24,
+			.frame_header_cfg         = 0x00000D28,
+			.line_done_cfg            = 0,
+			.irq_subsample_period     = 0x00000D30,
+			.irq_subsample_pattern    = 0x00000D34,
+			.framedrop_period         = 0x00000D38,
+			.framedrop_pattern        = 0x00000D3C,
+			.system_cache_cfg         = 0x00000D68,
+			.addr_cfg                 = 0x00000D70,
+			.addr_status_0            = 0x00000D74,
+			.addr_status_1            = 0x00000D78,
+			.addr_status_2            = 0x00000D7C,
+			.addr_status_3            = 0x00000D80,
+			.debug_status_cfg         = 0x00000D84,
+			.debug_status_0           = 0x00000D88,
+			.debug_status_1           = 0x00000D8C,
+			.mmu_prefetch_cfg         = 0x00000D60,
+			.mmu_prefetch_max_offset  = 0x00000D64,
+			.bw_limiter_addr          = 0x00000D1C,
+			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_2,
+		},
+		/* BUS Client 4 STATS_BE_1 */
+		{
+			.cfg                      = 0x00000E00,
+			.image_addr               = 0x00000E04,
+			.frame_incr               = 0x00000E08,
+			.image_cfg_0              = 0x00000E0C,
+			.image_cfg_1              = 0x00000E10,
+			.image_cfg_2              = 0x00000E14,
+			.packer_cfg               = 0x00000E18,
+			.frame_header_addr        = 0x00000E20,
+			.frame_header_incr        = 0x00000E24,
+			.frame_header_cfg         = 0x00000E28,
+			.line_done_cfg            = 0,
+			.irq_subsample_period     = 0x00000E30,
+			.irq_subsample_pattern    = 0x00000E34,
+			.framedrop_period         = 0x00000E38,
+			.framedrop_pattern        = 0x00000E3C,
+			.system_cache_cfg         = 0x00000E68,
+			.addr_cfg                 = 0x00000E70,
+			.addr_status_0            = 0x00000E74,
+			.addr_status_1            = 0x00000E78,
+			.addr_status_2            = 0x00000E7C,
+			.addr_status_3            = 0x00000E80,
+			.debug_status_cfg         = 0x00000E84,
+			.debug_status_0           = 0x00000E88,
+			.debug_status_1           = 0x00000E8C,
+			.mmu_prefetch_cfg         = 0x00000E60,
+			.mmu_prefetch_max_offset  = 0x00000E64,
+			.bw_limiter_addr          = 0x00000E1C,
+			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_3,
+		},
+		/* BUS Client 5 STATS_BHIST_1 */
+		{
+			.cfg                      = 0x00000F00,
+			.image_addr               = 0x00000F04,
+			.frame_incr               = 0x00000F08,
+			.image_cfg_0              = 0x00000F0C,
+			.image_cfg_1              = 0x00000F10,
+			.image_cfg_2              = 0x00000F14,
+			.packer_cfg               = 0x00000F18,
+			.frame_header_addr        = 0x00000F20,
+			.frame_header_incr        = 0x00000F24,
+			.frame_header_cfg         = 0x00000F28,
+			.line_done_cfg            = 0,
+			.irq_subsample_period     = 0x00000F30,
+			.irq_subsample_pattern    = 0x00000F34,
+			.framedrop_period         = 0x00000F38,
+			.framedrop_pattern        = 0x00000F3C,
+			.system_cache_cfg         = 0x00000F68,
+			.addr_cfg                 = 0x00000F70,
+			.addr_status_0            = 0x00000F74,
+			.addr_status_1            = 0x00000F78,
+			.addr_status_2            = 0x00000F7C,
+			.addr_status_3            = 0x00000F80,
+			.debug_status_cfg         = 0x00000F84,
+			.debug_status_0           = 0x00000F88,
+			.debug_status_1           = 0x00000F8C,
+			.mmu_prefetch_cfg         = 0x00000F60,
+			.mmu_prefetch_max_offset  = 0x00000F64,
+			.bw_limiter_addr          = 0x00000F1C,
+			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_3,
+		},
+		/* BUS Client 6 STATS_BE_2 */
+		{
+			.cfg                      = 0x00001000,
+			.image_addr               = 0x00001004,
+			.frame_incr               = 0x00001008,
+			.image_cfg_0              = 0x0000100C,
+			.image_cfg_1              = 0x00001010,
+			.image_cfg_2              = 0x00001014,
+			.packer_cfg               = 0x00001018,
+			.frame_header_addr        = 0x00001020,
+			.frame_header_incr        = 0x00001024,
+			.frame_header_cfg         = 0x00001028,
+			.line_done_cfg            = 0,
+			.irq_subsample_period     = 0x00001030,
+			.irq_subsample_pattern    = 0x00001034,
+			.framedrop_period         = 0x00001038,
+			.framedrop_pattern        = 0x0000103C,
+			.system_cache_cfg         = 0x00001068,
+			.addr_cfg                 = 0x00001070,
+			.addr_status_0            = 0x00001074,
+			.addr_status_1            = 0x00001078,
+			.addr_status_2            = 0x0000107C,
+			.addr_status_3            = 0x00001080,
+			.debug_status_cfg         = 0x00001084,
+			.debug_status_0           = 0x00001088,
+			.debug_status_1           = 0x0000108C,
+			.mmu_prefetch_cfg         = 0x00001060,
+			.mmu_prefetch_max_offset  = 0x00001064,
+			.bw_limiter_addr          = 0x0000101C,
+			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_4,
+		},
+		/* BUS Client 7 STATS_BHIST_2 */
+		{
+			.cfg                      = 0x00001100,
+			.image_addr               = 0x00001104,
+			.frame_incr               = 0x00001108,
+			.image_cfg_0              = 0x0000110C,
+			.image_cfg_1              = 0x00001110,
+			.image_cfg_2              = 0x00001114,
+			.packer_cfg               = 0x00001118,
+			.frame_header_addr        = 0x00001120,
+			.frame_header_incr        = 0x00001124,
+			.frame_header_cfg         = 0x00001128,
+			.line_done_cfg            = 0,
+			.irq_subsample_period     = 0x00001130,
+			.irq_subsample_pattern    = 0x00001134,
+			.framedrop_period         = 0x00001138,
+			.framedrop_pattern        = 0x0000113C,
+			.system_cache_cfg         = 0x00001168,
+			.addr_cfg                 = 0x00001170,
+			.addr_status_0            = 0x00001174,
+			.addr_status_1            = 0x00001178,
+			.addr_status_2            = 0x0000117C,
+			.addr_status_3            = 0x00001180,
+			.debug_status_cfg         = 0x00001184,
+			.debug_status_0           = 0x00001188,
+			.debug_status_1           = 0x0000118C,
+			.mmu_prefetch_cfg         = 0x00001160,
+			.mmu_prefetch_max_offset  = 0x00001164,
+			.bw_limiter_addr          = 0x0000111C,
+			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_4,
+		},
+		/* BUS Client 8 STATS_RS_0 */
+		{
+			.cfg                      = 0x00001200,
+			.image_addr               = 0x00001204,
+			.frame_incr               = 0x00001208,
+			.image_cfg_0              = 0x0000120C,
+			.image_cfg_1              = 0x00001210,
+			.image_cfg_2              = 0x00001214,
+			.packer_cfg               = 0x00001218,
+			.frame_header_addr        = 0x00001220,
+			.frame_header_incr        = 0x00001224,
+			.frame_header_cfg         = 0x00001228,
+			.line_done_cfg            = 0,
+			.irq_subsample_period     = 0x00001230,
+			.irq_subsample_pattern    = 0x00001234,
+			.framedrop_period         = 0x00001238,
+			.framedrop_pattern        = 0x0000123C,
+			.system_cache_cfg         = 0x00001268,
+			.addr_cfg                 = 0x00001270,
+			.addr_status_0            = 0x00001274,
+			.addr_status_1            = 0x00001278,
+			.addr_status_2            = 0x0000127C,
+			.addr_status_3            = 0x00001280,
+			.debug_status_cfg         = 0x00001284,
+			.debug_status_0           = 0x00001288,
+			.debug_status_1           = 0x0000128C,
+			.mmu_prefetch_cfg         = 0x00001260,
+			.mmu_prefetch_max_offset  = 0x00001264,
+			.bw_limiter_addr          = 0x0000121C,
+			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_2,
+		},
+		/* BUS Client 9 STATS_RS_1 */
+		{
+			.cfg                      = 0x00001300,
+			.image_addr               = 0x00001304,
+			.frame_incr               = 0x00001308,
+			.image_cfg_0              = 0x0000130C,
+			.image_cfg_1              = 0x00001310,
+			.image_cfg_2              = 0x00001314,
+			.packer_cfg               = 0x00001318,
+			.frame_header_addr        = 0x00001320,
+			.frame_header_incr        = 0x00001324,
+			.frame_header_cfg         = 0x00001328,
+			.line_done_cfg            = 0,
+			.irq_subsample_period     = 0x00001330,
+			.irq_subsample_pattern    = 0x00001334,
+			.framedrop_period         = 0x00001338,
+			.framedrop_pattern        = 0x0000133C,
+			.system_cache_cfg         = 0x00001368,
+			.addr_cfg                 = 0x00001370,
+			.addr_status_0            = 0x00001374,
+			.addr_status_1            = 0x00001378,
+			.addr_status_2            = 0x0000137C,
+			.addr_status_3            = 0x00001380,
+			.debug_status_cfg         = 0x00001384,
+			.debug_status_0           = 0x00001388,
+			.debug_status_1           = 0x0000138C,
+			.mmu_prefetch_cfg         = 0x00001360,
+			.mmu_prefetch_max_offset  = 0x00001364,
+			.bw_limiter_addr          = 0x0000131C,
+			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_3,
+		},
+		/* BUS Client 10 STATS_RS_2 */
+		{
+			.cfg                      = 0x00001400,
+			.image_addr               = 0x00001404,
+			.frame_incr               = 0x00001408,
+			.image_cfg_0              = 0x0000140C,
+			.image_cfg_1              = 0x00001410,
+			.image_cfg_2              = 0x00001414,
+			.packer_cfg               = 0x00001418,
+			.frame_header_addr        = 0x00001420,
+			.frame_header_incr        = 0x00001424,
+			.frame_header_cfg         = 0x00001428,
+			.line_done_cfg            = 0,
+			.irq_subsample_period     = 0x00001430,
+			.irq_subsample_pattern    = 0x00001434,
+			.framedrop_period         = 0x00001438,
+			.framedrop_pattern        = 0x0000143C,
+			.system_cache_cfg         = 0x00001468,
+			.addr_cfg                 = 0x00001470,
+			.addr_status_0            = 0x00001474,
+			.addr_status_1            = 0x00001478,
+			.addr_status_2            = 0x0000147C,
+			.addr_status_3            = 0x00001480,
+			.debug_status_cfg         = 0x00001484,
+			.debug_status_0           = 0x00001488,
+			.debug_status_1           = 0x0000148C,
+			.mmu_prefetch_cfg         = 0x00001460,
+			.mmu_prefetch_max_offset  = 0x00001464,
+			.bw_limiter_addr          = 0x0000141C,
+			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_4,
+		},
+		/* BUS Client 11 RDI0 */
+		{
+			.cfg                      = 0x00001500,
+			.image_addr               = 0x00001504,
+			.frame_incr               = 0x00001508,
+			.image_cfg_0              = 0x0000150C,
+			.image_cfg_1              = 0x00001510,
+			.image_cfg_2              = 0x00001514,
+			.packer_cfg               = 0x00001518,
+			.frame_header_addr        = 0x00001520,
+			.frame_header_incr        = 0x00001524,
+			.frame_header_cfg         = 0x00001528,
+			.line_done_cfg            = 0x0000152C,
+			.irq_subsample_period     = 0x00001530,
+			.irq_subsample_pattern    = 0x00001534,
+			.framedrop_period         = 0x00001538,
+			.framedrop_pattern        = 0x0000153C,
+			.system_cache_cfg         = 0x00001568,
+			.addr_cfg                 = 0x00001574,
+			.addr_status_0            = 0x00001574,
+			.addr_status_1            = 0x00001578,
+			.addr_status_2            = 0x0000157C,
+			.addr_status_3            = 0x00001580,
+			.debug_status_cfg         = 0x00001584,
+			.debug_status_0           = 0x00001588,
+			.debug_status_1           = 0x0000158C,
+			.mmu_prefetch_cfg         = 0x00001560,
+			.mmu_prefetch_max_offset  = 0x00001564,
+			.bw_limiter_addr          = 0x0000151C,
+			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_5,
+		},
+		/* BUS Client 12 RDI1 */
+		{
+			.cfg                      = 0x00001600,
+			.image_addr               = 0x00001604,
+			.frame_incr               = 0x00001608,
+			.image_cfg_0              = 0x0000160C,
+			.image_cfg_1              = 0x00001610,
+			.image_cfg_2              = 0x00001614,
+			.packer_cfg               = 0x00001618,
+			.frame_header_addr        = 0x00001620,
+			.frame_header_incr        = 0x00001624,
+			.frame_header_cfg         = 0x00001628,
+			.line_done_cfg            = 0x0000162C,
+			.irq_subsample_period     = 0x00001630,
+			.irq_subsample_pattern    = 0x00001634,
+			.framedrop_period         = 0x00001638,
+			.framedrop_pattern        = 0x0000163C,
+			.system_cache_cfg         = 0x00001668,
+			.addr_cfg                 = 0x00001670,
+			.addr_status_0            = 0x00001674,
+			.addr_status_1            = 0x00001678,
+			.addr_status_2            = 0x0000167C,
+			.addr_status_3            = 0x00001680,
+			.debug_status_cfg         = 0x00001684,
+			.debug_status_0           = 0x00001688,
+			.debug_status_1           = 0x0000168C,
+			.mmu_prefetch_cfg         = 0x00001660,
+			.mmu_prefetch_max_offset  = 0x00001664,
+			.bw_limiter_addr          = 0x0000161C,
+			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_6,
+		},
+		/* BUS Client 13 RDI2 */
+		{
+			.cfg                      = 0x00001700,
+			.image_addr               = 0x00001704,
+			.frame_incr               = 0x00001708,
+			.image_cfg_0              = 0x0000170C,
+			.image_cfg_1              = 0x00001710,
+			.image_cfg_2              = 0x00001714,
+			.packer_cfg               = 0x00001718,
+			.frame_header_addr        = 0x00001720,
+			.frame_header_incr        = 0x00001724,
+			.frame_header_cfg         = 0x00001728,
+			.line_done_cfg            = 0x0000172C,
+			.irq_subsample_period     = 0x00001730,
+			.irq_subsample_pattern    = 0x00001734,
+			.framedrop_period         = 0x00001738,
+			.framedrop_pattern        = 0x0000173C,
+			.system_cache_cfg         = 0x00001768,
+			.addr_cfg                 = 0x00001770,
+			.addr_status_0            = 0x00001774,
+			.addr_status_1            = 0x00001778,
+			.addr_status_2            = 0x0000177C,
+			.addr_status_3            = 0x00001780,
+			.debug_status_cfg         = 0x00001784,
+			.debug_status_0           = 0x00001788,
+			.debug_status_1           = 0x0000178C,
+			.mmu_prefetch_cfg         = 0x00001760,
+			.mmu_prefetch_max_offset  = 0x00001764,
+			.bw_limiter_addr          = 0x0000171C,
+			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_7,
+		},
+		/* BUS Client 14 RDI3 */
+		{
+			.cfg                      = 0x00001800,
+			.image_addr               = 0x00001804,
+			.frame_incr               = 0x00001808,
+			.image_cfg_0              = 0x0000180C,
+			.image_cfg_1              = 0x00001810,
+			.image_cfg_2              = 0x00001814,
+			.packer_cfg               = 0x00001818,
+			.frame_header_addr        = 0x00001820,
+			.frame_header_incr        = 0x00001824,
+			.frame_header_cfg         = 0x00001828,
+			.line_done_cfg            = 0x0000182C,
+			.irq_subsample_period     = 0x00001830,
+			.irq_subsample_pattern    = 0x00001834,
+			.framedrop_period         = 0x00001838,
+			.framedrop_pattern        = 0x0000183C,
+			.system_cache_cfg         = 0x00001868,
+			.addr_cfg                 = 0x00001870,
+			.addr_status_0            = 0x00001874,
+			.addr_status_1            = 0x00001878,
+			.addr_status_2            = 0x0000187C,
+			.addr_status_3            = 0x00001880,
+			.debug_status_cfg         = 0x00001884,
+			.debug_status_0           = 0x00001888,
+			.debug_status_1           = 0x0000188C,
+			.mmu_prefetch_cfg         = 0x00001860,
+			.mmu_prefetch_max_offset  = 0x00001864,
+			.bw_limiter_addr          = 0x0000181C,
+			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_8,
+		},
+		/* BUS Client 15 RDI4 */
+		{
+			.cfg                      = 0x00001900,
+			.image_addr               = 0x00001904,
+			.frame_incr               = 0x00001908,
+			.image_cfg_0              = 0x0000190C,
+			.image_cfg_1              = 0x00001910,
+			.image_cfg_2              = 0x00001914,
+			.packer_cfg               = 0x00001918,
+			.frame_header_addr        = 0x00001920,
+			.frame_header_incr        = 0x00001924,
+			.frame_header_cfg         = 0x00001928,
+			.line_done_cfg            = 0x0000192C,
+			.irq_subsample_period     = 0x00001930,
+			.irq_subsample_pattern    = 0x00001934,
+			.framedrop_period         = 0x00001938,
+			.framedrop_pattern        = 0x0000193C,
+			.system_cache_cfg         = 0x00001968,
+			.addr_cfg                 = 0x00001970,
+			.addr_status_0            = 0x00001974,
+			.addr_status_1            = 0x00001978,
+			.addr_status_2            = 0x0000197C,
+			.addr_status_3            = 0x00001980,
+			.debug_status_cfg         = 0x00001984,
+			.debug_status_0           = 0x00001988,
+			.debug_status_1           = 0x0000198C,
+			.mmu_prefetch_cfg         = 0x00001960,
+			.mmu_prefetch_max_offset  = 0x00001964,
+			.bw_limiter_addr          = 0x0000191C,
+			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_9,
+		},
+	},
+	.num_out = 16,
+	.sfe_out_hw_info = {
+		{
+			.sfe_out_type  = CAM_SFE_BUS_SFE_OUT_RDI0,
+			.max_width     = -1,
+			.max_height    = -1,
+			.source_group  = CAM_SFE_BUS_WR_SRC_GRP_1,
+			.mid[0]        = 45,
+			.num_wm        = 1,
+			.wm_idx        = 11,
+			.name          = "RDI_0",
+		},
+		{
+			.sfe_out_type  = CAM_SFE_BUS_SFE_OUT_RDI1,
+			.max_width     = -1,
+			.max_height    = -1,
+			.source_group  = CAM_SFE_BUS_WR_SRC_GRP_2,
+			.mid[0]        = 46,
+			.num_wm        = 1,
+			.wm_idx        = 12,
+			.name          = "RDI_1",
+		},
+		{
+			.sfe_out_type  = CAM_SFE_BUS_SFE_OUT_RDI2,
+			.max_width     = -1,
+			.max_height    = -1,
+			.source_group  = CAM_SFE_BUS_WR_SRC_GRP_3,
+			.mid[0]        = 47,
+			.num_wm        = 1,
+			.wm_idx        = 13,
+			.name          = "RDI_2",
+		},
+		{
+			.sfe_out_type  = CAM_SFE_BUS_SFE_OUT_RDI3,
+			.max_width     = -1,
+			.max_height    = -1,
+			.source_group  = CAM_SFE_BUS_WR_SRC_GRP_4,
+			.mid[0]        = 48,
+			.num_wm        = 1,
+			.wm_idx        = 14,
+			.name          = "RDI_3",
+		},
+		{
+			.sfe_out_type  = CAM_SFE_BUS_SFE_OUT_RDI4,
+			.max_width     = -1,
+			.max_height    = -1,
+			.source_group  = CAM_SFE_BUS_WR_SRC_GRP_5,
+			.mid[0]        = 49,
+			.num_wm        = 1,
+			.wm_idx        = 15,
+			.name          = "RDI_4",
+		},
+		{
+			.sfe_out_type  = CAM_SFE_BUS_SFE_OUT_RAW_DUMP,
+			.max_width     = 9312,
+			.max_height    = 6992,
+			.source_group  = CAM_SFE_BUS_WR_SRC_GRP_0,
+			.mid[0]        = 32,
+			.mid[1]        = 33,
+			.num_wm        = 1,
+			.wm_idx        = 0,
+			.name          = "REMOSIAC",
+		},
+		{
+			.sfe_out_type  = CAM_SFE_BUS_SFE_OUT_IR,
+			.max_width     = 9312,
+			.max_height    = 6772,
+			.source_group  = CAM_SFE_BUS_WR_SRC_GRP_0,
+			.mid[0]        = 34,
+			.mid[1]        = 35,
+			.num_wm        = 1,
+			.wm_idx        = 1,
+			.name          = "IR_OUT",
+		},
+		{
+			.sfe_out_type  = CAM_SFE_BUS_SFE_OUT_BE_0,
+			.max_width     = 7296,
+			.max_height    = 5472,
+			.source_group  = CAM_SFE_BUS_WR_SRC_GRP_0,
+			.mid[0]        = 36,
+			.num_wm        = 1,
+			.wm_idx        = 2,
+			.name          = "STATS_BE_0",
+		},
+		{
+			.sfe_out_type  = CAM_SFE_BUS_SFE_OUT_BHIST_0,
+			.max_width     = 7296,
+			.max_height    = 5472,
+			.source_group  = CAM_SFE_BUS_WR_SRC_GRP_0,
+			.mid[0]        = 37,
+			.num_wm        = 1,
+			.wm_idx        = 3,
+			.name          = "STATS_BHIST_0",
+		},
+		{
+			.sfe_out_type  = CAM_SFE_BUS_SFE_OUT_BE_1,
+			.max_width     = 7296,
+			.max_height    = 5472,
+			.source_group  = CAM_SFE_BUS_WR_SRC_GRP_0,
+			.mid[0]        = 38,
+			.num_wm        = 1,
+			.wm_idx        = 4,
+			.name          = "STATS_BE_1",
+		},
+		{
+			.sfe_out_type  = CAM_SFE_BUS_SFE_OUT_BHIST_1,
+			.max_width     = 7296,
+			.max_height    = 5472,
+			.source_group  = CAM_SFE_BUS_WR_SRC_GRP_0,
+			.mid[0]        = 39,
+			.num_wm        = 1,
+			.wm_idx        = 5,
+			.name          = "STATS_BHIST_1",
+		},
+		{
+			.sfe_out_type  = CAM_SFE_BUS_SFE_OUT_BE_2,
+			.max_width     = 7296,
+			.max_height    = 5472,
+			.source_group  = CAM_SFE_BUS_WR_SRC_GRP_0,
+			.mid[0]        = 40,
+			.num_wm        = 1,
+			.wm_idx        = 6,
+			.name          = "STATS_BE_2",
+		},
+		{
+			.sfe_out_type  = CAM_SFE_BUS_SFE_OUT_BHIST_2,
+			.max_width     = 7296,
+			.max_height    = 5472,
+			.source_group  = CAM_SFE_BUS_WR_SRC_GRP_0,
+			.mid[0]        = 41,
+			.num_wm        = 1,
+			.wm_idx        = 7,
+			.name          = "STATS_BHIST_2",
+		},
+		{
+			.sfe_out_type  = CAM_SFE_BUS_SFE_OUT_BAYER_RS_0,
+			.max_width     = 7296,
+			.max_height    = 5472,
+			.source_group  = CAM_SFE_BUS_WR_SRC_GRP_0,
+			.mid[0]        = 42,
+			.num_wm        = 1,
+			.wm_idx        = 8,
+			.name          = "STATS_RS_0",
+		},
+		{
+			.sfe_out_type  = CAM_SFE_BUS_SFE_OUT_BAYER_RS_1,
+			.max_width     = 7296,
+			.max_height    = 5472,
+			.source_group  = CAM_SFE_BUS_WR_SRC_GRP_0,
+			.mid[0]        = 43,
+			.num_wm        = 1,
+			.wm_idx        = 9,
+			.name          = "STATS_RS_1",
+		},
+		{
+			.sfe_out_type  = CAM_SFE_BUS_SFE_OUT_BAYER_RS_2,
+			.max_width     = 7296,
+			.max_height    = 5472,
+			.source_group  = CAM_SFE_BUS_WR_SRC_GRP_0,
+			.mid[0]        = 44,
+			.num_wm        = 1,
+			.wm_idx        = 10,
+			.name          = "STATS_RS_2",
+		},
+	},
+	.num_cons_err = 29,
+	.constraint_error_list = {
+		{
+			.bitmask = BIT(0),
+			.error_description = "PPC 1x1 input not supported"
+		},
+		{
+			.bitmask = BIT(1),
+			.error_description = "PPC 1x2 input not supported"
+		},
+		{
+			.bitmask = BIT(2),
+			.error_description = "PPC 2x1 input not supported"
+		},
+		{
+			.bitmask = BIT(3),
+			.error_description = "PPC 2x2 input not supported"
+		},
+		{
+			.bitmask = BIT(4),
+			.error_description = "Pack 8 BPP format not supported"
+		},
+		{
+			.bitmask = BIT(5),
+			.error_description = "Pack 16 format not supported"
+		},
+		{
+			.bitmask = BIT(6),
+			.error_description = "Pack 32 BPP format not supported"
+		},
+		{
+			.bitmask = BIT(7),
+			.error_description = "Pack 64 BPP format not supported"
+		},
+		{
+			.bitmask = BIT(8),
+			.error_description = "Pack MIPI 20 format not supported"
+		},
+		{
+			.bitmask = BIT(9),
+			.error_description = "Pack MIPI 14 format not supported"
+		},
+		{
+			.bitmask = BIT(10),
+			.error_description = "Pack MIPI 12 format not supported"
+		},
+		{
+			.bitmask = BIT(11),
+			.error_description = "Pack MIPI 10 format not supported"
+		},
+		{
+			.bitmask = BIT(12),
+			.error_description = "Pack 128 BPP format not supported"
+		},
+		{
+			.bitmask = BIT(13),
+			.error_description = "UBWC NV12 format not supported"
+		},
+		{
+			.bitmask = BIT(14),
+			.error_description = "UBWC NV12 4R format not supported"
+		},
+		{
+			.bitmask = BIT(15),
+			.error_description = "UBWC TP10 format not supported"
+		},
+		{
+			.bitmask = BIT(16),
+			.error_description = "Frame based Mode not supported"
+		},
+		{
+			.bitmask = BIT(17),
+			.error_description = "Index based Mode not supported"
+		},
+		{
+			.bitmask = BIT(18),
+			.error_description = "FIFO image addr unalign"
+		},
+		{
+			.bitmask = BIT(19),
+			.error_description = "FIFO ubwc addr unalign"
+		},
+		{
+			.bitmask = BIT(20),
+			.error_description = "FIFO frmheader addr unalign"
+		},
+		{
+			.bitmask = BIT(21),
+			.error_description = "Image address unalign"
+		},
+		{
+			.bitmask = BIT(22),
+			.error_description = "UBWC address unalign"
+		},
+		{
+			.bitmask = BIT(23),
+			.error_description = "Frame Header address unalign"
+		},
+		{
+			.bitmask = BIT(24),
+			.error_description = "Stride unalign"
+		},
+		{
+			.bitmask = BIT(25),
+			.error_description = "X Initialization unalign"
+		},
+		{
+			.bitmask = BIT(26),
+			.error_description = "Image Width unalign"
+		},
+		{
+			.bitmask = BIT(27),
+			.error_description = "Image Height unalign"
+		},
+		{
+			.bitmask = BIT(28),
+			.error_description = "Meta Stride unalign"
+		},
+	},
+	.num_comp_grp         = 10,
+	.comp_done_shift      = 17,
+	.line_done_cfg        = 0x11,
+	.top_irq_shift        = 0x0,
+	.max_bw_counter_limit = 0xFF,
+};
+
+static struct cam_irq_register_set sfe780_top_irq_reg_set[1] = {
+	{
+	.mask_reg_offset   = 0x00000020,
+	.clear_reg_offset  = 0x00000024,
+	.status_reg_offset = 0x00000028,
+	},
+};
+
+static struct cam_irq_controller_reg_info sfe780_top_irq_reg_info = {
+	.num_registers = 1,
+	.irq_reg_set = sfe780_top_irq_reg_set,
+	.global_clear_offset  = 0x0000001C,
+	.global_clear_bitmask = 0x00000001,
+};
+
+struct cam_sfe_hw_info cam_sfe780_hw_info = {
+	.irq_reg_info                  = &sfe780_top_irq_reg_info,
+
+	.bus_wr_version                = CAM_SFE_BUS_WR_VER_1_0,
+	.bus_wr_hw_info                = &sfe780_bus_wr_hw_info,
+
+	.bus_rd_version                = CAM_SFE_BUS_RD_VER_1_0,
+	.bus_rd_hw_info                = &sfe780_bus_rd_hw_info,
+
+	.top_version                   = CAM_SFE_TOP_VER_1_0,
+	.top_hw_info                   = &sfe780_top_hw_info,
+};
+
+#endif /* _CAM_SFE780_H_ */

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe_dev.c

@@ -11,6 +11,7 @@
 #include "cam_sfe_core.h"
 #include "cam_sfe_soc.h"
 #include "cam_sfe680.h"
+#include "cam_sfe780.h"
 #include "cam_debug_util.h"
 #include "camera_main.h"
 
@@ -225,6 +226,10 @@ static const struct of_device_id cam_sfe_dt_match[] = {
 		.compatible = "qcom,sfe680",
 		.data = &cam_sfe680_hw_info,
 	},
+	{
+		.compatible = "qcom,sfe780",
+		.data = &cam_sfe780_hw_info,
+	},
 	{}
 };
 MODULE_DEVICE_TABLE(of, cam_sfe_dt_match);

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_rd.h

@@ -47,6 +47,7 @@ struct cam_sfe_bus_rd_reg_offset_bus_client {
 	uint32_t unpacker_cfg;
 	uint32_t latency_buf_allocation;
 	uint32_t system_cache_cfg;
+	uint32_t addr_cfg;
 };
 
 /*

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_wr.c

@@ -196,6 +196,7 @@ struct cam_sfe_bus_wr_priv {
 	void                               *tasklet_info;
 	uint32_t                            num_cons_err;
 	struct cam_sfe_constraint_error_info      *constraint_error_list;
+	struct cam_sfe_bus_sfe_out_hw_info        *sfe_out_hw_info;
 };
 
 static int cam_sfe_bus_wr_process_cmd(
@@ -215,6 +216,7 @@ static bool cam_sfe_bus_can_be_secure(uint32_t out_type)
 	case CAM_SFE_BUS_SFE_OUT_RDI2:
 	case CAM_SFE_BUS_SFE_OUT_RDI3:
 	case CAM_SFE_BUS_SFE_OUT_RDI4:
+	case CAM_SFE_BUS_SFE_OUT_IR:
 		return true;
 	case CAM_SFE_BUS_SFE_OUT_LCR:
 	case CAM_SFE_BUS_SFE_OUT_BE_0:
@@ -223,6 +225,9 @@ static bool cam_sfe_bus_can_be_secure(uint32_t out_type)
 	case CAM_SFE_BUS_SFE_OUT_BHIST_1:
 	case CAM_SFE_BUS_SFE_OUT_BE_2:
 	case CAM_SFE_BUS_SFE_OUT_BHIST_2:
+	case CAM_SFE_BUS_SFE_OUT_BAYER_RS_0:
+	case CAM_SFE_BUS_SFE_OUT_BAYER_RS_1:
+	case CAM_SFE_BUS_SFE_OUT_BAYER_RS_2:
 	default:
 		return false;
 	}
@@ -258,6 +263,14 @@ static enum cam_sfe_bus_sfe_out_type
 		return CAM_SFE_BUS_SFE_OUT_BHIST_2;
 	case CAM_ISP_SFE_OUT_RES_LCR:
 		return CAM_SFE_BUS_SFE_OUT_LCR;
+	case CAM_ISP_SFE_OUT_RES_IR:
+		return CAM_SFE_BUS_SFE_OUT_IR;
+	case CAM_ISP_SFE_OUT_BAYER_RS_STATS_0:
+		return CAM_SFE_BUS_SFE_OUT_BAYER_RS_0;
+	case CAM_ISP_SFE_OUT_BAYER_RS_STATS_1:
+		return CAM_SFE_BUS_SFE_OUT_BAYER_RS_1;
+	case CAM_ISP_SFE_OUT_BAYER_RS_STATS_2:
+		return CAM_SFE_BUS_SFE_OUT_BAYER_RS_2;
 	default:
 		return CAM_SFE_BUS_SFE_OUT_MAX;
 	}
@@ -268,52 +281,90 @@ static int cam_sfe_bus_get_comp_sfe_out_res_id_list(
 {
 	int count = 0;
 
-	if (comp_mask & (1 << CAM_SFE_BUS_SFE_OUT_RDI0))
+	if (comp_mask & (BIT(CAM_SFE_BUS_SFE_OUT_RDI0)))
 		out_list[count++] = CAM_ISP_SFE_OUT_RES_RDI_0;
 
-	if (comp_mask & (1 << CAM_SFE_BUS_SFE_OUT_RDI1))
+	if (comp_mask & (BIT(CAM_SFE_BUS_SFE_OUT_RDI1)))
 		out_list[count++] = CAM_ISP_SFE_OUT_RES_RDI_1;
 
-	if (comp_mask & (1 << CAM_SFE_BUS_SFE_OUT_RDI2))
+	if (comp_mask & (BIT(CAM_SFE_BUS_SFE_OUT_RDI2)))
 		out_list[count++] = CAM_ISP_SFE_OUT_RES_RDI_2;
 
-	if (comp_mask & (1 << CAM_SFE_BUS_SFE_OUT_RDI3))
+	if (comp_mask & (BIT(CAM_SFE_BUS_SFE_OUT_RDI3)))
 		out_list[count++] = CAM_ISP_SFE_OUT_RES_RDI_3;
 
-	if (comp_mask & (1 << CAM_SFE_BUS_SFE_OUT_RDI4))
+	if (comp_mask & (BIT(CAM_SFE_BUS_SFE_OUT_RDI4)))
 		out_list[count++] = CAM_ISP_SFE_OUT_RES_RDI_4;
 
-	if (comp_mask & (1 << CAM_SFE_BUS_SFE_OUT_RAW_DUMP))
+	if (comp_mask & (BIT(CAM_SFE_BUS_SFE_OUT_RAW_DUMP)))
 		out_list[count++] = CAM_ISP_SFE_OUT_RES_RAW_DUMP;
 
-	if (comp_mask & (1 << CAM_SFE_BUS_SFE_OUT_BE_0))
+	if (comp_mask & (BIT(CAM_SFE_BUS_SFE_OUT_BE_0)))
 		out_list[count++] = CAM_ISP_SFE_OUT_BE_STATS_0;
 
-	if (comp_mask & (1 << CAM_SFE_BUS_SFE_OUT_BHIST_0))
+	if (comp_mask & (BIT(CAM_SFE_BUS_SFE_OUT_BHIST_0)))
 		out_list[count++] = CAM_ISP_SFE_OUT_BHIST_STATS_0;
 
-	if (comp_mask & (1 << CAM_SFE_BUS_SFE_OUT_BE_1))
+	if (comp_mask & (BIT(CAM_SFE_BUS_SFE_OUT_BE_1)))
 		out_list[count++] = CAM_ISP_SFE_OUT_BE_STATS_1;
 
-	if (comp_mask & (1 << CAM_SFE_BUS_SFE_OUT_BHIST_1))
+	if (comp_mask & (BIT(CAM_SFE_BUS_SFE_OUT_BHIST_1)))
 		out_list[count++] = CAM_ISP_SFE_OUT_BHIST_STATS_1;
 
-	if (comp_mask & (1 << CAM_SFE_BUS_SFE_OUT_BE_2))
+	if (comp_mask & (BIT(CAM_SFE_BUS_SFE_OUT_BE_2)))
 		out_list[count++] = CAM_ISP_SFE_OUT_BE_STATS_2;
 
-	if (comp_mask & (1 << CAM_SFE_BUS_SFE_OUT_BHIST_2))
+	if (comp_mask & (BIT(CAM_SFE_BUS_SFE_OUT_BHIST_2)))
 		out_list[count++] = CAM_ISP_SFE_OUT_BHIST_STATS_2;
 
-	if (comp_mask & (1 << CAM_SFE_BUS_SFE_OUT_LCR))
+	if (comp_mask & (BIT(CAM_SFE_BUS_SFE_OUT_LCR)))
 		out_list[count++] = CAM_ISP_SFE_OUT_RES_LCR;
 
+	if (comp_mask & (BIT(CAM_SFE_BUS_SFE_OUT_IR)))
+		out_list[count++] = CAM_ISP_SFE_OUT_RES_IR;
+
+	if (comp_mask & (BIT(CAM_SFE_BUS_SFE_OUT_BAYER_RS_0)))
+		out_list[count++] = CAM_ISP_SFE_OUT_BAYER_RS_STATS_0;
+
+	if (comp_mask & (BIT(CAM_SFE_BUS_SFE_OUT_BAYER_RS_1)))
+		out_list[count++] = CAM_ISP_SFE_OUT_BAYER_RS_STATS_1;
+
+	if (comp_mask & (BIT(CAM_SFE_BUS_SFE_OUT_BAYER_RS_2)))
+		out_list[count++] = CAM_ISP_SFE_OUT_BAYER_RS_STATS_2;
+
 	*num_out = count;
 	return 0;
 }
 
+bool cam_sfe_is_mipi_pcking_needed(
+	struct cam_sfe_bus_wr_priv *bus_priv,
+	int wm_index)
+{
+	int i;
+
+	for(i = 0; i < bus_priv->num_out; i++)
+	{
+		if (((wm_index == bus_priv->sfe_out_hw_info[i].wm_idx) &&
+			(bus_priv->sfe_out_hw_info[i].sfe_out_type ==
+				CAM_SFE_BUS_SFE_OUT_RAW_DUMP)) ||
+			((wm_index == bus_priv->sfe_out_hw_info[i].wm_idx) &&
+				(bus_priv->sfe_out_hw_info[i].sfe_out_type ==
+					CAM_SFE_BUS_SFE_OUT_IR)))
+		       return true;
+	}
+
+	return false;
+}
+
 static enum cam_sfe_bus_wr_packer_format
-	cam_sfe_bus_get_packer_fmt(uint32_t out_fmt, int wm_index)
+	cam_sfe_bus_get_packer_fmt(
+	struct cam_sfe_bus_wr_priv *bus_priv,
+	uint32_t out_fmt,
+	int wm_index)
 {
+	bool is_mipi_packing =
+		cam_sfe_is_mipi_pcking_needed(bus_priv, wm_index);
+
 	switch (out_fmt) {
 	case CAM_FORMAT_MIPI_RAW_6:
 	case CAM_FORMAT_MIPI_RAW_8:
@@ -323,22 +374,22 @@ static enum cam_sfe_bus_wr_packer_format
 	case CAM_FORMAT_PD8:
 		return PACKER_FMT_PLAIN_128;
 	case CAM_FORMAT_MIPI_RAW_10:
-		if (wm_index == 0)
+		if (is_mipi_packing)
 			return PACKER_FMT_MIPI10;
 		else
 			return PACKER_FMT_PLAIN_128;
 	case CAM_FORMAT_MIPI_RAW_12:
-		if (wm_index == 0)
+		if (is_mipi_packing)
 			return PACKER_FMT_MIPI12;
 		else
 			return PACKER_FMT_PLAIN_128;
 	case CAM_FORMAT_MIPI_RAW_14:
-		if (wm_index == 0)
+		if (is_mipi_packing)
 			return PACKER_FMT_MIPI14;
 		else
 			return PACKER_FMT_PLAIN_128;
 	case CAM_FORMAT_MIPI_RAW_20:
-		if (wm_index == 0)
+		if (is_mipi_packing)
 			return PACKER_FMT_MIPI20;
 		else
 			return PACKER_FMT_PLAIN_128;
@@ -604,8 +655,8 @@ static int cam_sfe_bus_acquire_wm(
 	rsrc_data = wm_res->res_priv;
 	wm_idx = rsrc_data->index;
 	rsrc_data->format = out_port_info->format;
-	rsrc_data->pack_fmt = cam_sfe_bus_get_packer_fmt(rsrc_data->format,
-		wm_idx);
+	rsrc_data->pack_fmt = cam_sfe_bus_get_packer_fmt(bus_priv,
+		rsrc_data->format, wm_idx);
 
 	rsrc_data->width = out_port_info->width;
 	rsrc_data->height = out_port_info->height;
@@ -647,8 +698,22 @@ static int cam_sfe_bus_acquire_wm(
 		default:
 			break;
 		}
+	} else if (sfe_out_res_id == CAM_SFE_BUS_SFE_OUT_IR) {
+		rsrc_data->stride = rsrc_data->width;
+		rsrc_data->en_cfg = 0x1;
+		switch (rsrc_data->format) {
+		case CAM_FORMAT_PLAIN16_10:
+		case CAM_FORMAT_PLAIN16_12:
+		case CAM_FORMAT_PLAIN16_14:
+		case CAM_FORMAT_PLAIN16_16:
+			/* LSB aligned */
+			rsrc_data->pack_fmt |= 0x20;
+			break;
+		default:
+			break;
+		}
 	} else if ((sfe_out_res_id >= CAM_SFE_BUS_SFE_OUT_BE_0) &&
-		(sfe_out_res_id <= CAM_SFE_BUS_SFE_OUT_BHIST_2)) {
+		(sfe_out_res_id <= CAM_SFE_BUS_SFE_OUT_BAYER_RS_2)) {
 		rsrc_data->width = 0;
 		rsrc_data->height = 0;
 		rsrc_data->stride = 1;
@@ -3001,6 +3066,7 @@ int cam_sfe_bus_wr_init(
 	bus_priv->common_data.sfe_irq_controller   = sfe_irq_controller;
 	bus_priv->num_cons_err = hw_info->num_cons_err;
 	bus_priv->constraint_error_list = hw_info->constraint_error_list;
+	bus_priv->sfe_out_hw_info = hw_info->sfe_out_hw_info;
 	rc = cam_cpas_get_cpas_hw_version(&bus_priv->common_data.hw_version);
 	if (rc) {
 		CAM_ERR(CAM_SFE, "Failed to get hw_version rc:%d", rc);

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_wr.h

@@ -9,7 +9,7 @@
 
 #include "cam_sfe_bus.h"
 
-#define CAM_SFE_BUS_WR_MAX_CLIENTS     13
+#define CAM_SFE_BUS_WR_MAX_CLIENTS     16
 #define CAM_SFE_BUS_WR_MAX_SUB_GRPS    6
 #define CAM_SFE_BUS_CONS_ERR_MAX       32
 
@@ -51,6 +51,10 @@ enum cam_sfe_bus_sfe_out_type {
 	CAM_SFE_BUS_SFE_OUT_BHIST_1,
 	CAM_SFE_BUS_SFE_OUT_BE_2,
 	CAM_SFE_BUS_SFE_OUT_BHIST_2,
+	CAM_SFE_BUS_SFE_OUT_BAYER_RS_0,
+	CAM_SFE_BUS_SFE_OUT_BAYER_RS_1,
+	CAM_SFE_BUS_SFE_OUT_BAYER_RS_2,
+	CAM_SFE_BUS_SFE_OUT_IR,
 	CAM_SFE_BUS_SFE_OUT_MAX,
 };
 
@@ -107,6 +111,7 @@ struct cam_sfe_bus_reg_offset_bus_client {
 	uint32_t framedrop_period;
 	uint32_t framedrop_pattern;
 	uint32_t system_cache_cfg;
+	uint32_t addr_cfg;
 	uint32_t addr_status_0;
 	uint32_t addr_status_1;
 	uint32_t addr_status_2;

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_top/cam_sfe_top.c

@@ -56,8 +56,10 @@ struct cam_sfe_top_priv {
 	void                           *priv_per_stream;
 	spinlock_t                      spin_lock;
 	cam_hw_mgr_event_cb_func        event_cb;
-	struct cam_sfe_top_module_desc *module_desc;
 	struct cam_sfe_wr_client_desc  *wr_client_desc;
+	struct cam_sfe_top_hw_info     *hw_info;
+	uint32_t                        num_clc_module;
+	struct cam_sfe_top_debug_info  (*clc_dbg_mod_info)[CAM_SFE_TOP_DBG_REG_MAX][8];
 };
 
 struct cam_sfe_path_data {
@@ -73,320 +75,6 @@ struct cam_sfe_path_data {
 	int                                       sof_eof_handle;
 };
 
-struct cam_sfe_top_debug_info {
-	uint32_t  shift;
-	char     *clc_name;
-};
-
-static const struct cam_sfe_top_debug_info sfe_dbg_list[][8] = {
-	{
-		{
-			.shift = 0,
-			.clc_name = "test_bus_reserved"
-		},
-		{
-			.shift = 4,
-			.clc_name = "test_bus_reserved"
-		},
-		{
-			.shift = 8,
-			.clc_name = "test_bus_reserved"
-		},
-		{
-			.shift = 12,
-			.clc_name = "test_bus_reserved"
-		},
-		{
-			.shift = 16,
-			.clc_name = "test_bus_reserved"
-		},
-		{
-			.shift = 20,
-			.clc_name = "test_bus_reserved"
-		},
-		{
-			.shift = 24,
-			.clc_name = "test_bus_reserved"
-		},
-		{
-			.shift = 28,
-			.clc_name = "test_bus_reserved"
-		},
-	},
-	{
-		{
-			.shift = 0,
-			.clc_name = "zsl_throttle"
-		},
-		{
-			.shift = 4,
-			.clc_name = "crc_zsl"
-		},
-		{
-			.shift = 8,
-			.clc_name = "comp_zsl"
-		},
-		{
-			.shift = 12,
-			.clc_name = "crc_prev"
-		},
-		{
-			.shift = 16,
-			.clc_name = "hdrc_ch2"
-		},
-		{
-			.shift = 20,
-			.clc_name = "hdrc_ch1"
-		},
-		{
-			.shift = 24,
-			.clc_name = "hdrc_ch0"
-		},
-		{
-			.shift = 28,
-			.clc_name = "stats_bhist_ch0"
-		},
-	},
-	{
-		{
-			.shift = 0,
-			.clc_name = "stats_bg_ch0"
-		},
-		{
-			.shift = 4,
-			.clc_name = "lsc_ch0"
-		},
-		{
-			.shift = 8,
-			.clc_name = "crc_ch0"
-		},
-		{
-			.shift = 12,
-			.clc_name = "ccif_2x2_to_2x1"
-		},
-		{
-			.shift = 16,
-			.clc_name = "decomp"
-		},
-		{
-			.shift = 20,
-			.clc_name = "msb_align_ch0"
-		},
-		{
-			.shift = 24,
-			.clc_name = "bpc_pdpc"
-		},
-		{
-			.shift = 28,
-			.clc_name = "ch0_gain"
-		},
-	},
-	{
-		{
-			.shift = 0,
-			.clc_name = "bhist_ch1"
-		},
-		{
-			.shift = 4,
-			.clc_name = "stats_bg_ch1"
-		},
-		{
-			.shift = 8,
-			.clc_name = "lsc_ch1"
-		},
-		{
-			.shift = 12,
-			.clc_name = "crc_ch1"
-		},
-		{
-			.shift = 16,
-			.clc_name = "msb_align_ch1"
-		},
-		{
-			.shift = 20,
-			.clc_name = "ch1_gain"
-		},
-		{
-			.shift = 24,
-			.clc_name = "bhist_ch2"
-		},
-		{
-			.shift = 28,
-			.clc_name = "stats_bg_ch2"
-		},
-	},
-	{
-		{
-			.shift = 0,
-			.clc_name = "lsc_ch2"
-		},
-		{
-			.shift = 4,
-			.clc_name = "crc_ch2"
-		},
-		{
-			.shift = 8,
-			.clc_name = "msb_align_ch2"
-		},
-		{
-			.shift = 12,
-			.clc_name = "ch2_gain"
-		},
-		{
-			.shift = 16,
-			.clc_name = "lcr_throttle"
-		},
-		{
-			.shift = 20,
-			.clc_name = "lcr"
-		},
-		{
-			.shift = 24,
-			.clc_name = "demux_fetch2"
-		},
-		{
-			.shift = 28,
-			.clc_name = "demux_fetch1"
-		},
-	},
-	{
-		{
-			.shift = 0,
-			.clc_name = "demux_fetch0"
-		},
-		{
-			.shift = 4,
-			.clc_name = "csid_ccif"
-		},
-		{
-			.shift = 8,
-			.clc_name = "RDI4"
-		},
-		{
-			.shift = 12,
-			.clc_name = "RDI3"
-		},
-		{
-			.shift = 16,
-			.clc_name = "RDI2"
-		},
-		{
-			.shift = 20,
-			.clc_name = "RDI1"
-		},
-		{
-			.shift = 24,
-			.clc_name = "RDI0"
-		},
-		{
-			.shift = 28,
-			.clc_name = "bhist2_bus_wr"
-		},
-	},
-	{
-		{
-			.shift = 0,
-			.clc_name = "bg2_bus_wr"
-		},
-		{
-			.shift = 4,
-			.clc_name = "bhist1_bus_wr"
-		},
-		{
-			.shift = 8,
-			.clc_name = "bg1_bus_wr"
-		},
-		{
-			.shift = 12,
-			.clc_name = "bhist0_bus_wr"
-		},
-		{
-			.shift = 16,
-			.clc_name = "bg0_bus_wr"
-		},
-		{
-			.shift = 20,
-			.clc_name = "lcr_bus_wr"
-		},
-		{
-			.shift = 24,
-			.clc_name = "zsl_bus_wr"
-		},
-		{
-			.shift = 28,
-			.clc_name = "sfe_op_throttle"
-		},
-	},
-	{
-		{
-			.shift = 0,
-			.clc_name = "line_smooth"
-		},
-		{
-			.shift = 4,
-			.clc_name = "pp"
-		},
-		{
-			.shift = 8,
-			.clc_name = "bus_conv_ch2"
-		},
-		{
-			.shift = 12,
-			.clc_name = "bus_conv_ch1"
-		},
-		{
-			.shift = 16,
-			.clc_name = "bus_conv_ch0"
-		},
-		{
-			.shift = 20,
-			.clc_name = "fe_ch2"
-		},
-		{
-			.shift = 24,
-			.clc_name = "fe_ch1"
-		},
-		{
-			.shift = 28,
-			.clc_name = "fe_ch0"
-		},
-	},
-	{
-		{
-			.shift = 0,
-			.clc_name = "rdi4"
-		},
-		{
-			.shift = 4,
-			.clc_name = "rdi3"
-		},
-		{
-			.shift = 8,
-			.clc_name = "rdi2"
-		},
-		{
-			.shift = 12,
-			.clc_name = "rdi1"
-		},
-		{
-			.shift = 16,
-			.clc_name = "rdi0"
-		},
-		{
-			.shift = 20,
-			.clc_name = "pixel"
-		},
-		{
-			.shift = 24,
-			.clc_name = "reserved"
-		},
-		{
-			.shift = 28,
-			.clc_name = "reserved"
-		},
-	},
-};
-
 static int cam_sfe_top_apply_clock_start_stop(struct cam_sfe_top_priv *top_priv);
 
 static int cam_sfe_top_apply_bw_start_stop(struct cam_sfe_top_priv *top_priv);
@@ -480,7 +168,7 @@ end:
 
 static void cam_sfe_top_check_module_status(
 	uint32_t num_reg, uint32_t *reg_val,
-	const struct cam_sfe_top_debug_info status_list[][8])
+	struct cam_sfe_top_debug_info (*status_list)[CAM_SFE_TOP_DBG_REG_MAX][8])
 {
 	bool found = false;
 	uint32_t i, j, val = 0;
@@ -496,13 +184,13 @@ static void cam_sfe_top_check_module_status(
 			continue;
 
 		for (j = 0; j < 8; j++) {
-			val = reg_val[i] >> status_list[i][j].shift;
+			val = reg_val[i] >> (*status_list)[i][j].shift;
 			val &= 0xF;
 			if (val == 0 || val == 5)
 				continue;
 
 			CAM_INFO_BUF(CAM_SFE, log_buf, 1024, &len, "%s [I:%u V:%u R:%u]",
-				status_list[i][j].clc_name,
+				(*status_list)[i][j].clc_name,
 				((val >> 2) & 1), ((val >> 1) & 1), (val & 1));
 			found = true;
 		}
@@ -522,11 +210,12 @@ static void cam_sfe_top_print_debug_reg_info(
 	struct cam_sfe_top_common_data  *common_data;
 	struct cam_hw_soc_info          *soc_info;
 	uint32_t                        *reg_val = NULL;
-	uint32_t num_reg = CAM_SFE_TOP_DBG_REG_MAX;
+	uint32_t num_reg = 0;
 	int i = 0, j;
 
 	common_data = &top_priv->common_data;
 	soc_info = common_data->soc_info;
+	num_reg = common_data->common_reg->num_debug_registers;
 	mem_base = soc_info->reg_map[SFE_CORE_BASE_IDX].mem_base;
 	reg_val    = kcalloc(num_reg, sizeof(uint32_t), GFP_KERNEL);
 	if (!reg_val)
@@ -542,8 +231,8 @@ static void cam_sfe_top_print_debug_reg_info(
 			(i - 2), reg_val[i - 2], (i - 1), reg_val[i - 1]);
 	}
 
-	cam_sfe_top_check_module_status(num_reg,
-		reg_val, sfe_dbg_list);
+	cam_sfe_top_check_module_status(top_priv->num_clc_module,
+		reg_val, top_priv->clc_dbg_mod_info);
 
 	kfree(reg_val);
 }
@@ -1483,8 +1172,8 @@ static int cam_sfe_top_handle_err_irq_top_half(
 
 	cam_isp_hw_get_timestamp(&evt_payload->ts);
 	evt_payload->violation_status =
-		cam_io_r(base +
-		top_priv->common_data.common_reg->violation_status);
+	cam_io_r(base +
+		top_priv->common_data.common_reg->ipp_violation_status);
 
 	th_payload->evt_payload_priv = evt_payload;
 
@@ -1580,6 +1269,45 @@ void cam_sfe_top_sel_frame_counter(
 	}
 }
 
+static void cam_sfe_top_print_ipp_violation_info(
+	struct cam_sfe_top_priv *top_priv,
+	uint32_t violation_status)
+{
+	struct cam_sfe_top_common_data *common_data = &top_priv->common_data;
+	struct cam_hw_soc_info         *soc_info = common_data->soc_info;
+	uint32_t val = violation_status;
+
+	CAM_INFO(CAM_SFE, "SFE[%u] IPP Violation status 0x%x",
+	     soc_info->index, val);
+
+	if (top_priv->hw_info->ipp_module_desc)
+		CAM_ERR(CAM_SFE, "SFE[%u] IPP Violation Module id: [%u %s]",
+			soc_info->index,
+			top_priv->hw_info->ipp_module_desc[val].id,
+			top_priv->hw_info->ipp_module_desc[val].desc);
+
+}
+
+static void cam_sfe_top_print_top_irq_error(
+	struct cam_sfe_top_priv *top_priv,
+	uint32_t irq_status,
+	uint32_t violation_status)
+{
+	uint32_t i = 0;
+
+	for (i = 0; i < top_priv->hw_info->num_top_errors; i++) {
+		if (top_priv->hw_info->top_err_desc[i].bitmask &
+			irq_status) {
+			CAM_ERR(CAM_SFE, "%s %s",
+				top_priv->hw_info->top_err_desc[i].err_name,
+				top_priv->hw_info->top_err_desc[i].desc);
+		}
+	}
+
+	if (irq_status & top_priv->common_data.common_reg->ipp_violation_mask)
+		cam_sfe_top_print_ipp_violation_info(top_priv, violation_status);
+
+}
 
 static int cam_sfe_top_handle_err_irq_bottom_half(
 	void *handler_priv, void *evt_payload_priv)
@@ -1602,24 +1330,11 @@ static int cam_sfe_top_handle_err_irq_bottom_half(
 
 	if (irq_status[0] &
 		top_priv->common_data.common_reg_data->error_irq_mask) {
-		if (irq_status[0] & 0x4000)
-			CAM_ERR(CAM_SFE, "PP VIOLATION");
-
-		if (irq_status[0] & 0x8000)
-			CAM_ERR(CAM_SFE, "DIAG VIOLATION");
-
-		if (irq_status[0] & 0x10000)
-			CAM_ERR(CAM_SFE, "LINE SMOOTH VIOLATION");
-
 		viol_sts = payload->violation_status;
 		CAM_INFO(CAM_SFE, "Violation status 0x%x",
 			viol_sts);
-		if (top_priv->module_desc)
-			CAM_ERR(CAM_ISP, "SFE:%u Violating Module [ID: %d name: %s]",
-				evt_info.hw_idx,
-				top_priv->module_desc[viol_sts].id,
-				top_priv->module_desc[viol_sts].desc);
-
+		cam_sfe_top_print_top_irq_error(top_priv,
+			irq_status[0], viol_sts);
 		evt_info.err_type = CAM_SFE_IRQ_STATUS_VIOLATION;
 		cam_sfe_top_print_debug_reg_info(top_priv);
 		if (top_priv->event_cb)
@@ -1705,6 +1420,7 @@ int cam_sfe_top_start(
 	struct cam_sfe_soc_private           *soc_private = NULL;
 	uint32_t   error_mask[CAM_SFE_IRQ_REGISTERS_MAX];
 	uint32_t   sof_eof_mask[CAM_SFE_IRQ_REGISTERS_MAX];
+	uint32_t core_cfg = 0, i = 0;
 
 	if (!priv || !start_args) {
 		CAM_ERR(CAM_SFE, "Invalid args");
@@ -1744,11 +1460,22 @@ int cam_sfe_top_start(
 		return rc;
 	}
 
+	core_cfg = cam_io_r_mb(path_data->mem_base +
+			path_data->common_reg->core_cfg);
+
 	/* core cfg updated via CDM */
 	CAM_DBG(CAM_SFE, "SFE HW [%u] core_cfg: 0x%x",
-		hw_info->soc_info.index,
-		cam_io_r_mb(path_data->mem_base +
-			path_data->common_reg->core_cfg));
+		hw_info->soc_info.index, core_cfg);
+
+	for (i = 0; i < path_data->common_reg->num_sfe_mode; i++) {
+		if (path_data->common_reg->sfe_mode[i].value ==
+			core_cfg) {
+			CAM_DBG(CAM_SFE, "SFE HW [%u] : [%s]",
+				hw_info->soc_info.index,
+				path_data->common_reg->sfe_mode[i].desc);
+			break;
+		}
+	}
 
 	/* Enable debug cfg registers */
 	cam_io_w(path_data->common_reg_data->top_debug_cfg_en,
@@ -2055,10 +1782,10 @@ int cam_sfe_top_init(
 	top_priv->common_data.hw_intf = hw_intf;
 	top_priv->common_data.common_reg =
 		sfe_top_hw_info->common_reg;
-	top_priv->common_data.common_reg_data =
-		sfe_top_hw_info->common_reg_data;
-	top_priv->module_desc = sfe_top_hw_info->module_desc;
-	top_priv->wr_client_desc = sfe_top_hw_info->wr_client_desc;
+	top_priv->hw_info = sfe_top_hw_info;
+	top_priv->wr_client_desc  = sfe_top_hw_info->wr_client_desc;
+	top_priv->num_clc_module   = sfe_top_hw_info->num_clc_module;
+	top_priv->clc_dbg_mod_info = sfe_top_hw_info->clc_dbg_mod_info;
 	top_priv->sfe_debug_cfg = 0;
 
 	sfe_top->hw_ops.process_cmd = cam_sfe_top_process_cmd;

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_top/cam_sfe_top.h

@@ -19,7 +19,7 @@
 #define CAM_SHIFT_TOP_CORE_CFG_OPS_MODE_CFG    1
 #define CAM_SHIFT_TOP_CORE_CFG_FS_MODE_CFG     0
 
-#define CAM_SFE_TOP_DBG_REG_MAX                12
+#define CAM_SFE_TOP_DBG_REG_MAX                18
 
 struct cam_sfe_top_module_desc {
 	uint32_t id;
@@ -31,11 +31,28 @@ struct cam_sfe_top {
 	struct cam_hw_ops       hw_ops;
 };
 
+struct cam_sfe_mode {
+	int  value;
+	char  *desc;
+};
+
 struct cam_sfe_wr_client_desc {
 	uint32_t  wm_id;
 	uint8_t  *desc;
 };
 
+struct cam_sfe_top_err_irq_desc {
+	uint32_t  bitmask;
+	char     *err_name;
+	char     *desc;
+};
+
+struct cam_sfe_top_debug_info {
+	uint32_t  shift;
+	char     *clc_name;
+};
+
+
 struct cam_sfe_top_common_reg_offset {
 	uint32_t hw_version;
 	uint32_t hw_capability;
@@ -43,7 +60,7 @@ struct cam_sfe_top_common_reg_offset {
 	uint32_t core_cgc_ctrl;
 	uint32_t ahb_clk_ovd;
 	uint32_t core_cfg;
-	uint32_t violation_status;
+	uint32_t ipp_violation_status;
 	uint32_t diag_config;
 	uint32_t diag_sensor_status_0;
 	uint32_t diag_sensor_status_1;
@@ -55,19 +72,28 @@ struct cam_sfe_top_common_reg_offset {
 	uint32_t lcr_throttle_cfg;
 	uint32_t hdr_throttle_cfg;
 	uint32_t sfe_op_throttle_cfg;
+	uint32_t irc_throttle_cfg;
+	uint32_t sfe_single_dual_cfg;
 	uint32_t bus_overflow_status;
 	uint32_t top_debug_cfg;
+	bool     lcr_supported;
+	bool     ir_supported;
+	bool     qcfa_only;
+	struct   cam_sfe_mode *sfe_mode;
+	uint32_t num_sfe_mode;
+	uint32_t ipp_violation_mask;
+	uint32_t num_debug_registers;
 	uint32_t top_debug[CAM_SFE_TOP_DBG_REG_MAX];
 };
 
 struct cam_sfe_modules_common_reg_offset {
 	uint32_t demux_module_cfg;
-	uint32_t demux_qcfa_cfg;
+	uint32_t demux_xcfa_cfg;
 	uint32_t demux_hdr_cfg;
 	uint32_t demux_lcr_sel;
 	uint32_t hdrc_remo_mod_cfg;
-	uint32_t hdrc_remo_qcfa_bin_cfg;
-	uint32_t qcfa_hdrc_remo_out_mux_cfg;
+	uint32_t hdrc_remo_xcfa_bin_cfg;
+	uint32_t xcfa_hdrc_remo_out_mux_cfg;
 };
 
 struct cam_sfe_top_common_reg_data {
@@ -87,13 +113,17 @@ struct cam_sfe_top_hw_info {
 	struct cam_sfe_top_common_reg_offset     *common_reg;
 	struct cam_sfe_modules_common_reg_offset *modules_hw_info;
 	struct cam_sfe_top_common_reg_data       *common_reg_data;
-	struct cam_sfe_top_module_desc           *module_desc;
+	struct cam_sfe_top_module_desc           *ipp_module_desc;
 	struct cam_sfe_wr_client_desc            *wr_client_desc;
 	struct cam_sfe_path_common_reg_data      *pix_reg_data;
 	struct cam_sfe_path_common_reg_data      *rdi_reg_data[CAM_SFE_RDI_MAX];
 	uint32_t                                  num_inputs;
 	uint32_t                                  input_type[
 		CAM_SFE_TOP_IN_PORT_MAX];
+	uint32_t                                  num_top_errors;
+	struct cam_sfe_top_err_irq_desc          *top_err_desc;
+	uint32_t                                  num_clc_module;
+	struct   cam_sfe_top_debug_info         (*clc_dbg_mod_info)[CAM_SFE_TOP_DBG_REG_MAX][8];
 };
 
 int cam_sfe_top_init(
@@ -108,4 +138,18 @@ int cam_sfe_top_deinit(
 	uint32_t                       hw_version,
 	struct cam_sfe_top           **sfe_top);
 
+#define SFE_DBG_INFO(shift_val, name) {.shift = shift_val, .clc_name = name}
+
+#define SFE_DBG_INFO_ARRAY_4bit(name1, name2, name3, name4, name5, name6, name7, name8) \
+	{                                                                               \
+		SFE_DBG_INFO(0, name1),                                                 \
+		SFE_DBG_INFO(4, name2),                                                 \
+		SFE_DBG_INFO(8, name3),                                                 \
+		SFE_DBG_INFO(12, name4),                                                \
+		SFE_DBG_INFO(16, name5),                                                \
+		SFE_DBG_INFO(20, name6),                                                \
+		SFE_DBG_INFO(24, name7),                                                \
+		SFE_DBG_INFO(28, name8),                                                \
+	}
+
 #endif /* _CAM_SFE_TOP_H_ */

include/uapi/camera/media/cam_isp_sfe.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
 /*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef __UAPI_CAM_ISP_SFE_H__
@@ -22,8 +22,12 @@
 #define CAM_ISP_SFE_OUT_BHIST_STATS_2         (CAM_ISP_SFE_OUT_RES_BASE + 10)
 #define CAM_ISP_SFE_OUT_RES_LCR               (CAM_ISP_SFE_OUT_RES_BASE + 11)
 #define CAM_ISP_SFE_OUT_RES_RAW_DUMP          (CAM_ISP_SFE_OUT_RES_BASE + 12)
+#define CAM_ISP_SFE_OUT_RES_IR                (CAM_ISP_SFE_OUT_RES_BASE + 13)
+#define CAM_ISP_SFE_OUT_BAYER_RS_STATS_0      (CAM_ISP_SFE_OUT_RES_BASE + 14)
+#define CAM_ISP_SFE_OUT_BAYER_RS_STATS_1      (CAM_ISP_SFE_OUT_RES_BASE + 15)
+#define CAM_ISP_SFE_OUT_BAYER_RS_STATS_2      (CAM_ISP_SFE_OUT_RES_BASE + 16)
 
-#define CAM_ISP_SFE_OUT_RES_MAX               (CAM_ISP_SFE_OUT_RES_BASE + 13)
+#define CAM_ISP_SFE_OUT_RES_MAX               (CAM_ISP_SFE_OUT_RES_BASE + 17)
 
 /* SFE input port resource type */
 #define CAM_ISP_SFE_IN_RES_BASE               0x5000