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@@ -18,7 +18,7 @@
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///////////////////////////////////////////////////////////////////////////////////////////////
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//
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-// wcss_seq_hwiobase.h : automatically generated by Autoseq 3.1 9/30/2016
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+// wcss_seq_hwiobase.h : automatically generated by Autoseq 3.1 10/27/2016
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// User Name:kanalas
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//
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// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
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@@ -42,6 +42,11 @@
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#define SEQ_WCSS_ECAHB_OFFSET 0x00008400
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#define SEQ_WCSS_ECAHB_TSLV_OFFSET 0x00009000
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#define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000
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+#define SEQ_WCSS_MPSS_OFFSET 0x00200000
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+#define SEQ_WCSS_MPSS_SEG0PDMEM_WFAX_PCSS_PDMEM_OFFSET 0x00200000
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+#define SEQ_WCSS_MPSS_SEG0_WFAX_PCSS_OFFSET 0x00280000
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+#define SEQ_WCSS_MPSS_SEG0_WFAX_PCSS_DUAL_TIMER_OFFSET 0x00281800
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+#define SEQ_WCSS_MPSS_SEG0_WFAX_PCSS_WATCHDOG_OFFSET 0x00281c00
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#define SEQ_WCSS_PHYA_OFFSET 0x00400000
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#define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00400000
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#define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET 0x00480000
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@@ -230,26 +235,26 @@
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#define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000
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#define SEQ_WCSS_WMAC0_MAC_RXDMA1_REG_OFFSET 0x00ab6000
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#define SEQ_WCSS_WMAC0_MAC_LPEC_REG_OFFSET 0x00ab9000
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-#define SEQ_WCSS_WMAC1_OFFSET 0x00ac0000
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-#define SEQ_WCSS_WMAC1_MAC_PDG_REG_OFFSET 0x00ac0000
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-#define SEQ_WCSS_WMAC1_MAC_TXDMA_REG_OFFSET 0x00ac3000
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-#define SEQ_WCSS_WMAC1_MAC_RXDMA_REG_OFFSET 0x00ac6000
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-#define SEQ_WCSS_WMAC1_MAC_MCMN_REG_OFFSET 0x00ac9000
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-#define SEQ_WCSS_WMAC1_MAC_RXPCU_REG_OFFSET 0x00acc000
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-#define SEQ_WCSS_WMAC1_MAC_TXPCU_REG_OFFSET 0x00acf000
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-#define SEQ_WCSS_WMAC1_MAC_AMPI_REG_OFFSET 0x00ad2000
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-#define SEQ_WCSS_WMAC1_MAC_RXOLE_REG_OFFSET 0x00ad5000
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-#define SEQ_WCSS_WMAC1_MAC_RXOLE_PARSER_REG_OFFSET 0x00ad8000
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-#define SEQ_WCSS_WMAC1_MAC_CCE_REG_OFFSET 0x00adb000
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-#define SEQ_WCSS_WMAC1_MAC_TXOLE_REG_OFFSET 0x00ade000
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-#define SEQ_WCSS_WMAC1_MAC_TXOLE_PARSER_REG_OFFSET 0x00ae1000
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-#define SEQ_WCSS_WMAC1_MAC_RRI_REG_OFFSET 0x00ae4000
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-#define SEQ_WCSS_WMAC1_MAC_CRYPTO_REG_OFFSET 0x00ae7000
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-#define SEQ_WCSS_WMAC1_MAC_HWSCH_REG_OFFSET 0x00aea000
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-#define SEQ_WCSS_WMAC1_MAC_MXI_REG_OFFSET 0x00af0000
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-#define SEQ_WCSS_WMAC1_MAC_SFM_REG_OFFSET 0x00af3000
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-#define SEQ_WCSS_WMAC1_MAC_RXDMA1_REG_OFFSET 0x00af6000
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-#define SEQ_WCSS_WMAC1_MAC_LPEC_REG_OFFSET 0x00af9000
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+#define SEQ_WCSS_WMAC1_OFFSET 0x00b00000
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+#define SEQ_WCSS_WMAC1_MAC_PDG_REG_OFFSET 0x00b00000
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+#define SEQ_WCSS_WMAC1_MAC_TXDMA_REG_OFFSET 0x00b03000
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+#define SEQ_WCSS_WMAC1_MAC_RXDMA_REG_OFFSET 0x00b06000
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+#define SEQ_WCSS_WMAC1_MAC_MCMN_REG_OFFSET 0x00b09000
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+#define SEQ_WCSS_WMAC1_MAC_RXPCU_REG_OFFSET 0x00b0c000
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+#define SEQ_WCSS_WMAC1_MAC_TXPCU_REG_OFFSET 0x00b0f000
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+#define SEQ_WCSS_WMAC1_MAC_AMPI_REG_OFFSET 0x00b12000
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+#define SEQ_WCSS_WMAC1_MAC_RXOLE_REG_OFFSET 0x00b15000
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+#define SEQ_WCSS_WMAC1_MAC_RXOLE_PARSER_REG_OFFSET 0x00b18000
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+#define SEQ_WCSS_WMAC1_MAC_CCE_REG_OFFSET 0x00b1b000
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+#define SEQ_WCSS_WMAC1_MAC_TXOLE_REG_OFFSET 0x00b1e000
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+#define SEQ_WCSS_WMAC1_MAC_TXOLE_PARSER_REG_OFFSET 0x00b21000
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+#define SEQ_WCSS_WMAC1_MAC_RRI_REG_OFFSET 0x00b24000
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+#define SEQ_WCSS_WMAC1_MAC_CRYPTO_REG_OFFSET 0x00b27000
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+#define SEQ_WCSS_WMAC1_MAC_HWSCH_REG_OFFSET 0x00b2a000
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+#define SEQ_WCSS_WMAC1_MAC_MXI_REG_OFFSET 0x00b30000
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+#define SEQ_WCSS_WMAC1_MAC_SFM_REG_OFFSET 0x00b33000
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+#define SEQ_WCSS_WMAC1_MAC_RXDMA1_REG_OFFSET 0x00b36000
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+#define SEQ_WCSS_WMAC1_MAC_LPEC_REG_OFFSET 0x00b39000
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#define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000
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#define SEQ_WCSS_WCMN_OFFSET 0x00b50000
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#define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000
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@@ -274,12 +279,12 @@
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#define SEQ_WCSS_DBG_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bb0000
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#define SEQ_WCSS_DBG_PHYA_CTI_QC_CTI_8T_8CH_OFFSET 0x00bb1000
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#define SEQ_WCSS_DBG_PHYA_NOC_PHYA_NOC_OFFSET 0x00bb6000
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-#define SEQ_WCSS_DBG_PHYA_CPU0_AHB_AP_OFFSET 0x00bbe000
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+#define SEQ_WCSS_DBG_PHYA_CPU0_M3_AHB_AP_OFFSET 0x00bbe000
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#define SEQ_WCSS_DBG_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc0000
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#define SEQ_WCSS_DBG_PHYB_CTI_QC_CTI_8T_8CH_OFFSET 0x00bc1000
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#define SEQ_WCSS_DBG_PHYB_NOC_PHYB_NOC_OFFSET 0x00bc6000
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-#define SEQ_WCSS_DBG_PHYB_CPU0_AHB_AP_OFFSET 0x00bce000
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-#define SEQ_WCSS_DBG_UMAC_CPU_AHB_AP_OFFSET 0x00bf0000
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+#define SEQ_WCSS_DBG_PHYB_CPU0_M3_AHB_AP_OFFSET 0x00bce000
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+#define SEQ_WCSS_DBG_UMAC_CPU_M3_AHB_AP_OFFSET 0x00bf0000
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#define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00bf1000
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#define SEQ_WCSS_RET_AHB_OFFSET 0x00c10000
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#define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00c20000
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@@ -297,6 +302,16 @@
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#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_OFFSET 0x00db0000
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+///////////////////////////////////////////////////////////////////////////////////////////////
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+// Instance Relative Offsets from Block mpss_top
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+///////////////////////////////////////////////////////////////////////////////////////////////
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+
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+#define SEQ_MPSS_TOP_SEG0PDMEM_WFAX_PCSS_PDMEM_OFFSET 0x00000000
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+#define SEQ_MPSS_TOP_SEG0_WFAX_PCSS_OFFSET 0x00080000
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+#define SEQ_MPSS_TOP_SEG0_WFAX_PCSS_DUAL_TIMER_OFFSET 0x00081800
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+#define SEQ_MPSS_TOP_SEG0_WFAX_PCSS_WATCHDOG_OFFSET 0x00081c00
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+
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+
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///////////////////////////////////////////////////////////////////////////////////////////////
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// Instance Relative Offsets from Block wfax_top
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///////////////////////////////////////////////////////////////////////////////////////////////
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@@ -661,6 +676,7 @@
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#define SEQ_WMAC_TOP_REG_28LP_MAC_SFM_REG_OFFSET 0x00033000
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#define SEQ_WMAC_TOP_REG_28LP_MAC_RXDMA1_REG_OFFSET 0x00036000
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#define SEQ_WMAC_TOP_REG_28LP_MAC_LPEC_REG_OFFSET 0x00039000
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+
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#define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_PDG_REG_OFFSET
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#define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_TXDMA_REG_OFFSET
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#define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_RXDMA_REG_OFFSET
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@@ -681,7 +697,6 @@
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#define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_RXDMA1_REG_OFFSET
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#define SEQ_WMAC_TOP_REG_MAC_LPEC_REG_OFFSET SEQ_WMAC_TOP_REG_28LP_MAC_LPEC_REG_OFFSET
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-
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///////////////////////////////////////////////////////////////////////////////////////////////
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// Instance Relative Offsets from Block wcssdbg_napier
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///////////////////////////////////////////////////////////////////////////////////////////////
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@@ -705,12 +720,12 @@
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#define SEQ_WCSSDBG_NAPIER_PHYA_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00020000
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#define SEQ_WCSSDBG_NAPIER_PHYA_CTI_QC_CTI_8T_8CH_OFFSET 0x00021000
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#define SEQ_WCSSDBG_NAPIER_PHYA_NOC_PHYA_NOC_OFFSET 0x00026000
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-#define SEQ_WCSSDBG_NAPIER_PHYA_CPU0_AHB_AP_OFFSET 0x0002e000
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+#define SEQ_WCSSDBG_NAPIER_PHYA_CPU0_M3_AHB_AP_OFFSET 0x0002e000
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#define SEQ_WCSSDBG_NAPIER_PHYB_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00030000
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#define SEQ_WCSSDBG_NAPIER_PHYB_CTI_QC_CTI_8T_8CH_OFFSET 0x00031000
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#define SEQ_WCSSDBG_NAPIER_PHYB_NOC_PHYB_NOC_OFFSET 0x00036000
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-#define SEQ_WCSSDBG_NAPIER_PHYB_CPU0_AHB_AP_OFFSET 0x0003e000
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-#define SEQ_WCSSDBG_NAPIER_UMAC_CPU_AHB_AP_OFFSET 0x00060000
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+#define SEQ_WCSSDBG_NAPIER_PHYB_CPU0_M3_AHB_AP_OFFSET 0x0003e000
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+#define SEQ_WCSSDBG_NAPIER_UMAC_CPU_M3_AHB_AP_OFFSET 0x00060000
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#define SEQ_WCSSDBG_NAPIER_BUS_TIMEOUT_OFFSET 0x00061000
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