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Merge changes I15de8298,I71675c8f,Ifcf6d6f1,I766f1569 into display-kernel.lnx.1.0

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* changes:
  disp: msm: rotator: migrated the new BUS driver for rotator on lahaina
  disp: msm: dsi: remove dsi bus scaling setting
  disp: msm: sde: migrated new sde icb bus scaling driver for lahaina
  display: add uapi and shared headers to techpack folder
This commit is contained in:
Linux Build Service Account
2019-12-04 17:26:51 -08:00
committed by Gerrit - the friendly Code Review server
parent 16a8f25de1 f3553ab628
commit 5706918517
29 changed files with 2205 additions and 533 deletions
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# Top-level Makefile calls into asm-$(ARCH)
# List only non-arch directories below

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# SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note
header-y += sde_io_util.h
header-y += sde_rsc.h

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2012, 2017-2019, The Linux Foundation. All rights reserved.
*/
#ifndef __SDE_IO_UTIL_H__
#define __SDE_IO_UTIL_H__
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/i2c.h>
#include <linux/types.h>
#ifdef DEBUG
#define DEV_DBG(fmt, args...) pr_err(fmt, ##args)
#else
#define DEV_DBG(fmt, args...) pr_debug(fmt, ##args)
#endif
#define DEV_INFO(fmt, args...) pr_info(fmt, ##args)
#define DEV_WARN(fmt, args...) pr_warn(fmt, ##args)
#define DEV_ERR(fmt, args...) pr_err(fmt, ##args)
struct dss_io_data {
u32 len;
void __iomem *base;
};
void dss_reg_w(struct dss_io_data *io, u32 offset, u32 value, u32 debug);
u32 dss_reg_r(struct dss_io_data *io, u32 offset, u32 debug);
void dss_reg_dump(void __iomem *base, u32 len, const char *prefix, u32 debug);
#define DSS_REG_W_ND(io, offset, val) dss_reg_w(io, offset, val, false)
#define DSS_REG_W(io, offset, val) dss_reg_w(io, offset, val, true)
#define DSS_REG_R_ND(io, offset) dss_reg_r(io, offset, false)
#define DSS_REG_R(io, offset) dss_reg_r(io, offset, true)
enum dss_vreg_type {
DSS_REG_LDO,
DSS_REG_VS,
};
struct dss_vreg {
struct regulator *vreg; /* vreg handle */
char vreg_name[32];
int min_voltage;
int max_voltage;
int enable_load;
int disable_load;
int pre_on_sleep;
int post_on_sleep;
int pre_off_sleep;
int post_off_sleep;
};
struct dss_gpio {
unsigned int gpio;
unsigned int value;
char gpio_name[32];
};
enum dss_clk_type {
DSS_CLK_AHB, /* no set rate. rate controlled through rpm */
DSS_CLK_PCLK,
DSS_CLK_OTHER,
};
struct dss_clk {
struct clk *clk; /* clk handle */
char clk_name[32];
enum dss_clk_type type;
unsigned long rate;
unsigned long max_rate;
};
struct dss_module_power {
unsigned int num_vreg;
struct dss_vreg *vreg_config;
unsigned int num_gpio;
struct dss_gpio *gpio_config;
unsigned int num_clk;
struct dss_clk *clk_config;
};
int msm_dss_ioremap_byname(struct platform_device *pdev,
struct dss_io_data *io_data, const char *name);
void msm_dss_iounmap(struct dss_io_data *io_data);
int msm_dss_enable_gpio(struct dss_gpio *in_gpio, int num_gpio, int enable);
int msm_dss_gpio_enable(struct dss_gpio *in_gpio, int num_gpio, int enable);
int msm_dss_config_vreg(struct device *dev, struct dss_vreg *in_vreg,
int num_vreg, int config);
int msm_dss_enable_vreg(struct dss_vreg *in_vreg, int num_vreg, int enable);
int msm_dss_get_clk(struct device *dev, struct dss_clk *clk_arry, int num_clk);
void msm_dss_put_clk(struct dss_clk *clk_arry, int num_clk);
int msm_dss_clk_set_rate(struct dss_clk *clk_arry, int num_clk);
int msm_dss_single_clk_set_rate(struct dss_clk *clk);
int msm_dss_enable_clk(struct dss_clk *clk_arry, int num_clk, int enable);
int sde_i2c_byte_read(struct i2c_client *client, uint8_t slave_addr,
uint8_t reg_offset, uint8_t *read_buf);
int sde_i2c_byte_write(struct i2c_client *client, uint8_t slave_addr,
uint8_t reg_offset, uint8_t *value);
#endif /* __SDE_IO_UTIL_H__ */

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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
*/
#ifndef _SDE_RSC_H_
#define _SDE_RSC_H_
#include <linux/kernel.h>
/* primary display rsc index */
#define SDE_RSC_INDEX 0
#define MAX_RSC_CLIENT_NAME_LEN 128
/* DRM Object IDs are numbered excluding 0, use 0 to indicate invalid CRTC */
#define SDE_RSC_INVALID_CRTC_ID 0
/**
* event will be triggered before sde core power collapse,
* mdss gdsc is still on
*/
#define SDE_RSC_EVENT_PRE_CORE_PC 0x1
/**
* event will be triggered after sde core collapse complete,
* mdss gdsc is off now
*/
#define SDE_RSC_EVENT_POST_CORE_PC 0x2
/**
* event will be triggered before restoring the sde core from power collapse,
* mdss gdsc is still off
*/
#define SDE_RSC_EVENT_PRE_CORE_RESTORE 0x4
/**
* event will be triggered after restoring the sde core from power collapse,
* mdss gdsc is on now
*/
#define SDE_RSC_EVENT_POST_CORE_RESTORE 0x8
/**
* event attached with solver state enabled
* all clients in clk_state or cmd_state
*/
#define SDE_RSC_EVENT_SOLVER_ENABLED 0x10
/**
* event attached with solver state disabled
* one of the client requested for vid state
*/
#define SDE_RSC_EVENT_SOLVER_DISABLED 0x20
/**
* sde_rsc_client_type: sde rsc client type information
* SDE_RSC_PRIMARY_DISP_CLIENT: A primary display client which can request
* vid or cmd state switch.
* SDE_RSC_EXTERNAL_DISPLAY_CLIENT:An external display client which can
* request only clk state switch.
* SDE_RSC_CLK_CLIENT: A clk client request for only rsc clocks
* enabled and mode_2 exit state.
*/
enum sde_rsc_client_type {
SDE_RSC_PRIMARY_DISP_CLIENT,
SDE_RSC_EXTERNAL_DISP_CLIENT,
SDE_RSC_CLK_CLIENT,
SDE_RSC_INVALID_CLIENT,
};
/**
* sde_rsc_state: sde rsc state information
* SDE_RSC_IDLE_STATE: A client requests for idle state when there is no
* pixel or cmd transfer expected. An idle vote from
* all clients lead to power collapse state.
* SDE_RSC_CLK_STATE: A client requests for clk state when it wants to
* only avoid mode-2 entry/exit. For ex: V4L2 driver,
* sde power handle, etc.
* SDE_RSC_CMD_STATE: A client requests for cmd state when it wants to
* enable the solver mode.
* SDE_RSC_VID_STATE: A client requests for vid state it wants to avoid
* solver enable because client is fetching data from
* continuously.
*/
enum sde_rsc_state {
SDE_RSC_IDLE_STATE,
SDE_RSC_CLK_STATE,
SDE_RSC_CMD_STATE,
SDE_RSC_VID_STATE,
};
/**
* struct sde_rsc_client: stores the rsc client for sde driver
* @name: name of the client
* @current_state: current client state
* @crtc_id: crtc_id associated with this rsc client.
* @rsc_index: rsc index of a client - only index "0" valid.
* @id: Index of client. It will be assigned during client_create call
* @client_type: check sde_rsc_client_type information
* @list: list to attach client master list
*/
struct sde_rsc_client {
char name[MAX_RSC_CLIENT_NAME_LEN];
short current_state;
int crtc_id;
u32 rsc_index;
u32 id;
enum sde_rsc_client_type client_type;
struct list_head list;
};
/**
* struct sde_rsc_event: local event registration entry structure
* @cb_func: Pointer to desired callback function
* @usr: User pointer to pass to callback on event trigger
* @rsc_index: rsc index of a client - only index "0" valid.
* @event_type: refer comments in event_register
* @list: list to attach event master list
*/
struct sde_rsc_event {
void (*cb_func)(uint32_t event_type, void *usr);
void *usr;
u32 rsc_index;
uint32_t event_type;
struct list_head list;
};
/**
* struct sde_rsc_cmd_config: provides panel configuration to rsc
* when client is command mode. It is not required to set it during
* video mode.
*
* @fps: panel te interval
* @vtotal: current vertical total (height + vbp + vfp)
* @jitter_numer: panel jitter numerator value. This config causes rsc/solver
* early before te. Default is 0.8% jitter.
* @jitter_denom: panel jitter denominator.
* @prefill_lines: max prefill lines based on panel
*/
struct sde_rsc_cmd_config {
u32 fps;
u32 vtotal;
u32 jitter_numer;
u32 jitter_denom;
u32 prefill_lines;
};
#ifdef CONFIG_DRM_SDE_RSC
/**
* sde_rsc_client_create() - create the client for sde rsc.
* Different displays like DSI, HDMI, DP, WB, etc should call this
* api to register their vote for rpmh. They still need to vote for
* power handle to get the clocks.
* @rsc_index: A client will be created on this RSC. As of now only
* SDE_RSC_INDEX is valid rsc index.
* @name: Caller needs to provide some valid string to identify
* the client. "primary", "dp", "hdmi" are suggested name.
* @client_type: check client_type enum for information
* @vsync_source: This parameter is only valid for primary display. It provides
* vsync source information
*
* Return: client node pointer.
*/
struct sde_rsc_client *sde_rsc_client_create(u32 rsc_index, char *name,
enum sde_rsc_client_type client_type, u32 vsync_source);
/**
* sde_rsc_client_destroy() - Destroy the sde rsc client.
*
* @client: Client pointer provided by sde_rsc_client_create().
*
* Return: none
*/
void sde_rsc_client_destroy(struct sde_rsc_client *client);
/**
* sde_rsc_client_state_update() - rsc client state update
* Video mode, cmd mode and clk state are supported as modes. A client need to
* set this property during panel time. A switching client can set the
* property to change the state
*
* @client: Client pointer provided by sde_rsc_client_create().
* @state: Client state - video/cmd
* @config: fps, vtotal, porches, etc configuration for command mode
* panel
* @crtc_id: current client's crtc id
* @wait_vblank_crtc_id: Output parameter. If set to non-zero, rsc hw
* state update requires a wait for one vblank on
* the primary crtc. In that case, this output
* param will be set to the crtc on which to wait.
* If SDE_RSC_INVALID_CRTC_ID, no wait necessary
*
* Return: error code.
*/
int sde_rsc_client_state_update(struct sde_rsc_client *client,
enum sde_rsc_state state,
struct sde_rsc_cmd_config *config, int crtc_id,
int *wait_vblank_crtc_id);
/**
* sde_rsc_client_get_vsync_refcount() - returns the status of the vsync
* refcount, to signal if the client needs to reset the refcounting logic
* @client: Client pointer provided by sde_rsc_client_create().
*
* Return: true if the state update has completed.
*/
int sde_rsc_client_get_vsync_refcount(
struct sde_rsc_client *caller_client);
/**
* sde_rsc_client_reset_vsync_refcount() - reduces the refcounting
* logic that waits for the vsync.
* @client: Client pointer provided by sde_rsc_client_create().
*
* Return: true if the state update has completed.
*/
int sde_rsc_client_reset_vsync_refcount(
struct sde_rsc_client *caller_client);
/**
* sde_rsc_client_is_state_update_complete() - check if state update is complete
* RSC state transition is not complete until HW receives VBLANK signal. This
* function checks RSC HW to determine whether that signal has been received.
* @client: Client pointer provided by sde_rsc_client_create().
*
* Return: true if the state update has completed.
*/
bool sde_rsc_client_is_state_update_complete(
struct sde_rsc_client *caller_client);
/**
* sde_rsc_client_vote() - stores ab/ib vote for rsc client
*
* @client: Client pointer provided by sde_rsc_client_create().
* @bus_id: data bus identifier
* @ab: aggregated bandwidth vote from client.
* @ib: instant bandwidth vote from client.
*
* Return: error code.
*/
int sde_rsc_client_vote(struct sde_rsc_client *caller_client,
u32 bus_id, u64 ab_vote, u64 ib_vote);
/**
* sde_rsc_register_event - register a callback function for an event
* @rsc_index: A client will be created on this RSC. As of now only
* SDE_RSC_INDEX is valid rsc index.
* @event_type: event type to register; client sets 0x3 if it wants
* to register for CORE_PC and CORE_RESTORE - both events.
* @cb_func: Pointer to desired callback function
* @usr: User pointer to pass to callback on event trigger
* Returns: sde_rsc_event pointer on success
*/
struct sde_rsc_event *sde_rsc_register_event(int rsc_index, uint32_t event_type,
void (*cb_func)(uint32_t event_type, void *usr), void *usr);
/**
* sde_rsc_unregister_event - unregister callback for an event
* @sde_rsc_event: event returned by sde_rsc_register_event
*/
void sde_rsc_unregister_event(struct sde_rsc_event *event);
/**
* is_sde_rsc_available - check if display rsc available.
* @rsc_index: A client will be created on this RSC. As of now only
* SDE_RSC_INDEX is valid rsc index.
* Returns: true if rsc is available; false in all other cases
*/
bool is_sde_rsc_available(int rsc_index);
/**
* get_sde_rsc_current_state - gets the current state of sde rsc.
* @rsc_index: A client will be created on this RSC. As of now only
* SDE_RSC_INDEX is valid rsc index.
* Returns: current state if rsc available; SDE_RSC_IDLE_STATE for
* all other cases
*/
enum sde_rsc_state get_sde_rsc_current_state(int rsc_index);
/**
* sde_rsc_client_trigger_vote() - triggers ab/ib vote for rsc client
*
* @client: Client pointer provided by sde_rsc_client_create().
* @delta_vote: if bw vote is increased or decreased
*
* Return: error code.
*/
int sde_rsc_client_trigger_vote(struct sde_rsc_client *caller_client,
bool delta_vote);
#else
static inline struct sde_rsc_client *sde_rsc_client_create(u32 rsc_index,
char *name, enum sde_rsc_client_type client_type, u32 vsync_source)
{
return NULL;
}
static inline void sde_rsc_client_destroy(struct sde_rsc_client *client)
{
}
static inline int sde_rsc_client_state_update(struct sde_rsc_client *client,
enum sde_rsc_state state,
struct sde_rsc_cmd_config *config, int crtc_id,
int *wait_vblank_crtc_id)
{
return 0;
}
static inline int sde_rsc_client_get_vsync_refcount(
struct sde_rsc_client *caller_client)
{
return 0;
}
static inline int sde_rsc_client_reset_vsync_refcount(
struct sde_rsc_client *caller_client)
{
return 0;
}
static inline bool sde_rsc_client_is_state_update_complete(
struct sde_rsc_client *caller_client)
{
return false;
}
static inline int sde_rsc_client_vote(struct sde_rsc_client *caller_client,
u32 bus_id, u64 ab_vote, u64 ib_vote)
{
return 0;
}
static inline struct sde_rsc_event *sde_rsc_register_event(int rsc_index,
uint32_t event_type,
void (*cb_func)(uint32_t event_type, void *usr), void *usr)
{
return NULL;
}
static inline void sde_rsc_unregister_event(struct sde_rsc_event *event)
{
}
static inline bool is_sde_rsc_available(int rsc_index)
{
return false;
}
static inline enum sde_rsc_state get_sde_rsc_current_state(int rsc_index)
{
return SDE_RSC_IDLE_STATE;
}
static inline int sde_rsc_client_trigger_vote(
struct sde_rsc_client *caller_client, bool delta_vote)
{
return 0;
}
#endif /* CONFIG_DRM_SDE_RSC */
#endif /* _SDE_RSC_H_ */

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# SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note
header-y += media/
header-y += drm/

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# SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note
header-y += msm_drm_pp.h
header-y += sde_drm.h

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/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
/*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
*/
#ifndef _MSM_DRM_PP_H_
#define _MSM_DRM_PP_H_
#include <linux/types.h>
/**
* struct drm_msm_pcc_coeff - PCC coefficient structure for each color
* component.
* @c: constant coefficient.
* @r: red coefficient.
* @g: green coefficient.
* @b: blue coefficient.
* @rg: red green coefficient.
* @gb: green blue coefficient.
* @rb: red blue coefficient.
* @rgb: red blue green coefficient.
*/
struct drm_msm_pcc_coeff {
__u32 c;
__u32 r;
__u32 g;
__u32 b;
__u32 rg;
__u32 gb;
__u32 rb;
__u32 rgb;
};
/**
* struct drm_msm_pcc - pcc feature structure
* @flags: for customizing operations
* @r: red coefficients.
* @g: green coefficients.
* @b: blue coefficients.
* @r_rr: second order coefficients
* @r_gg: second order coefficients
* @r_bb: second order coefficients
* @g_rr: second order coefficients
* @g_gg: second order coefficients
* @g_bb: second order coefficients
* @b_rr: second order coefficients
* @b_gg: second order coefficients
* @b_bb: second order coefficients
*/
#define DRM_MSM_PCC3
struct drm_msm_pcc {
__u64 flags;
struct drm_msm_pcc_coeff r;
struct drm_msm_pcc_coeff g;
struct drm_msm_pcc_coeff b;
__u32 r_rr;
__u32 r_gg;
__u32 r_bb;
__u32 g_rr;
__u32 g_gg;
__u32 g_bb;
__u32 b_rr;
__u32 b_gg;
__u32 b_bb;
};
/* struct drm_msm_pa_vlut - picture adjustment vLUT structure
* flags: for customizing vlut operation
* val: vLUT values
*/
#define PA_VLUT_SIZE 256
struct drm_msm_pa_vlut {
__u64 flags;
__u32 val[PA_VLUT_SIZE];
};
#define PA_HSIC_HUE_ENABLE (1 << 0)
#define PA_HSIC_SAT_ENABLE (1 << 1)
#define PA_HSIC_VAL_ENABLE (1 << 2)
#define PA_HSIC_CONT_ENABLE (1 << 3)
/**
* struct drm_msm_pa_hsic - pa hsic feature structure
* @flags: flags for the feature customization, values can be:
* - PA_HSIC_HUE_ENABLE: Enable hue adjustment
* - PA_HSIC_SAT_ENABLE: Enable saturation adjustment
* - PA_HSIC_VAL_ENABLE: Enable value adjustment
* - PA_HSIC_CONT_ENABLE: Enable contrast adjustment
*
* @hue: hue setting
* @saturation: saturation setting
* @value: value setting
* @contrast: contrast setting
*/
#define DRM_MSM_PA_HSIC
struct drm_msm_pa_hsic {
__u64 flags;
__u32 hue;
__u32 saturation;
__u32 value;
__u32 contrast;
};
#define MEMCOL_PROT_HUE (1 << 0)
#define MEMCOL_PROT_SAT (1 << 1)
#define MEMCOL_PROT_VAL (1 << 2)
#define MEMCOL_PROT_CONT (1 << 3)
#define MEMCOL_PROT_SIXZONE (1 << 4)
#define MEMCOL_PROT_BLEND (1 << 5)
/* struct drm_msm_memcol - Memory color feature structure.
* Skin, sky, foliage features are supported.
* @prot_flags: Bit mask for enabling protection feature.
* @color_adjust_p0: Adjustment curve.
* @color_adjust_p1: Adjustment curve.
* @color_adjust_p2: Adjustment curve.
* @blend_gain: Blend gain weightage from othe PA features.
* @sat_hold: Saturation hold value.
* @val_hold: Value hold info.
* @hue_region: Hue qualifier.
* @sat_region: Saturation qualifier.
* @val_region: Value qualifier.
*/
#define DRM_MSM_MEMCOL
struct drm_msm_memcol {
__u64 prot_flags;
__u32 color_adjust_p0;
__u32 color_adjust_p1;
__u32 color_adjust_p2;
__u32 blend_gain;
__u32 sat_hold;
__u32 val_hold;
__u32 hue_region;
__u32 sat_region;
__u32 val_region;
};
#define DRM_MSM_SIXZONE
#define SIXZONE_LUT_SIZE 384
#define SIXZONE_HUE_ENABLE (1 << 0)
#define SIXZONE_SAT_ENABLE (1 << 1)
#define SIXZONE_VAL_ENABLE (1 << 2)
/* struct drm_msm_sixzone_curve - Sixzone HSV adjustment curve structure.
* @p0: Hue adjustment.
* @p1: Saturation/Value adjustment.
*/
struct drm_msm_sixzone_curve {
__u32 p1;
__u32 p0;
};
/* struct drm_msm_sixzone - Sixzone feature structure.
* @flags: for feature customization, values can be:
* - SIXZONE_HUE_ENABLE: Enable hue adjustment
* - SIXZONE_SAT_ENABLE: Enable saturation adjustment
* - SIXZONE_VAL_ENABLE: Enable value adjustment
* @threshold: threshold qualifier.
* @adjust_p0: Adjustment curve.
* @adjust_p1: Adjustment curve.
* @sat_hold: Saturation hold info.
* @val_hold: Value hold info.
* @curve: HSV adjustment curve lut.
*/
struct drm_msm_sixzone {
__u64 flags;
__u32 threshold;
__u32 adjust_p0;
__u32 adjust_p1;
__u32 sat_hold;
__u32 val_hold;
struct drm_msm_sixzone_curve curve[SIXZONE_LUT_SIZE];
};
#define GAMUT_3D_MODE_17 1
#define GAMUT_3D_MODE_5 2
#define GAMUT_3D_MODE_13 3
#define GAMUT_3D_MODE17_TBL_SZ 1229
#define GAMUT_3D_MODE5_TBL_SZ 32
#define GAMUT_3D_MODE13_TBL_SZ 550
#define GAMUT_3D_SCALE_OFF_SZ 16
#define GAMUT_3D_SCALEB_OFF_SZ 12
#define GAMUT_3D_TBL_NUM 4
#define GAMUT_3D_SCALE_OFF_TBL_NUM 3
#define GAMUT_3D_MAP_EN (1 << 0)
/**
* struct drm_msm_3d_col - 3d gamut color component structure
* @c0: Holds c0 value
* @c2_c1: Holds c2/c1 values
*/
struct drm_msm_3d_col {
__u32 c2_c1;
__u32 c0;
};
/**
* struct drm_msm_3d_gamut - 3d gamut feature structure
* @flags: flags for the feature values are:
* 0 - no map
* GAMUT_3D_MAP_EN - enable map
* @mode: lut mode can take following values:
* - GAMUT_3D_MODE_17
* - GAMUT_3D_MODE_5
* - GAMUT_3D_MODE_13
* @scale_off: Scale offset table
* @col: Color component tables
*/
struct drm_msm_3d_gamut {
__u64 flags;
__u32 mode;
__u32 scale_off[GAMUT_3D_SCALE_OFF_TBL_NUM][GAMUT_3D_SCALE_OFF_SZ];
struct drm_msm_3d_col col[GAMUT_3D_TBL_NUM][GAMUT_3D_MODE17_TBL_SZ];
};
#define PGC_TBL_LEN 512
#define PGC_8B_ROUND (1 << 0)
/**
* struct drm_msm_pgc_lut - pgc lut feature structure
* @flags: flags for the featue values can be:
* - PGC_8B_ROUND
* @c0: color0 component lut
* @c1: color1 component lut
* @c2: color2 component lut
*/
struct drm_msm_pgc_lut {
__u64 flags;
__u32 c0[PGC_TBL_LEN];
__u32 c1[PGC_TBL_LEN];
__u32 c2[PGC_TBL_LEN];
};
#define IGC_TBL_LEN 256
#define IGC_DITHER_ENABLE (1 << 0)
/**
* struct drm_msm_igc_lut - igc lut feature structure
* @flags: flags for the feature customization, values can be:
* - IGC_DITHER_ENABLE: Enable dither functionality
* @c0: color0 component lut
* @c1: color1 component lut
* @c2: color2 component lut
* @strength: dither strength, considered valid when IGC_DITHER_ENABLE
* is set in flags. Strength value based on source bit width.
* @c0_last: color0 lut_last component
* @c1_last: color1 lut_last component
* @c2_last: color2 lut_last component
*/
struct drm_msm_igc_lut {
__u64 flags;
__u32 c0[IGC_TBL_LEN];
__u32 c1[IGC_TBL_LEN];
__u32 c2[IGC_TBL_LEN];
__u32 strength;
__u32 c0_last;
__u32 c1_last;
__u32 c2_last;
};
#define LAST_LUT 2
#define HIST_V_SIZE 256
/**
* struct drm_msm_hist - histogram feature structure
* @flags: for customizing operations
* @data: histogram data
*/
struct drm_msm_hist {
__u64 flags;
__u32 data[HIST_V_SIZE];
};
#define AD4_LUT_GRP0_SIZE 33
#define AD4_LUT_GRP1_SIZE 32
/*
* struct drm_msm_ad4_init - ad4 init structure set by user-space client.
* Init param values can change based on tuning
* hence it is passed by user-space clients.
*/
struct drm_msm_ad4_init {
__u32 init_param_001[AD4_LUT_GRP0_SIZE];
__u32 init_param_002[AD4_LUT_GRP0_SIZE];
__u32 init_param_003[AD4_LUT_GRP0_SIZE];
__u32 init_param_004[AD4_LUT_GRP0_SIZE];
__u32 init_param_005[AD4_LUT_GRP1_SIZE];
__u32 init_param_006[AD4_LUT_GRP1_SIZE];
__u32 init_param_007[AD4_LUT_GRP0_SIZE];
__u32 init_param_008[AD4_LUT_GRP0_SIZE];
__u32 init_param_009;
__u32 init_param_010;
__u32 init_param_011;
__u32 init_param_012;
__u32 init_param_013;
__u32 init_param_014;
__u32 init_param_015;
__u32 init_param_016;
__u32 init_param_017;
__u32 init_param_018;
__u32 init_param_019;
__u32 init_param_020;
__u32 init_param_021;
__u32 init_param_022;
__u32 init_param_023;
__u32 init_param_024;
__u32 init_param_025;
__u32 init_param_026;
__u32 init_param_027;
__u32 init_param_028;
__u32 init_param_029;
__u32 init_param_030;
__u32 init_param_031;
__u32 init_param_032;
__u32 init_param_033;
__u32 init_param_034;
__u32 init_param_035;
__u32 init_param_036;
__u32 init_param_037;
__u32 init_param_038;
__u32 init_param_039;
__u32 init_param_040;
__u32 init_param_041;
__u32 init_param_042;
__u32 init_param_043;
__u32 init_param_044;
__u32 init_param_045;
__u32 init_param_046;
__u32 init_param_047;
__u32 init_param_048;
__u32 init_param_049;
__u32 init_param_050;
__u32 init_param_051;
__u32 init_param_052;
__u32 init_param_053;
__u32 init_param_054;
__u32 init_param_055;
__u32 init_param_056;
__u32 init_param_057;
__u32 init_param_058;
__u32 init_param_059;
__u32 init_param_060;
__u32 init_param_061;
__u32 init_param_062;
__u32 init_param_063;
__u32 init_param_064;
__u32 init_param_065;
__u32 init_param_066;
__u32 init_param_067;
__u32 init_param_068;
__u32 init_param_069;
__u32 init_param_070;
__u32 init_param_071;
__u32 init_param_072;
__u32 init_param_073;
__u32 init_param_074;
__u32 init_param_075;
};
/*
* struct drm_msm_ad4_cfg - ad4 config structure set by user-space client.
* Config param values can vary based on tuning,
* hence it is passed by user-space clients.
*/
struct drm_msm_ad4_cfg {
__u32 cfg_param_001;
__u32 cfg_param_002;
__u32 cfg_param_003;
__u32 cfg_param_004;
__u32 cfg_param_005;
__u32 cfg_param_006;
__u32 cfg_param_007;
__u32 cfg_param_008;
__u32 cfg_param_009;
__u32 cfg_param_010;
__u32 cfg_param_011;
__u32 cfg_param_012;
__u32 cfg_param_013;
__u32 cfg_param_014;
__u32 cfg_param_015;
__u32 cfg_param_016;
__u32 cfg_param_017;
__u32 cfg_param_018;
__u32 cfg_param_019;
__u32 cfg_param_020;
__u32 cfg_param_021;
__u32 cfg_param_022;
__u32 cfg_param_023;
__u32 cfg_param_024;
__u32 cfg_param_025;
__u32 cfg_param_026;
__u32 cfg_param_027;
__u32 cfg_param_028;
__u32 cfg_param_029;
__u32 cfg_param_030;
__u32 cfg_param_031;
__u32 cfg_param_032;
__u32 cfg_param_033;
__u32 cfg_param_034;
__u32 cfg_param_035;
__u32 cfg_param_036;
__u32 cfg_param_037;
__u32 cfg_param_038;
__u32 cfg_param_039;
__u32 cfg_param_040;
__u32 cfg_param_041;
__u32 cfg_param_042;
__u32 cfg_param_043;
__u32 cfg_param_044;
__u32 cfg_param_045;
__u32 cfg_param_046;
__u32 cfg_param_047;
__u32 cfg_param_048;
__u32 cfg_param_049;
__u32 cfg_param_050;
__u32 cfg_param_051;
__u32 cfg_param_052;
__u32 cfg_param_053;
};
#define DITHER_MATRIX_SZ 16
/**
* struct drm_msm_dither - dither feature structure
* @flags: for customizing operations
* @temporal_en: temperal dither enable
* @c0_bitdepth: c0 component bit depth
* @c1_bitdepth: c1 component bit depth
* @c2_bitdepth: c2 component bit depth
* @c3_bitdepth: c2 component bit depth
* @matrix: dither strength matrix
*/
struct drm_msm_dither {
__u64 flags;
__u32 temporal_en;
__u32 c0_bitdepth;
__u32 c1_bitdepth;
__u32 c2_bitdepth;
__u32 c3_bitdepth;
__u32 matrix[DITHER_MATRIX_SZ];
};
/**
* struct drm_msm_pa_dither - dspp dither feature structure
* @flags: for customizing operations
* @strength: dither strength
* @offset_en: offset enable bit
* @matrix: dither data matrix
*/
#define DRM_MSM_PA_DITHER
struct drm_msm_pa_dither {
__u64 flags;
__u32 strength;
__u32 offset_en;
__u32 matrix[DITHER_MATRIX_SZ];
};
/**
* struct drm_msm_ad4_roi_cfg - ad4 roi params config set
* by user-space client.
* @h_x - hotizontal direction start
* @h_y - hotizontal direction end
* @v_x - vertical direction start
* @v_y - vertical direction end
* @factor_in - the alpha value for inside roi region
* @factor_out - the alpha value for outside roi region
*/
#define DRM_MSM_AD4_ROI
struct drm_msm_ad4_roi_cfg {
__u32 h_x;
__u32 h_y;
__u32 v_x;
__u32 v_y;
__u32 factor_in;
__u32 factor_out;
};
#define LTM_FEATURE_DEF 1
#define LTM_DATA_SIZE_0 32
#define LTM_DATA_SIZE_1 128
#define LTM_DATA_SIZE_2 256
#define LTM_DATA_SIZE_3 33
#define LTM_BUFFER_SIZE 5
#define LTM_GUARD_BYTES 255
#define LTM_BLOCK_SIZE 2
#define LTM_STATS_SAT (1 << 1)
#define LTM_STATS_MERGE_SAT (1 << 2)
/*
* struct drm_msm_ltm_stats_data - LTM stats data structure
*/
struct drm_msm_ltm_stats_data {
__u32 stats_01[LTM_DATA_SIZE_0][LTM_DATA_SIZE_1];
__u32 stats_02[LTM_DATA_SIZE_2];
__u32 stats_03[LTM_DATA_SIZE_0];
__u32 stats_04[LTM_DATA_SIZE_0];
__u32 stats_05[LTM_DATA_SIZE_0];
__u32 status_flag;
__u32 display_h;
__u32 display_v;
__u32 init_h[LTM_BLOCK_SIZE];
__u32 init_v;
__u32 inc_h;
__u32 inc_v;
__u32 portrait_en;
__u32 merge_en;
__u32 cfg_param_01;
__u32 cfg_param_02;
__u32 cfg_param_03;
__u32 cfg_param_04;
};
/*
* struct drm_msm_ltm_init_param - LTM init param structure
*/
struct drm_msm_ltm_init_param {
__u32 init_param_01;
__u32 init_param_02;
__u32 init_param_03;
__u32 init_param_04;
};
/*
* struct drm_msm_ltm_cfg_param - LTM config param structure
*/
struct drm_msm_ltm_cfg_param {
__u32 cfg_param_01;
__u32 cfg_param_02;
__u32 cfg_param_03;
__u32 cfg_param_04;
__u32 cfg_param_05;
__u32 cfg_param_06;
};
/*
* struct drm_msm_ltm_data - LTM data structure
*/
struct drm_msm_ltm_data {
__u32 data[LTM_DATA_SIZE_0][LTM_DATA_SIZE_3];
};
/*
* struct drm_msm_ltm_buffers_crtl - LTM buffer control structure.
* This struct will be used to init and
* de-init the LTM buffers in driver.
* @num_of_buffers: valid number of buffers used
* @fds: fd array to for all the valid buffers
*/
struct drm_msm_ltm_buffers_ctrl {
__u32 num_of_buffers;
__u32 fds[LTM_BUFFER_SIZE];
};
/*
* struct drm_msm_ltm_buffer - LTM buffer structure.
* This struct will be passed from driver to user
* space for LTM stats data notification.
* @fd: fd assicated with the buffer that has LTM stats data
* @offset: offset from base address that used for alignment
* @status status flag for error indication
*/
struct drm_msm_ltm_buffer {
__u32 fd;
__u32 offset;
__u32 status;
};
/**
* struct drm_msm_ad4_manual_str_cfg - ad4 manual strength config set
* by user-space client.
* @in_str - strength for inside roi region
* @out_str - strength for outside roi region
*/
#define DRM_MSM_AD4_MANUAL_STRENGTH
struct drm_msm_ad4_manual_str_cfg {
__u32 in_str;
__u32 out_str;
};
#endif /* _MSM_DRM_PP_H_ */

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include/uapi/drm/sde_drm.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
/*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
*/
#ifndef _SDE_DRM_H_
#define _SDE_DRM_H_
#include <drm/drm.h>
#if defined(__cplusplus)
extern "C" {
#endif
/* Total number of supported color planes */
#define SDE_MAX_PLANES 4
/* Total number of parameterized detail enhancer mapping curves */
#define SDE_MAX_DE_CURVES 3
/* Y/RGB and UV filter configuration */
#define FILTER_EDGE_DIRECTED_2D 0x0
#define FILTER_CIRCULAR_2D 0x1
#define FILTER_SEPARABLE_1D 0x2
#define FILTER_BILINEAR 0x3
/* Alpha filters */
#define FILTER_ALPHA_DROP_REPEAT 0x0
#define FILTER_ALPHA_BILINEAR 0x1
#define FILTER_ALPHA_2D 0x3
/* Blend filters */
#define FILTER_BLEND_CIRCULAR_2D 0x0
#define FILTER_BLEND_SEPARABLE_1D 0x1
/* LUT configuration flags */
#define SCALER_LUT_SWAP 0x1
#define SCALER_LUT_DIR_WR 0x2
#define SCALER_LUT_Y_CIR_WR 0x4
#define SCALER_LUT_UV_CIR_WR 0x8
#define SCALER_LUT_Y_SEP_WR 0x10
#define SCALER_LUT_UV_SEP_WR 0x20
/**
* Blend operations for "blend_op" property
*
* @SDE_DRM_BLEND_OP_NOT_DEFINED: No blend operation defined for the layer.
* @SDE_DRM_BLEND_OP_OPAQUE: Apply a constant blend operation. The layer
* would appear opaque in case fg plane alpha
* is 0xff.
* @SDE_DRM_BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already
* has alpha pre-multiplication done. If the fg
* plane alpha is less than 0xff, apply
* modulation as well. This operation is
* intended on layers having alpha channel.
* @SDE_DRM_BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not
* alpha pre-multiplied. Apply
* pre-multiplication. If fg plane alpha is
* less than 0xff, apply modulation as well.
* @SDE_DRM_BLEND_OP_MAX: Used to track maximum blend operation
* possible by mdp.
*/
#define SDE_DRM_BLEND_OP_NOT_DEFINED 0
#define SDE_DRM_BLEND_OP_OPAQUE 1
#define SDE_DRM_BLEND_OP_PREMULTIPLIED 2
#define SDE_DRM_BLEND_OP_COVERAGE 3
#define SDE_DRM_BLEND_OP_MAX 4
/**
* Bit masks for "src_config" property
* construct bitmask via (1UL << SDE_DRM_<flag>)
*/
#define SDE_DRM_DEINTERLACE 0 /* Specifies interlaced input */
/* DRM bitmasks are restricted to 0..63 */
#define SDE_DRM_BITMASK_COUNT 64
/**
* Framebuffer modes for "fb_translation_mode" PLANE and CONNECTOR property
*
* @SDE_DRM_FB_NON_SEC: IOMMU configuration for this framebuffer mode
* is non-secure domain and requires
* both stage I and stage II translations when
* this buffer is accessed by the display HW.
* This is the default mode of all frambuffers.
* @SDE_DRM_FB_SEC: IOMMU configuration for this framebuffer mode
* is secure domain and requires
* both stage I and stage II translations when
* this buffer is accessed by the display HW.
* @SDE_DRM_FB_NON_SEC_DIR_TRANS: IOMMU configuration for this framebuffer mode
* is non-secure domain and requires
* only stage II translation when
* this buffer is accessed by the display HW.
* @SDE_DRM_FB_SEC_DIR_TRANS: IOMMU configuration for this framebuffer mode
* is secure domain and requires
* only stage II translation when
* this buffer is accessed by the display HW.
*/
#define SDE_DRM_FB_NON_SEC 0
#define SDE_DRM_FB_SEC 1
#define SDE_DRM_FB_NON_SEC_DIR_TRANS 2
#define SDE_DRM_FB_SEC_DIR_TRANS 3
/**
* Secure levels for "security_level" CRTC property.
* CRTC property which specifies what plane types
* can be attached to this CRTC. Plane component
* derives the plane type based on the FB_MODE.
* @ SDE_DRM_SEC_NON_SEC: Both Secure and non-secure plane types can be
* attached to this CRTC. This is the default state of
* the CRTC.
* @ SDE_DRM_SEC_ONLY: Only secure planes can be added to this CRTC. If a
* CRTC is instructed to be in this mode it follows the
* platform dependent restrictions.
*/
#define SDE_DRM_SEC_NON_SEC 0
#define SDE_DRM_SEC_ONLY 1
/**
* struct sde_drm_pix_ext_v1 - version 1 of pixel ext structure
* @num_ext_pxls_lr: Number of total horizontal pixels
* @num_ext_pxls_tb: Number of total vertical lines
* @left_ftch: Number of extra pixels to overfetch from left
* @right_ftch: Number of extra pixels to overfetch from right
* @top_ftch: Number of extra lines to overfetch from top
* @btm_ftch: Number of extra lines to overfetch from bottom
* @left_rpt: Number of extra pixels to repeat from left
* @right_rpt: Number of extra pixels to repeat from right
* @top_rpt: Number of extra lines to repeat from top
* @btm_rpt: Number of extra lines to repeat from bottom
*/
struct sde_drm_pix_ext_v1 {
/*
* Number of pixels ext in left, right, top and bottom direction
* for all color components.
*/
int32_t num_ext_pxls_lr[SDE_MAX_PLANES];
int32_t num_ext_pxls_tb[SDE_MAX_PLANES];
/*
* Number of pixels needs to be overfetched in left, right, top
* and bottom directions from source image for scaling.
*/
int32_t left_ftch[SDE_MAX_PLANES];
int32_t right_ftch[SDE_MAX_PLANES];
int32_t top_ftch[SDE_MAX_PLANES];
int32_t btm_ftch[SDE_MAX_PLANES];
/*
* Number of pixels needs to be repeated in left, right, top and
* bottom directions for scaling.
*/
int32_t left_rpt[SDE_MAX_PLANES];
int32_t right_rpt[SDE_MAX_PLANES];
int32_t top_rpt[SDE_MAX_PLANES];
int32_t btm_rpt[SDE_MAX_PLANES];
};
/**
* struct sde_drm_scaler_v1 - version 1 of struct sde_drm_scaler
* @lr: Pixel extension settings for left/right
* @tb: Pixel extension settings for top/botton
* @init_phase_x: Initial scaler phase values for x
* @phase_step_x: Phase step values for x
* @init_phase_y: Initial scaler phase values for y
* @phase_step_y: Phase step values for y
* @horz_filter: Horizontal filter array
* @vert_filter: Vertical filter array
*/
struct sde_drm_scaler_v1 {
/*
* Pix ext settings
*/
struct sde_drm_pix_ext_v1 pe;
/*
* Phase settings
*/
int32_t init_phase_x[SDE_MAX_PLANES];
int32_t phase_step_x[SDE_MAX_PLANES];
int32_t init_phase_y[SDE_MAX_PLANES];
int32_t phase_step_y[SDE_MAX_PLANES];
/*
* Filter type to be used for scaling in horizontal and vertical
* directions
*/
uint32_t horz_filter[SDE_MAX_PLANES];
uint32_t vert_filter[SDE_MAX_PLANES];
};
/**
* struct sde_drm_de_v1 - version 1 of detail enhancer structure
* @enable: Enables/disables detail enhancer
* @sharpen_level1: Sharpening strength for noise
* @sharpen_level2: Sharpening strength for context
* @clip: Clip coefficient
* @limit: Detail enhancer limit factor
* @thr_quiet: Quite zone threshold
* @thr_dieout: Die-out zone threshold
* @thr_low: Linear zone left threshold
* @thr_high: Linear zone right threshold
* @prec_shift: Detail enhancer precision
* @adjust_a: Mapping curves A coefficients
* @adjust_b: Mapping curves B coefficients
* @adjust_c: Mapping curves C coefficients
*/
struct sde_drm_de_v1 {
uint32_t enable;
int16_t sharpen_level1;
int16_t sharpen_level2;
uint16_t clip;
uint16_t limit;
uint16_t thr_quiet;
uint16_t thr_dieout;
uint16_t thr_low;
uint16_t thr_high;
uint16_t prec_shift;
int16_t adjust_a[SDE_MAX_DE_CURVES];
int16_t adjust_b[SDE_MAX_DE_CURVES];
int16_t adjust_c[SDE_MAX_DE_CURVES];
};
/*
* Scaler configuration flags
*/
/* Disable dynamic expansion */
#define SDE_DYN_EXP_DISABLE 0x1
#define SDE_DRM_QSEED3LITE
#define SDE_DRM_QSEED4
/**
* struct sde_drm_scaler_v2 - version 2 of struct sde_drm_scaler
* @enable: Scaler enable
* @dir_en: Detail enhancer enable
* @pe: Pixel extension settings
* @horz_decimate: Horizontal decimation factor
* @vert_decimate: Vertical decimation factor
* @init_phase_x: Initial scaler phase values for x
* @phase_step_x: Phase step values for x
* @init_phase_y: Initial scaler phase values for y
* @phase_step_y: Phase step values for y
* @preload_x: Horizontal preload value
* @preload_y: Vertical preload value
* @src_width: Source width
* @src_height: Source height
* @dst_width: Destination width
* @dst_height: Destination height
* @y_rgb_filter_cfg: Y/RGB plane filter configuration
* @uv_filter_cfg: UV plane filter configuration
* @alpha_filter_cfg: Alpha filter configuration
* @blend_cfg: Selection of blend coefficients
* @lut_flag: LUT configuration flags
* @dir_lut_idx: 2d 4x4 LUT index
* @y_rgb_cir_lut_idx: Y/RGB circular LUT index
* @uv_cir_lut_idx: UV circular LUT index
* @y_rgb_sep_lut_idx: Y/RGB separable LUT index
* @uv_sep_lut_idx: UV separable LUT index
* @de: Detail enhancer settings
* @dir_weight: Directional Weight
* @unsharp_mask_blend: Unsharp Blend Filter Ratio
* @de_blend: Ratio of two unsharp mask filters
* @flags: Scaler configuration flags
*/
struct sde_drm_scaler_v2 {
/*
* General definitions
*/
uint32_t enable;
uint32_t dir_en;
/*
* Pix ext settings
*/
struct sde_drm_pix_ext_v1 pe;
/*
* Decimation settings
*/
uint32_t horz_decimate;
uint32_t vert_decimate;
/*
* Phase settings
*/
int32_t init_phase_x[SDE_MAX_PLANES];
int32_t phase_step_x[SDE_MAX_PLANES];
int32_t init_phase_y[SDE_MAX_PLANES];
int32_t phase_step_y[SDE_MAX_PLANES];
uint32_t preload_x[SDE_MAX_PLANES];
uint32_t preload_y[SDE_MAX_PLANES];
uint32_t src_width[SDE_MAX_PLANES];
uint32_t src_height[SDE_MAX_PLANES];
uint32_t dst_width;
uint32_t dst_height;
uint32_t y_rgb_filter_cfg;
uint32_t uv_filter_cfg;
uint32_t alpha_filter_cfg;
uint32_t blend_cfg;
uint32_t lut_flag;
uint32_t dir_lut_idx;
/* for Y(RGB) and UV planes*/
uint32_t y_rgb_cir_lut_idx;
uint32_t uv_cir_lut_idx;
uint32_t y_rgb_sep_lut_idx;
uint32_t uv_sep_lut_idx;
/*
* Detail enhancer settings
*/
struct sde_drm_de_v1 de;
uint32_t dir_weight;
uint32_t unsharp_mask_blend;
uint32_t de_blend;
uint32_t flags;
};
/* Number of dest scalers supported */
#define SDE_MAX_DS_COUNT 2
/*
* Destination scaler flag config
*/
#define SDE_DRM_DESTSCALER_ENABLE 0x1
#define SDE_DRM_DESTSCALER_SCALE_UPDATE 0x2
#define SDE_DRM_DESTSCALER_ENHANCER_UPDATE 0x4
#define SDE_DRM_DESTSCALER_PU_ENABLE 0x8
/**
* struct sde_drm_dest_scaler_cfg - destination scaler config structure
* @flags: Flag to switch between mode for destination scaler
* refer to destination scaler flag config
* @index: Destination scaler selection index
* @lm_width: Layer mixer width configuration
* @lm_height: Layer mixer height configuration
* @scaler_cfg: The scaling parameters for all the mode except disable
* Userspace pointer to struct sde_drm_scaler_v2
*/
struct sde_drm_dest_scaler_cfg {
uint32_t flags;
uint32_t index;
uint32_t lm_width;
uint32_t lm_height;
uint64_t scaler_cfg;
};
/**
* struct sde_drm_dest_scaler_data - destination scaler data struct
* @num_dest_scaler: Number of dest scalers to be configured
* @ds_cfg: Destination scaler block configuration
*/
struct sde_drm_dest_scaler_data {
uint32_t num_dest_scaler;
struct sde_drm_dest_scaler_cfg ds_cfg[SDE_MAX_DS_COUNT];
};
/*
* Define constants for struct sde_drm_csc
*/
#define SDE_CSC_MATRIX_COEFF_SIZE 9
#define SDE_CSC_CLAMP_SIZE 6
#define SDE_CSC_BIAS_SIZE 3
/**
* struct sde_drm_csc_v1 - version 1 of struct sde_drm_csc
* @ctm_coeff: Matrix coefficients, in S31.32 format
* @pre_bias: Pre-bias array values
* @post_bias: Post-bias array values
* @pre_clamp: Pre-clamp array values
* @post_clamp: Post-clamp array values
*/
struct sde_drm_csc_v1 {
int64_t ctm_coeff[SDE_CSC_MATRIX_COEFF_SIZE];
uint32_t pre_bias[SDE_CSC_BIAS_SIZE];
uint32_t post_bias[SDE_CSC_BIAS_SIZE];
uint32_t pre_clamp[SDE_CSC_CLAMP_SIZE];
uint32_t post_clamp[SDE_CSC_CLAMP_SIZE];
};
/**
* struct sde_drm_color - struct to store the color and alpha values
* @color_0: Color 0 value
* @color_1: Color 1 value
* @color_2: Color 2 value
* @color_3: Color 3 value
*/
struct sde_drm_color {
uint32_t color_0;
uint32_t color_1;
uint32_t color_2;
uint32_t color_3;
};
/* Total number of supported dim layers */
#define SDE_MAX_DIM_LAYERS 7
/* SDE_DRM_DIM_LAYER_CONFIG_FLAG - flags for Dim Layer */
/* Color fill inside of the rect, including border */
#define SDE_DRM_DIM_LAYER_INCLUSIVE 0x1
/* Color fill outside of the rect, excluding border */
#define SDE_DRM_DIM_LAYER_EXCLUSIVE 0x2
/**
* struct sde_drm_dim_layer - dim layer cfg struct
* @flags: Refer SDE_DRM_DIM_LAYER_CONFIG_FLAG for possible values
* @stage: Blending stage of the dim layer
* @color_fill: Color fill for dim layer
* @rect: Dim layer coordinates
*/
struct sde_drm_dim_layer_cfg {
uint32_t flags;
uint32_t stage;
struct sde_drm_color color_fill;
struct drm_clip_rect rect;
};
/**
* struct sde_drm_dim_layer_v1 - version 1 of dim layer struct
* @num_layers: Numer of Dim Layers
* @layer: Dim layer user cfgs ptr for the num_layers
*/
struct sde_drm_dim_layer_v1 {
uint32_t num_layers;
struct sde_drm_dim_layer_cfg layer_cfg[SDE_MAX_DIM_LAYERS];
};
/* Writeback Config version definition */
#define SDE_DRM_WB_CFG 0x1
/* SDE_DRM_WB_CONFIG_FLAGS - Writeback configuration flags */
#define SDE_DRM_WB_CFG_FLAGS_CONNECTED (1<<0)
/**
* struct sde_drm_wb_cfg - Writeback configuration structure
* @flags: see DRM_MSM_WB_CONFIG_FLAGS
* @connector_id: writeback connector identifier
* @count_modes: Count of modes in modes_ptr
* @modes: Pointer to struct drm_mode_modeinfo
*/
struct sde_drm_wb_cfg {
uint32_t flags;
uint32_t connector_id;
uint32_t count_modes;
uint64_t modes;
};
#define SDE_MAX_ROI_V1 4
/**
* struct sde_drm_roi_v1 - list of regions of interest for a drm object
* @num_rects: number of valid rectangles in the roi array
* @roi: list of roi rectangles
*/
struct sde_drm_roi_v1 {
uint32_t num_rects;
struct drm_clip_rect roi[SDE_MAX_ROI_V1];
};
/**
* Define extended power modes supported by the SDE connectors.
*/
#define SDE_MODE_DPMS_ON 0
#define SDE_MODE_DPMS_LP1 1
#define SDE_MODE_DPMS_LP2 2
#define SDE_MODE_DPMS_STANDBY 3
#define SDE_MODE_DPMS_SUSPEND 4
#define SDE_MODE_DPMS_OFF 5
/**
* sde recovery events for notifying client
*/
#define SDE_RECOVERY_SUCCESS 0
#define SDE_RECOVERY_CAPTURE 1
#define SDE_RECOVERY_HARD_RESET 2
/*
* Colorimetry Data Block values
* These bit nums are defined as per the CTA spec
* and indicate the colorspaces supported by the sink
*/
#define DRM_EDID_CLRMETRY_xvYCC_601 (1 << 0)
#define DRM_EDID_CLRMETRY_xvYCC_709 (1 << 1)
#define DRM_EDID_CLRMETRY_sYCC_601 (1 << 2)
#define DRM_EDID_CLRMETRY_ADOBE_YCC_601 (1 << 3)
#define DRM_EDID_CLRMETRY_ADOBE_RGB (1 << 4)
#define DRM_EDID_CLRMETRY_BT2020_CYCC (1 << 5)
#define DRM_EDID_CLRMETRY_BT2020_YCC (1 << 6)
#define DRM_EDID_CLRMETRY_BT2020_RGB (1 << 7)
#define DRM_EDID_CLRMETRY_DCI_P3 (1 << 15)
/*
* HDR Metadata
* These are defined as per EDID spec and shall be used by the sink
* to set the HDR metadata for playback from userspace.
*/
#define HDR_PRIMARIES_COUNT 3
/* HDR EOTF */
#define HDR_EOTF_SDR_LUM_RANGE 0x0
#define HDR_EOTF_HDR_LUM_RANGE 0x1
#define HDR_EOTF_SMTPE_ST2084 0x2
#define HDR_EOTF_HLG 0x3
#define DRM_MSM_EXT_HDR_METADATA
#define DRM_MSM_EXT_HDR_PLUS_METADATA
struct drm_msm_ext_hdr_metadata {
__u32 hdr_state; /* HDR state */
__u32 eotf; /* electro optical transfer function */
__u32 hdr_supported; /* HDR supported */
__u32 display_primaries_x[HDR_PRIMARIES_COUNT]; /* Primaries x */
__u32 display_primaries_y[HDR_PRIMARIES_COUNT]; /* Primaries y */
__u32 white_point_x; /* white_point_x */
__u32 white_point_y; /* white_point_y */
__u32 max_luminance; /* Max luminance */
__u32 min_luminance; /* Min Luminance */
__u32 max_content_light_level; /* max content light level */
__u32 max_average_light_level; /* max average light level */
__u64 hdr_plus_payload; /* user pointer to dynamic HDR payload */
__u32 hdr_plus_payload_size;/* size of dynamic HDR payload data */
};
/**
* HDR sink properties
* These are defined as per EDID spec and shall be used by the userspace
* to determine the HDR properties to be set to the sink.
*/
#define DRM_MSM_EXT_HDR_PROPERTIES
#define DRM_MSM_EXT_HDR_PLUS_PROPERTIES
struct drm_msm_ext_hdr_properties {
__u8 hdr_metadata_type_one; /* static metadata type one */
__u32 hdr_supported; /* HDR supported */
__u32 hdr_eotf; /* electro optical transfer function */
__u32 hdr_max_luminance; /* Max luminance */
__u32 hdr_avg_luminance; /* Avg luminance */
__u32 hdr_min_luminance; /* Min Luminance */
__u32 hdr_plus_supported; /* HDR10+ supported */
};
/* HDR WRGB x and y index */
#define DISPLAY_PRIMARIES_WX 0
#define DISPLAY_PRIMARIES_WY 1
#define DISPLAY_PRIMARIES_RX 2
#define DISPLAY_PRIMARIES_RY 3
#define DISPLAY_PRIMARIES_GX 4
#define DISPLAY_PRIMARIES_GY 5
#define DISPLAY_PRIMARIES_BX 6
#define DISPLAY_PRIMARIES_BY 7
#define DISPLAY_PRIMARIES_MAX 8
struct drm_panel_hdr_properties {
__u32 hdr_enabled;
/* WRGB X and y values arrayed in format */
/* [WX, WY, RX, RY, GX, GY, BX, BY] */
__u32 display_primaries[DISPLAY_PRIMARIES_MAX];
/* peak brightness supported by panel */
__u32 peak_brightness;
/* Blackness level supported by panel */
__u32 blackness_level;
};
/**
* struct drm_msm_event_req - Payload to event enable/disable ioctls.
* @object_id: DRM object id. e.g.: for crtc pass crtc id.
* @object_type: DRM object type. e.g.: for crtc set it to DRM_MODE_OBJECT_CRTC.
* @event: Event for which notification is being enabled/disabled.
* e.g.: for Histogram set - DRM_EVENT_HISTOGRAM.
* @client_context: Opaque pointer that will be returned during event response
* notification.
* @index: Object index(e.g.: crtc index), optional for user-space to set.
* Driver will override value based on object_id and object_type.
*/
struct drm_msm_event_req {
__u32 object_id;
__u32 object_type;
__u32 event;
__u64 client_context;
__u32 index;
};
/**
* struct drm_msm_event_resp - payload returned when read is called for
* custom notifications.
* @base: Event type and length of complete notification payload.
* @info: Contains information about DRM that which raised this event.
* @data: Custom payload that driver returns for event type.
* size of data = base.length - (sizeof(base) + sizeof(info))
*/
struct drm_msm_event_resp {
struct drm_event base;
struct drm_msm_event_req info;
__u8 data[];
};
/**
* struct drm_msm_power_ctrl: Payload to enable/disable the power vote
* @enable: enable/disable the power vote
* @flags: operation control flags, for future use
*/
struct drm_msm_power_ctrl {
__u32 enable;
__u32 flags;
};
#define DRM_SDE_WB_CONFIG 0x40
#define DRM_MSM_REGISTER_EVENT 0x41
#define DRM_MSM_DEREGISTER_EVENT 0x42
#define DRM_MSM_RMFB2 0x43
#define DRM_MSM_POWER_CTRL 0x44
/* sde custom events */
#define DRM_EVENT_HISTOGRAM 0x80000000
#define DRM_EVENT_AD_BACKLIGHT 0x80000001
#define DRM_EVENT_CRTC_POWER 0x80000002
#define DRM_EVENT_SYS_BACKLIGHT 0x80000003
#define DRM_EVENT_SDE_POWER 0x80000004
#define DRM_EVENT_IDLE_NOTIFY 0x80000005
#define DRM_EVENT_PANEL_DEAD 0x80000006 /* ESD event */
#define DRM_EVENT_SDE_HW_RECOVERY 0X80000007
#define DRM_EVENT_LTM_HIST 0X80000008
#define DRM_EVENT_LTM_WB_PB 0X80000009
#define DRM_EVENT_LTM_OFF 0X8000000A
#define DRM_IOCTL_SDE_WB_CONFIG \
DRM_IOW((DRM_COMMAND_BASE + DRM_SDE_WB_CONFIG), struct sde_drm_wb_cfg)
#define DRM_IOCTL_MSM_REGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + \
DRM_MSM_REGISTER_EVENT), struct drm_msm_event_req)
#define DRM_IOCTL_MSM_DEREGISTER_EVENT DRM_IOW((DRM_COMMAND_BASE + \
DRM_MSM_DEREGISTER_EVENT), struct drm_msm_event_req)
#define DRM_IOCTL_MSM_RMFB2 DRM_IOW((DRM_COMMAND_BASE + \
DRM_MSM_RMFB2), unsigned int)
#define DRM_IOCTL_MSM_POWER_CTRL DRM_IOW((DRM_COMMAND_BASE + \
DRM_MSM_POWER_CTRL), struct drm_msm_power_ctrl)
#if defined(__cplusplus)
}
#endif
#endif /* _SDE_DRM_H_ */

3
include/uapi/media/Kbuild Normal file
View File

@@ -0,0 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note
header-y += msm_sde_rotator.h

122
include/uapi/media/msm_sde_rotator.h Normal file
View File

@@ -0,0 +1,122 @@
/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
/*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
*/
#ifndef __UAPI_MSM_SDE_ROTATOR_H__
#define __UAPI_MSM_SDE_ROTATOR_H__
#include <linux/videodev2.h>
#include <linux/types.h>
#include <linux/ioctl.h>
/* SDE Rotator pixel format definitions */
#define SDE_PIX_FMT_XRGB_8888 V4L2_PIX_FMT_XBGR32
#define SDE_PIX_FMT_ARGB_8888 V4L2_PIX_FMT_ABGR32
#define SDE_PIX_FMT_ABGR_8888 V4L2_PIX_FMT_SDE_ABGR_8888
#define SDE_PIX_FMT_RGBA_8888 V4L2_PIX_FMT_SDE_RGBA_8888
#define SDE_PIX_FMT_BGRA_8888 V4L2_PIX_FMT_ARGB32
#define SDE_PIX_FMT_RGBX_8888 V4L2_PIX_FMT_SDE_RGBX_8888
#define SDE_PIX_FMT_BGRX_8888 V4L2_PIX_FMT_XRGB32
#define SDE_PIX_FMT_XBGR_8888 V4L2_PIX_FMT_SDE_XBGR_8888
#define SDE_PIX_FMT_RGBA_5551 V4L2_PIX_FMT_SDE_RGBA_5551
#define SDE_PIX_FMT_ARGB_1555 V4L2_PIX_FMT_ARGB555
#define SDE_PIX_FMT_ABGR_1555 V4L2_PIX_FMT_SDE_ABGR_1555
#define SDE_PIX_FMT_BGRA_5551 V4L2_PIX_FMT_SDE_BGRA_5551
#define SDE_PIX_FMT_BGRX_5551 V4L2_PIX_FMT_SDE_BGRX_5551
#define SDE_PIX_FMT_RGBX_5551 V4L2_PIX_FMT_SDE_RGBX_5551
#define SDE_PIX_FMT_XBGR_1555 V4L2_PIX_FMT_SDE_XBGR_1555
#define SDE_PIX_FMT_XRGB_1555 V4L2_PIX_FMT_XRGB555
#define SDE_PIX_FMT_ARGB_4444 V4L2_PIX_FMT_ARGB444
#define SDE_PIX_FMT_RGBA_4444 V4L2_PIX_FMT_SDE_RGBA_4444
#define SDE_PIX_FMT_BGRA_4444 V4L2_PIX_FMT_SDE_BGRA_4444
#define SDE_PIX_FMT_ABGR_4444 V4L2_PIX_FMT_SDE_ABGR_4444
#define SDE_PIX_FMT_RGBX_4444 V4L2_PIX_FMT_SDE_RGBX_4444
#define SDE_PIX_FMT_XRGB_4444 V4L2_PIX_FMT_XRGB444
#define SDE_PIX_FMT_BGRX_4444 V4L2_PIX_FMT_SDE_BGRX_4444
#define SDE_PIX_FMT_XBGR_4444 V4L2_PIX_FMT_SDE_XBGR_4444
#define SDE_PIX_FMT_RGB_888 V4L2_PIX_FMT_RGB24
#define SDE_PIX_FMT_BGR_888 V4L2_PIX_FMT_BGR24
#define SDE_PIX_FMT_RGB_565 V4L2_PIX_FMT_RGB565
#define SDE_PIX_FMT_BGR_565 V4L2_PIX_FMT_SDE_BGR_565
#define SDE_PIX_FMT_Y_CB_CR_H2V2 V4L2_PIX_FMT_YUV420
#define SDE_PIX_FMT_Y_CR_CB_H2V2 V4L2_PIX_FMT_YVU420
#define SDE_PIX_FMT_Y_CR_CB_GH2V2 V4L2_PIX_FMT_SDE_Y_CR_CB_GH2V2
#define SDE_PIX_FMT_Y_CBCR_H2V2 V4L2_PIX_FMT_NV12
#define SDE_PIX_FMT_Y_CRCB_H2V2 V4L2_PIX_FMT_NV21
#define SDE_PIX_FMT_Y_CBCR_H1V2 V4L2_PIX_FMT_SDE_Y_CBCR_H1V2
#define SDE_PIX_FMT_Y_CRCB_H1V2 V4L2_PIX_FMT_SDE_Y_CRCB_H1V2
#define SDE_PIX_FMT_Y_CBCR_H2V1 V4L2_PIX_FMT_NV16
#define SDE_PIX_FMT_Y_CRCB_H2V1 V4L2_PIX_FMT_NV61
#define SDE_PIX_FMT_YCBYCR_H2V1 V4L2_PIX_FMT_YUYV
#define SDE_PIX_FMT_Y_CBCR_H2V2_VENUS V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_VENUS
#define SDE_PIX_FMT_Y_CRCB_H2V2_VENUS V4L2_PIX_FMT_SDE_Y_CRCB_H2V2_VENUS
#define SDE_PIX_FMT_RGBA_8888_UBWC V4L2_PIX_FMT_RGBA8888_UBWC
#define SDE_PIX_FMT_RGBX_8888_UBWC V4L2_PIX_FMT_SDE_RGBX_8888_UBWC
#define SDE_PIX_FMT_RGB_565_UBWC V4L2_PIX_FMT_SDE_RGB_565_UBWC
#define SDE_PIX_FMT_Y_CBCR_H2V2_UBWC V4L2_PIX_FMT_NV12_UBWC
#define SDE_PIX_FMT_RGBA_1010102 V4L2_PIX_FMT_SDE_RGBA_1010102
#define SDE_PIX_FMT_RGBX_1010102 V4L2_PIX_FMT_SDE_RGBX_1010102
#define SDE_PIX_FMT_ARGB_2101010 V4L2_PIX_FMT_SDE_ARGB_2101010
#define SDE_PIX_FMT_XRGB_2101010 V4L2_PIX_FMT_SDE_XRGB_2101010
#define SDE_PIX_FMT_BGRA_1010102 V4L2_PIX_FMT_SDE_BGRA_1010102
#define SDE_PIX_FMT_BGRX_1010102 V4L2_PIX_FMT_SDE_BGRX_1010102
#define SDE_PIX_FMT_ABGR_2101010 V4L2_PIX_FMT_SDE_ABGR_2101010
#define SDE_PIX_FMT_XBGR_2101010 V4L2_PIX_FMT_SDE_XBGR_2101010
#define SDE_PIX_FMT_RGBA_1010102_UBWC V4L2_PIX_FMT_SDE_RGBA_1010102_UBWC
#define SDE_PIX_FMT_RGBX_1010102_UBWC V4L2_PIX_FMT_SDE_RGBX_1010102_UBWC
#define SDE_PIX_FMT_Y_CBCR_H2V2_P010 V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_P010
#define SDE_PIX_FMT_Y_CBCR_H2V2_P010_VENUS \
V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_P010_VENUS
#define SDE_PIX_FMT_Y_CBCR_H2V2_TP10 V4L2_PIX_FMT_SDE_Y_CBCR_H2V2_TP10
#define SDE_PIX_FMT_Y_CBCR_H2V2_TP10_UBWC V4L2_PIX_FMT_NV12_TP10_UBWC
#define SDE_PIX_FMT_Y_CBCR_H2V2_P010_UBWC V4L2_PIX_FMT_NV12_P010_UBWC
/*
* struct msm_sde_rotator_fence - v4l2 buffer fence info
* @index: id number of the buffer
* @type: enum v4l2_buf_type; buffer type
* @fd: file descriptor of the fence associated with this buffer
*/
struct msm_sde_rotator_fence {
__u32 index;
__u32 type;
__s32 fd;
__u32 reserved[5];
};
/*
* struct msm_sde_rotator_comp_ratio - v4l2 buffer compression ratio
* @index: id number of the buffer
* @type: enum v4l2_buf_type; buffer type
* @numer: numerator of the ratio
* @denom: denominator of the ratio
*/
struct msm_sde_rotator_comp_ratio {
__u32 index;
__u32 type;
__u32 numer;
__u32 denom;
__u32 reserved[4];
};
/* SDE Rotator private ioctl ID */
#define VIDIOC_G_SDE_ROTATOR_FENCE \
_IOWR('V', BASE_VIDIOC_PRIVATE + 10, struct msm_sde_rotator_fence)
#define VIDIOC_S_SDE_ROTATOR_FENCE \
_IOWR('V', BASE_VIDIOC_PRIVATE + 11, struct msm_sde_rotator_fence)
#define VIDIOC_G_SDE_ROTATOR_COMP_RATIO \
_IOWR('V', BASE_VIDIOC_PRIVATE + 12, struct msm_sde_rotator_comp_ratio)
#define VIDIOC_S_SDE_ROTATOR_COMP_RATIO \
_IOWR('V', BASE_VIDIOC_PRIVATE + 13, struct msm_sde_rotator_comp_ratio)
/* SDE Rotator private control ID's */
#define V4L2_CID_SDE_ROTATOR_SECURE (V4L2_CID_USER_BASE + 0x1000)
/*
* This control Id indicates this context is associated with the
* secure camera.
*/
#define V4L2_CID_SDE_ROTATOR_SECURE_CAMERA (V4L2_CID_USER_BASE + 0x2000)
#endif /* __UAPI_MSM_SDE_ROTATOR_H__ */

2
msm/dsi/dsi_clk.h
View File

@@ -178,7 +178,6 @@ typedef int (*pre_clockon_cb)(void *priv,
* @c_clks[MAX_DSI_CTRL] array of core clock configurations
* @l_lp_clks[MAX_DSI_CTRL] array of low power(esc) clock configurations
* @l_hs_clks[MAX_DSI_CTRL] array of high speed clock configurations
* @bus_handle[MAX_DSI_CTRL] array of bus handles
* @ctrl_index[MAX_DSI_CTRL] array of DSI controller indexes mapped
* to core and link clock configurations
* @pre_clkoff_cb callback before clock is turned off
@@ -194,7 +193,6 @@ struct dsi_clk_info {
struct dsi_core_clk_info c_clks[MAX_DSI_CTRL];
struct dsi_link_lp_clk_info l_lp_clks[MAX_DSI_CTRL];
struct dsi_link_hs_clk_info l_hs_clks[MAX_DSI_CTRL];
u32 bus_handle[MAX_DSI_CTRL];
u32 ctrl_index[MAX_DSI_CTRL];
pre_clockoff_cb pre_clkoff_cb;
post_clockoff_cb post_clkoff_cb;

21
msm/dsi/dsi_clk_manager.c
View File

@@ -6,14 +6,12 @@
#include <linux/of.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/msm-bus.h>
#include <linux/pm_runtime.h>
#include "dsi_clk.h"
#include "dsi_defs.h"
struct dsi_core_clks {
struct dsi_core_clk_info clks;
u32 bus_handle;
};
struct dsi_link_clks {
@@ -265,19 +263,9 @@ int dsi_core_clk_start(struct dsi_core_clks *c_clks)
}
}
if (c_clks->bus_handle) {
rc = msm_bus_scale_client_update_request(c_clks->bus_handle, 1);
if (rc) {
DSI_ERR("bus scale client enable failed, rc=%d\n", rc);
goto error_disable_mmss_clk;
}
}
return rc;
error_disable_mmss_clk:
if (c_clks->clks.core_mmss_clk)
clk_disable_unprepare(c_clks->clks.core_mmss_clk);
error_disable_bus_clk:
if (c_clks->clks.bus_clk)
clk_disable_unprepare(c_clks->clks.bus_clk);
@@ -298,14 +286,6 @@ int dsi_core_clk_stop(struct dsi_core_clks *c_clks)
{
int rc = 0;
if (c_clks->bus_handle) {
rc = msm_bus_scale_client_update_request(c_clks->bus_handle, 0);
if (rc) {
DSI_ERR("bus scale client disable failed, rc=%d\n", rc);
return rc;
}
}
if (c_clks->clks.core_mmss_clk)
clk_disable_unprepare(c_clks->clks.core_mmss_clk);
@@ -1446,7 +1426,6 @@ void *dsi_display_clk_mngr_register(struct dsi_clk_info *info)
sizeof(struct dsi_link_hs_clk_info));
memcpy(&mngr->link_clks[i].lp_clks, &info->l_lp_clks[i],
sizeof(struct dsi_link_lp_clk_info));
mngr->core_clks[i].bus_handle = info->bus_handle[i];
mngr->ctrl_index[i] = info->ctrl_index[i];
}

47
msm/dsi/dsi_ctrl.c
View File

@@ -7,7 +7,6 @@
#include <linux/err.h>
#include <linux/regulator/consumer.h>
#include <linux/clk.h>
#include <linux/msm-bus.h>
#include <linux/of_irq.h>
#include <video/mipi_display.h>
@@ -812,43 +811,6 @@ error_digital:
return rc;
}
static int dsi_ctrl_axi_bus_client_init(struct platform_device *pdev,
struct dsi_ctrl *ctrl)
{
int rc = 0;
struct dsi_ctrl_bus_scale_info *bus = &ctrl->axi_bus_info;
bus->bus_scale_table = msm_bus_cl_get_pdata(pdev);
if (IS_ERR_OR_NULL(bus->bus_scale_table)) {
rc = PTR_ERR(bus->bus_scale_table);
DSI_CTRL_DEBUG(ctrl, "msm_bus_cl_get_pdata() failed, rc = %d\n",
rc);
bus->bus_scale_table = NULL;
return rc;
}
bus->bus_handle = msm_bus_scale_register_client(bus->bus_scale_table);
if (!bus->bus_handle) {
rc = -EINVAL;
DSI_CTRL_ERR(ctrl, "failed to register axi bus client\n");
}
return rc;
}
static int dsi_ctrl_axi_bus_client_deinit(struct dsi_ctrl *ctrl)
{
struct dsi_ctrl_bus_scale_info *bus = &ctrl->axi_bus_info;
if (bus->bus_handle) {
msm_bus_scale_unregister_client(bus->bus_handle);
bus->bus_handle = 0;
}
return 0;
}
static int dsi_ctrl_validate_panel_info(struct dsi_ctrl *dsi_ctrl,
struct dsi_host_config *config)
{
@@ -1928,11 +1890,6 @@ static int dsi_ctrl_dev_probe(struct platform_device *pdev)
goto fail_supplies;
}
rc = dsi_ctrl_axi_bus_client_init(pdev, dsi_ctrl);
if (rc)
DSI_CTRL_DEBUG(dsi_ctrl, "failed to init axi bus client, rc = %d\n",
rc);
item->ctrl = dsi_ctrl;
mutex_lock(&dsi_ctrl_list_lock);
@@ -1977,10 +1934,6 @@ static int dsi_ctrl_dev_remove(struct platform_device *pdev)
mutex_unlock(&dsi_ctrl_list_lock);
mutex_lock(&dsi_ctrl->ctrl_lock);
rc = dsi_ctrl_axi_bus_client_deinit(dsi_ctrl);
if (rc)
DSI_CTRL_ERR(dsi_ctrl, "failed to deinitialize axi bus client, rc = %d\n",
rc);
rc = dsi_ctrl_supplies_deinit(dsi_ctrl);
if (rc)

12
msm/dsi/dsi_ctrl.h
View File

@@ -136,16 +136,6 @@ struct dsi_ctrl_clk_info {
struct dsi_clk_link_set shadow_clks;
};
/**
* struct dsi_ctrl_bus_scale_info - Bus scale info for msm-bus bandwidth voting
* @bus_scale_table: Bus scale voting usecases.
* @bus_handle: Handle used for voting bandwidth.
*/
struct dsi_ctrl_bus_scale_info {
struct msm_bus_scale_pdata *bus_scale_table;
u32 bus_handle;
};
/**
* struct dsi_ctrl_state_info - current driver state information
* @power_state: Status of power states on DSI controller.
@@ -208,7 +198,6 @@ struct dsi_ctrl_interrupts {
* @clk_info: Clock information.
* @clk_freq: DSi Link clock frequency information.
* @pwr_info: Power information.
* @axi_bus_info: AXI bus information.
* @host_config: Current host configuration.
* @mode_bounds: Boundaries of the default mode ROI.
* Origin is at top left of all CTRLs.
@@ -263,7 +252,6 @@ struct dsi_ctrl {
struct dsi_ctrl_clk_info clk_info;
struct link_clk_freq clk_freq;
struct dsi_ctrl_power_info pwr_info;
struct dsi_ctrl_bus_scale_info axi_bus_info;
struct dsi_host_config host_config;
struct dsi_rect mode_bounds;

2
msm/dsi/dsi_display.c
View File

@@ -4874,8 +4874,6 @@ static int dsi_display_bind(struct device *dev,
sizeof(struct dsi_link_lp_clk_info));
info.c_clks[i].drm = drm;
info.bus_handle[i] =
display_ctrl->ctrl->axi_bus_info.bus_handle;
info.ctrl_index[i] = display_ctrl->ctrl->cell_index;
}

1
msm/dsi/dsi_phy.c
View File

@@ -7,7 +7,6 @@
#include <linux/err.h>
#include <linux/regulator/consumer.h>
#include <linux/clk.h>
#include <linux/msm-bus.h>
#include <linux/list.h>
#include "msm_drv.h"

1
msm/msm_drv.h
View File

@@ -44,6 +44,7 @@
#include <drm/drm_plane_helper.h>
#include <drm/drm_fb_helper.h>
#include <drm/msm_drm.h>
#include <drm/sde_drm.h>
#include <drm/drm_gem.h>
#include "sde_power_handle.h"

1
msm/sde/sde_encoder.c
View File

@@ -19,6 +19,7 @@
#define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
#include <linux/kthread.h>
#include <linux/debugfs.h>
#include <linux/input.h>
#include <linux/seq_file.h>
#include <linux/sde_rsc.h>

1
msm/sde/sde_hw_catalog.h
View File

@@ -10,7 +10,6 @@
#include <linux/bug.h>
#include <linux/bitmap.h>
#include <linux/err.h>
#include <linux/msm-bus.h>
#include <linux/of_fdt.h>
#include <drm/drmP.h>
#include "sde_hw_mdss.h"

258
msm/sde_power_handle.c
View File

@@ -14,8 +14,6 @@
#include <linux/mutex.h>
#include <linux/of_platform.h>
#include <linux/msm-bus.h>
#include <linux/msm-bus-board.h>
#include <linux/sde_io_util.h>
#include <linux/sde_rsc.h>
@@ -23,6 +21,13 @@
#include "sde_trace.h"
#include "sde_dbg.h"
static const struct sde_power_bus_scaling_data sde_reg_bus_table[] = {
{0, 0},
{0, 76800},
{0, 150000},
{0, 300000},
};
static const char *data_bus_name[SDE_POWER_HANDLE_DBUS_ID_MAX] = {
[SDE_POWER_HANDLE_DBUS_ID_MNOC] = "qcom,sde-data-bus",
[SDE_POWER_HANDLE_DBUS_ID_LLCC] = "qcom,sde-llcc-bus",
@@ -277,68 +282,50 @@ clk_err:
return rc;
}
#ifdef CONFIG_QCOM_BUS_SCALING
#define MAX_AXI_PORT_COUNT 3
static int _sde_power_data_bus_set_quota(
struct sde_power_data_bus_handle *pdbus,
u64 in_ab_quota, u64 in_ib_quota)
{
int new_uc_idx;
u64 ab_quota[MAX_AXI_PORT_COUNT] = {0, 0};
u64 ib_quota[MAX_AXI_PORT_COUNT] = {0, 0};
int rc;
int rc = 0, i = 0, j = 0;
if (pdbus->data_bus_hdl < 1) {
pr_err("invalid bus handle %d\n", pdbus->data_bus_hdl);
if (!pdbus->data_paths_cnt) {
pr_err("invalid data bus handle\n");
return -EINVAL;
}
if (!in_ab_quota && !in_ib_quota) {
new_uc_idx = 0;
} else {
int i;
struct msm_bus_vectors *vect = NULL;
struct msm_bus_scale_pdata *bw_table =
pdbus->data_bus_scale_table;
u32 total_data_paths_cnt = pdbus->data_paths_cnt;
pr_debug("ab=%llu ib=%llu\n", in_ab_quota, in_ib_quota);
if (!bw_table || !total_data_paths_cnt ||
total_data_paths_cnt > MAX_AXI_PORT_COUNT) {
pr_err("invalid input\n");
return -EINVAL;
}
ab_quota[0] = div_u64(in_ab_quota, total_data_paths_cnt);
ib_quota[0] = div_u64(in_ib_quota, total_data_paths_cnt);
for (i = 1; i < total_data_paths_cnt; i++) {
ab_quota[i] = ab_quota[0];
ib_quota[i] = ib_quota[0];
}
new_uc_idx = (pdbus->curr_bw_uc_idx %
(bw_table->num_usecases - 1)) + 1;
for (i = 0; i < total_data_paths_cnt; i++) {
vect = &bw_table->usecase[new_uc_idx].vectors[i];
vect->ab = ab_quota[i];
vect->ib = ib_quota[i];
pr_debug(
"%s uc_idx=%d idx=%d ab=%llu ib=%llu\n",
bw_table->name, new_uc_idx, i, vect->ab,
vect->ib);
}
}
pdbus->curr_bw_uc_idx = new_uc_idx;
in_ab_quota = div_u64(in_ab_quota, pdbus->data_paths_cnt);
SDE_ATRACE_BEGIN("msm_bus_scale_req");
rc = msm_bus_scale_client_update_request(pdbus->data_bus_hdl,
new_uc_idx);
for (i = 0; i < pdbus->data_paths_cnt; i++) {
if (pdbus->data_bus_hdl[i]) {
rc = icc_set_bw(pdbus->data_bus_hdl[i],
in_ab_quota, in_ib_quota);
if (rc)
goto err;
}
}
pdbus->curr_val.ab = in_ab_quota;
pdbus->curr_val.ib = in_ib_quota;
SDE_ATRACE_END("msm_bus_scale_req");
return rc;
err:
for (j = 0; j < i; j++)
if (pdbus->data_bus_hdl[j])
icc_set_bw(pdbus->data_bus_hdl[j],
pdbus->curr_val.ab,
pdbus->curr_val.ib);
SDE_ATRACE_END("msm_bus_scale_req");
pr_err("failed to set data bus vote ab=%llu ib=%llu rc=%d\n",
rc, in_ab_quota, in_ib_quota);
return rc;
}
@@ -356,7 +343,7 @@ int sde_power_data_bus_set_quota(struct sde_power_handle *phandle,
trace_sde_perf_update_bus(bus_id, ab_quota, ib_quota);
if (phandle->data_bus_handle[bus_id].data_bus_hdl)
if (phandle->data_bus_handle[bus_id].data_paths_cnt > 0)
rc = _sde_power_data_bus_set_quota(
&phandle->data_bus_handle[bus_id], ab_quota, ib_quota);
@@ -368,96 +355,96 @@ int sde_power_data_bus_set_quota(struct sde_power_handle *phandle,
static void sde_power_data_bus_unregister(
struct sde_power_data_bus_handle *pdbus)
{
if (pdbus->data_bus_hdl) {
msm_bus_scale_unregister_client(pdbus->data_bus_hdl);
pdbus->data_bus_hdl = 0;
int i = 0;
for (i = 0; i < pdbus->data_paths_cnt; i++) {
if (pdbus->data_bus_hdl[i]) {
icc_put(pdbus->data_bus_hdl[i]);
pdbus->data_bus_hdl[i] = NULL;
}
}
}
static int sde_power_data_bus_parse(struct platform_device *pdev,
struct sde_power_data_bus_handle *pdbus, const char *name)
{
struct device_node *node;
int rc = 0;
int paths;
char bus_name[32];
int i = 0, ret = 0;
node = of_get_child_by_name(pdev->dev.of_node, name);
if (!node)
goto end;
for (i = 0; i < DATA_BUS_PATH_MAX; i++) {
snprintf(bus_name, sizeof(bus_name), "%s%d", name, i);
ret = of_property_match_string(pdev->dev.of_node,
"interconnect-names", bus_name);
if (ret < 0) {
if (!pdbus->data_paths_cnt) {
pr_debug("sde: bus %s dt node missing\n", bus_name);
return 0;
} else
goto end;
} else
pdbus->data_bus_hdl[i] = of_icc_get(&pdev->dev, bus_name);
rc = of_property_read_u32(node, "qcom,msm-bus,num-paths", &paths);
if (rc) {
pr_err("Error. qcom,msm-bus,num-paths not found\n");
return rc;
if (IS_ERR_OR_NULL(pdbus->data_bus_hdl[i])) {
pr_debug("icc get path failed for %s\n", bus_name);
break;
}
pdbus->data_paths_cnt++;
}
pdbus->data_paths_cnt = paths;
pdbus->data_bus_scale_table = msm_bus_pdata_from_node(pdev, node);
if (IS_ERR_OR_NULL(pdbus->data_bus_scale_table)) {
pr_err("reg bus handle parsing failed\n");
rc = PTR_ERR(pdbus->data_bus_scale_table);
if (!pdbus->data_bus_scale_table)
rc = -EINVAL;
goto end;
if (!pdbus->data_paths_cnt) {
pr_err("get none data bus path for %s\n", name);
return -EINVAL;
}
pdbus->data_bus_hdl = msm_bus_scale_register_client(
pdbus->data_bus_scale_table);
if (!pdbus->data_bus_hdl) {
pr_err("data_bus_client register failed\n");
rc = -EINVAL;
goto end;
}
pr_debug("register %s data_bus_hdl=%x\n", name, pdbus->data_bus_hdl);
end:
return rc;
if (of_find_property(pdev->dev.of_node,
"qcom,msm-bus,active-only", NULL)) {
pdbus->bus_active_only = true;
for (i = 0; i < pdbus->data_paths_cnt; i++) {
icc_set_tag(pdbus->data_bus_hdl[i],
QCOM_ICC_TAG_ACTIVE_ONLY);
}
}
pr_debug("register %s data_bus success, path number=%d\n",
name, pdbus->data_paths_cnt);
return 0;
}
static int sde_power_reg_bus_parse(struct platform_device *pdev,
struct sde_power_handle *phandle)
{
struct device_node *node;
struct msm_bus_scale_pdata *bus_scale_table;
int rc = 0;
node = of_get_child_by_name(pdev->dev.of_node, "qcom,sde-reg-bus");
if (node) {
bus_scale_table = msm_bus_pdata_from_node(pdev, node);
if (IS_ERR_OR_NULL(bus_scale_table)) {
pr_err("reg bus handle parsing failed\n");
rc = PTR_ERR(bus_scale_table);
if (!bus_scale_table)
rc = -EINVAL;
goto end;
}
phandle->reg_bus_hdl = msm_bus_scale_register_client(
bus_scale_table);
if (!phandle->reg_bus_hdl) {
pr_err("reg_bus_client register failed\n");
rc = -EINVAL;
goto end;
}
pr_debug("register reg_bus_hdl=%x\n", phandle->reg_bus_hdl);
phandle->reg_bus_hdl = of_icc_get(&pdev->dev, "qcom,sde-reg-bus");
if (IS_ERR_OR_NULL(phandle->reg_bus_hdl)) {
pr_err("reg bus handle parsing failed\n");
phandle->reg_bus_hdl = NULL;
rc = -EINVAL;
} else {
pr_debug("reg_bus_hdl parsing success\n");
}
end:
return rc;
}
static void sde_power_reg_bus_unregister(u32 reg_bus_hdl)
static void sde_power_reg_bus_unregister(struct icc_path *reg_bus_hdl)
{
if (reg_bus_hdl)
msm_bus_scale_unregister_client(reg_bus_hdl);
icc_put(reg_bus_hdl);
}
static int sde_power_reg_bus_update(u32 reg_bus_hdl, u32 usecase_ndx)
static int sde_power_reg_bus_update(struct icc_path *reg_bus_hdl,
u32 usecase_ndx)
{
int rc = 0;
if (reg_bus_hdl) {
SDE_ATRACE_BEGIN("msm_bus_scale_req");
rc = msm_bus_scale_client_update_request(reg_bus_hdl,
usecase_ndx);
rc = icc_set_bw(reg_bus_hdl,
sde_reg_bus_table[usecase_ndx].ab,
sde_reg_bus_table[usecase_ndx].ib);
SDE_ATRACE_END("msm_bus_scale_req");
}
@@ -466,52 +453,6 @@ static int sde_power_reg_bus_update(u32 reg_bus_hdl, u32 usecase_ndx)
return rc;
}
#else
static int _sde_power_data_bus_set_quota(
struct sde_power_data_bus_handle *pdbus,
u64 in_ab_quota, u64 in_ib_quota)
{
return 0;
}
static int sde_power_data_bus_parse(struct platform_device *pdev,
struct sde_power_data_bus_handle *pdbus, const char *name)
{
return 0;
}
static void sde_power_data_bus_unregister(
struct sde_power_data_bus_handle *pdbus)
{
}
int sde_power_data_bus_set_quota(struct sde_power_handle *phandle,
u32 bus_id, u64 ab_quota, u64 ib_quota)
{
return 0;
}
static int sde_power_reg_bus_parse(struct platform_device *pdev,
struct sde_power_handle *phandle)
{
return 0;
}
static void sde_power_reg_bus_unregister(u32 reg_bus_hdl)
{
}
static int sde_power_reg_bus_update(u32 reg_bus_hdl, u32 usecase_ndx)
{
return 0;
}
int sde_power_data_bus_state_update(struct sde_power_handle *phandle,
bool enable)
{
return 0;
}
#endif
int sde_power_resource_init(struct platform_device *pdev,
struct sde_power_handle *phandle)
@@ -675,6 +616,13 @@ int sde_power_scale_reg_bus(struct sde_power_handle *phandle,
usecase_ndx);
if (rc)
pr_err("failed to set reg bus vote rc=%d\n", rc);
else {
phandle->reg_bus_curr_val.ab =
sde_reg_bus_table[usecase_ndx].ab;
phandle->reg_bus_curr_val.ib =
sde_reg_bus_table[usecase_ndx].ib;
phandle->current_usecase_ndx = usecase_ndx;
}
if (!skip_lock)
mutex_unlock(&phandle->phandle_lock);
@@ -723,7 +671,7 @@ int sde_power_resource_enable(struct sde_power_handle *phandle, bool enable)
SDE_POWER_EVENT_PRE_ENABLE);
for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX &&
phandle->data_bus_handle[i].data_bus_hdl; i++) {
phandle->data_bus_handle[i].data_paths_cnt > 0; i++) {
rc = _sde_power_data_bus_set_quota(
&phandle->data_bus_handle[i],
SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
@@ -777,7 +725,7 @@ int sde_power_resource_enable(struct sde_power_handle *phandle, bool enable)
msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, enable);
for (i = SDE_POWER_HANDLE_DBUS_ID_MAX - 1; i >= 0; i--)
if (phandle->data_bus_handle[i].data_bus_hdl)
if (phandle->data_bus_handle[i].data_paths_cnt > 0)
_sde_power_data_bus_set_quota(
&phandle->data_bus_handle[i],
SDE_POWER_HANDLE_DISABLE_BUS_AB_QUOTA,
@@ -799,7 +747,7 @@ rsc_err:
reg_bus_hdl_err:
msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, 0);
vreg_err:
for (i-- ; i >= 0 && phandle->data_bus_handle[i].data_bus_hdl; i--)
for (i-- ; i >= 0 && phandle->data_bus_handle[i].data_paths_cnt > 0; i--)
_sde_power_data_bus_set_quota(
&phandle->data_bus_handle[i],
SDE_POWER_HANDLE_DISABLE_BUS_AB_QUOTA,

53
msm/sde_power_handle.h
View File

@@ -18,6 +18,7 @@
#define SDE_POWER_HANDLE_CONT_SPLASH_BUS_AB_QUOTA 3000000000ULL
#include <linux/sde_io_util.h>
#include <linux/interconnect.h>
#include <soc/qcom/cx_ipeak.h>
/* event will be triggered before power handler disable */
@@ -31,6 +32,23 @@
/* event will be triggered after power handler enable */
#define SDE_POWER_EVENT_POST_ENABLE 0x8
#define DATA_BUS_PATH_MAX 0x2
/*
* The AMC bucket denotes constraints that are applied to hardware when
* icc_set_bw() completes, whereas the WAKE and SLEEP constraints are applied
* when the execution environment transitions between active and low power mode.
*/
#define QCOM_ICC_BUCKET_AMC 0
#define QCOM_ICC_BUCKET_WAKE 1
#define QCOM_ICC_BUCKET_SLEEP 2
#define QCOM_ICC_NUM_BUCKETS 3
#define QCOM_ICC_TAG_AMC BIT(QCOM_ICC_BUCKET_AMC)
#define QCOM_ICC_TAG_WAKE BIT(QCOM_ICC_BUCKET_WAKE)
#define QCOM_ICC_TAG_SLEEP BIT(QCOM_ICC_BUCKET_SLEEP)
#define QCOM_ICC_TAG_ACTIVE_ONLY (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE)
#define QCOM_ICC_TAG_ALWAYS (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE |\
QCOM_ICC_TAG_SLEEP)
/**
* mdss_bus_vote_type: register bus vote type
@@ -73,30 +91,27 @@ enum SDE_POWER_HANDLE_DBUS_ID {
SDE_POWER_HANDLE_DBUS_ID_MAX,
};
/**
* struct sde_power_bus_scaling_data: struct for bus setting
* @ab: average bandwidth in kilobytes per second
* @ib: peak bandwidth in kilobytes per second
*/
struct sde_power_bus_scaling_data {
uint64_t ab; /* Arbitrated bandwidth */
uint64_t ib; /* Instantaneous bandwidth */
};
/**
* struct sde_power_data_handle: power handle struct for data bus
* @data_bus_scale_table: pointer to bus scaling table
* @data_bus_hdl: current data bus handle
* @curr_val : save the current bus value
* @data_paths_cnt: number of rt data path ports
* @curr_bw_uc_idx: current use case index of data bus
* @ao_bw_uc_idx: active only use case index of data bus
* @ab_rt: realtime ab quota
* @ib_rt: realtime ib quota
* @ab_nrt: non-realtime ab quota
* @ib_nrt: non-realtime ib quota
* @enable: true if bus is enabled
*/
struct sde_power_data_bus_handle {
struct msm_bus_scale_pdata *data_bus_scale_table;
u32 data_bus_hdl;
struct icc_path *data_bus_hdl[DATA_BUS_PATH_MAX];
struct sde_power_bus_scaling_data curr_val;
u32 data_paths_cnt;
u32 curr_bw_uc_idx;
u32 ao_bw_uc_idx;
u64 ab_rt;
u64 ib_rt;
u64 ab_nrt;
u64 ib_nrt;
bool enable;
bool bus_active_only;
};
/*
@@ -124,6 +139,7 @@ struct sde_power_event {
* @dev: pointer to device structure
* @usecase_ndx: current usecase index
* @reg_bus_hdl: current register bus handle
* @reg_bus_curr_val: save currecnt reg bus value
* @data_bus_handle: context structure for data bus control
* @event_list: current power handle event list
* @rsc_client: sde rsc client pointer
@@ -135,7 +151,8 @@ struct sde_power_handle {
struct mutex phandle_lock;
struct device *dev;
u32 current_usecase_ndx;
u32 reg_bus_hdl;
struct icc_path *reg_bus_hdl;
struct sde_power_bus_scaling_data reg_bus_curr_val;
struct sde_power_data_bus_handle data_bus_handle
[SDE_POWER_HANDLE_DBUS_ID_MAX];
struct list_head event_list;

37
msm/sde_rsc.c
View File

@@ -15,7 +15,6 @@
#include <linux/mutex.h>
#include <linux/of_platform.h>
#include <linux/module.h>
#include <linux/msm-bus.h>
#include <soc/qcom/rpmh.h>
#include <drm/drmP.h>
@@ -64,6 +63,21 @@
static struct sde_rsc_priv *rsc_prv_list[MAX_RSC_COUNT];
static struct device *rpmh_dev[MAX_RSC_COUNT];
static void sde_rsc_set_data_bus_mode(struct sde_power_handle *phandle, u32 tag)
{
int i = 0, j = 0;
for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++) {
if (!phandle->data_bus_handle[i].bus_active_only)
continue;
for (j = 0; j < phandle->data_bus_handle[i].data_paths_cnt; j++)
icc_set_tag(phandle->data_bus_handle[i].data_bus_hdl[j],
tag);
}
}
/**
* sde_rsc_client_create() - create the client for sde rsc.
* Different displays like DSI, HDMI, DP, WB, etc should call this
@@ -523,8 +537,11 @@ static int sde_rsc_switch_to_cmd(struct sde_rsc_priv *rsc,
if (rsc->hw_ops.state_update) {
rc = rsc->hw_ops.state_update(rsc, SDE_RSC_CMD_STATE);
if (!rc)
if (!rc) {
rpmh_mode_solver_set(rsc->rpmh_dev, true);
sde_rsc_set_data_bus_mode(&rsc->phandle,
QCOM_ICC_TAG_WAKE);
}
}
vsync_wait:
@@ -574,8 +591,11 @@ static int sde_rsc_switch_to_clk(struct sde_rsc_priv *rsc,
if (rsc->hw_ops.state_update) {
rc = rsc->hw_ops.state_update(rsc, SDE_RSC_CLK_STATE);
if (!rc)
if (!rc) {
rpmh_mode_solver_set(rsc->rpmh_dev, false);
sde_rsc_set_data_bus_mode(&rsc->phandle,
QCOM_ICC_TAG_AMC);
}
}
/* indicate wait for vsync for cmd/vid to clk state switch */
@@ -661,9 +681,13 @@ static int sde_rsc_switch_to_vid(struct sde_rsc_priv *rsc,
if (rsc->hw_ops.state_update) {
rc = rsc->hw_ops.state_update(rsc, SDE_RSC_VID_STATE);
if (!rc)
if (!rc) {
rpmh_mode_solver_set(rsc->rpmh_dev,
rsc->version == SDE_RSC_REV_3 ? true : false);
sde_rsc_set_data_bus_mode(&rsc->phandle,
rsc->version == SDE_RSC_REV_3 ?
QCOM_ICC_TAG_WAKE : QCOM_ICC_TAG_AMC);
}
}
vsync_wait:
@@ -737,8 +761,11 @@ static int sde_rsc_switch_to_idle(struct sde_rsc_priv *rsc,
rc = CLK_MODE_SWITCH_SUCCESS;
} else if (rsc->hw_ops.state_update) {
rc = rsc->hw_ops.state_update(rsc, SDE_RSC_IDLE_STATE);
if (!rc)
if (!rc) {
rpmh_mode_solver_set(rsc->rpmh_dev, true);
sde_rsc_set_data_bus_mode(&rsc->phandle,
QCOM_ICC_TAG_WAKE);
}
}
return rc;

106
rotator/sde_rotator_base.c
View File

@@ -14,8 +14,6 @@
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/msm-bus.h>
#include <linux/msm-bus-board.h>
#include <linux/regulator/consumer.h>
#define CREATE_TRACE_POINTS
@@ -26,6 +24,13 @@
#include "sde_rotator_dev.h"
#include "sde_rotator_vbif.h"
static const struct sde_rot_bus_data sde_rot_reg_bus_table[] = {
{0, 0},
{0, 76800},
{0, 150000},
{0, 300000},
};
static inline u64 fudge_factor(u64 val, u32 numer, u32 denom)
{
u64 result = (val * (u64)numer);
@@ -51,6 +56,11 @@ static inline bool validate_comp_ratio(struct sde_mult_factor *factor)
return factor->numer && factor->denom;
}
const struct sde_rot_bus_data *sde_get_rot_reg_bus_value(u32 usecase_ndx)
{
return &sde_rot_reg_bus_table[usecase_ndx];
}
u32 sde_apply_comp_ratio_factor(u32 quota,
struct sde_mdp_format_params *fmt,
struct sde_mult_factor *factor)
@@ -471,6 +481,7 @@ int sde_update_reg_bus_vote(struct reg_bus_client *bus_client, u32 usecase_ndx)
int ret = 0;
bool changed = false;
u32 max_usecase_ndx = VOTE_INDEX_DISABLE;
const struct sde_rot_bus_data *reg_bus_value = NULL;
struct reg_bus_client *client, *temp_client;
struct sde_rot_data_type *sde_res = sde_rot_get_mdata();
@@ -487,19 +498,27 @@ int sde_update_reg_bus_vote(struct reg_bus_client *bus_client, u32 usecase_ndx)
max_usecase_ndx = client->usecase_ndx;
}
if (sde_res->reg_bus_usecase_ndx != max_usecase_ndx) {
if (sde_res->reg_bus_usecase_ndx != max_usecase_ndx)
changed = true;
sde_res->reg_bus_usecase_ndx = max_usecase_ndx;
}
SDEROT_DBG(
"%pS: changed=%d current idx=%d request client %s id:%u idx:%d\n",
__builtin_return_address(0), changed, max_usecase_ndx,
bus_client->name, bus_client->id, usecase_ndx);
if (changed)
ret = msm_bus_scale_client_update_request(sde_res->reg_bus_hdl,
max_usecase_ndx);
if (changed) {
reg_bus_value = sde_get_rot_reg_bus_value(max_usecase_ndx);
ret = icc_set_bw(sde_res->reg_bus_hdl, reg_bus_value->ab,
reg_bus_value->ib);
}
if (ret) {
pr_err("rotator: reg_bus_hdl set failed ab=%llu, ib=%llu\n",
reg_bus_value->ab, reg_bus_value->ib);
if (sde_res->reg_bus_usecase_ndx == VOTE_INDEX_DISABLE)
pr_err("rotator: reg_bus_hdl was disabled\n");
} else {
sde_res->reg_bus_usecase_ndx = max_usecase_ndx;
}
mutex_unlock(&sde_res->reg_bus_lock);
return ret;
}
@@ -820,74 +839,33 @@ static void sde_mdp_destroy_dt_misc(struct platform_device *pdev,
mdata->vbif_nrt_qos = NULL;
}
#define MDP_REG_BUS_VECTOR_ENTRY(ab_val, ib_val) \
{ \
.src = MSM_BUS_MASTER_AMPSS_M0, \
.dst = MSM_BUS_SLAVE_DISPLAY_CFG, \
.ab = (ab_val), \
.ib = (ib_val), \
}
#define BUS_VOTE_19_MHZ 153600000
#define BUS_VOTE_40_MHZ 320000000
#define BUS_VOTE_80_MHZ 640000000
#ifdef CONFIG_QCOM_BUS_SCALING
static struct msm_bus_vectors mdp_reg_bus_vectors[] = {
MDP_REG_BUS_VECTOR_ENTRY(0, 0),
MDP_REG_BUS_VECTOR_ENTRY(0, BUS_VOTE_19_MHZ),
MDP_REG_BUS_VECTOR_ENTRY(0, BUS_VOTE_40_MHZ),
MDP_REG_BUS_VECTOR_ENTRY(0, BUS_VOTE_80_MHZ),
};
static struct msm_bus_paths mdp_reg_bus_usecases[ARRAY_SIZE(
mdp_reg_bus_vectors)];
static struct msm_bus_scale_pdata mdp_reg_bus_scale_table = {
.usecase = mdp_reg_bus_usecases,
.num_usecases = ARRAY_SIZE(mdp_reg_bus_usecases),
.name = "sde_reg",
.active_only = true,
};
static int sde_mdp_bus_scale_register(struct sde_rot_data_type *mdata)
{
struct msm_bus_scale_pdata *reg_bus_pdata;
int i;
int rc = 0;
if (!mdata->reg_bus_hdl) {
reg_bus_pdata = &mdp_reg_bus_scale_table;
for (i = 0; i < reg_bus_pdata->num_usecases; i++) {
mdp_reg_bus_usecases[i].num_paths = 1;
mdp_reg_bus_usecases[i].vectors =
&mdp_reg_bus_vectors[i];
}
mdata->reg_bus_hdl = of_icc_get(&mdata->pdev->dev, "qcom,sde-reg-bus");
mdata->reg_bus_hdl =
msm_bus_scale_register_client(reg_bus_pdata);
if (!mdata->reg_bus_hdl) {
/* Continue without reg_bus scaling */
SDEROT_WARN("reg_bus_client register failed\n");
} else
SDEROT_DBG("register reg_bus_hdl=%x\n",
mdata->reg_bus_hdl);
if (mdata->reg_bus_hdl == NULL) {
pr_err("rotator: reg bus dt node missing\n");
return 0;
} else if (IS_ERR(mdata->reg_bus_hdl)) {
SDEROT_ERR("reg bus handle parsing failed\n");
mdata->reg_bus_hdl = NULL;
rc = -EINVAL;
} else {
SDEROT_DBG("rotator reg_bus_hdl parsing success\n");
}
return 0;
return rc;
}
#else
static inline int sde_mdp_bus_scale_register(struct sde_rot_data_type *mdata)
{
return 0;
}
#endif
static void sde_mdp_bus_scale_unregister(struct sde_rot_data_type *mdata)
{
SDEROT_DBG("unregister reg_bus_hdl=%x\n", mdata->reg_bus_hdl);
SDEROT_DBG("unregister reg_bus_hdl\n");
if (mdata->reg_bus_hdl) {
msm_bus_scale_unregister_client(mdata->reg_bus_hdl);
mdata->reg_bus_hdl = 0;
icc_put(mdata->reg_bus_hdl);
mdata->reg_bus_hdl = NULL;
}
}

20
rotator/sde_rotator_base.h
View File

@@ -13,6 +13,7 @@
#include <linux/regulator/consumer.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/interconnect.h>
#include "sde_rotator_hwio.h"
#include "sde_rotator_io_util.h"
@@ -90,9 +91,9 @@ struct sde_mdp_vbif_halt_params {
enum sde_bus_vote_type {
VOTE_INDEX_DISABLE,
VOTE_INDEX_19_MHZ,
VOTE_INDEX_40_MHZ,
VOTE_INDEX_80_MHZ,
VOTE_INDEX_76_MHZ,
VOTE_INDEX_150_MHZ,
VOTE_INDEX_300_MHZ,
VOTE_INDEX_MAX,
};
@@ -192,6 +193,16 @@ struct sde_smmu_client {
u32 sid;
};
/*
* struct sde_rot_bus_data: struct for bus setting
* @ab: average bandwidth in kilobytes per second
* @ib: peak bandwidth in kilobytes per second
*/
struct sde_rot_bus_data {
uint64_t ab; /* Arbitrated bandwidth */
uint64_t ib; /* Instantaneous bandwidth */
};
/*
* struct sde_rot_debug_bus: rotator debugbus header structure
* @wr_addr: write address for debugbus controller
@@ -251,7 +262,7 @@ struct sde_rot_data_type {
u32 rot_block_size;
/* register bus (AHB) */
u32 reg_bus_hdl;
struct icc_path *reg_bus_hdl;
u32 reg_bus_usecase_ndx;
struct list_head reg_bus_clist;
struct mutex reg_bus_lock;
@@ -320,6 +331,7 @@ void vbif_unlock(struct platform_device *parent_pdev);
void sde_mdp_halt_vbif_xin(struct sde_mdp_vbif_halt_params *params);
int sde_mdp_init_vbif(void);
const struct sde_rot_bus_data *sde_get_rot_reg_bus_value(u32 usecase_ndx);
#define SDE_VBIF_WRITE(mdata, offset, value) \
(sde_reg_w(&mdata->vbif_nrt_io, offset, value, 0))

306
rotator/sde_rotator_core.c
View File

@@ -13,8 +13,6 @@
#include <linux/of.h>
#include <linux/clk.h>
#include <linux/debugfs.h>
#include <linux/msm-bus.h>
#include <linux/msm-bus-board.h>
#include <linux/regulator/consumer.h>
#include <linux/dma-direction.h>
#include <soc/qcom/scm.h>
@@ -69,50 +67,20 @@
*/
#define ROT_MAX_HW_BLOCKS 2
#define SDE_REG_BUS_VECTOR_ENTRY(ab_val, ib_val) \
{ \
.src = MSM_BUS_MASTER_AMPSS_M0, \
.dst = MSM_BUS_SLAVE_DISPLAY_CFG, \
.ab = (ab_val), \
.ib = (ib_val), \
}
#define BUS_VOTE_19_MHZ 153600000
/* forward prototype */
static int sde_rotator_update_perf(struct sde_rot_mgr *mgr);
#ifdef CONFIG_QCOM_BUS_SCALING
static struct msm_bus_vectors rot_reg_bus_vectors[] = {
SDE_REG_BUS_VECTOR_ENTRY(0, 0),
SDE_REG_BUS_VECTOR_ENTRY(0, BUS_VOTE_19_MHZ),
};
static struct msm_bus_paths rot_reg_bus_usecases[ARRAY_SIZE(
rot_reg_bus_vectors)];
static struct msm_bus_scale_pdata rot_reg_bus_scale_table = {
.usecase = rot_reg_bus_usecases,
.num_usecases = ARRAY_SIZE(rot_reg_bus_usecases),
.name = "mdss_rot_reg",
.active_only = 1,
};
static int sde_rotator_bus_scale_set_quota(struct sde_rot_bus_data_type *bus,
u64 quota)
{
int new_uc_idx;
int ret;
int ret = 0, i = 0, j = 0;
u64 ab = 0;
if (!bus) {
SDEROT_ERR("null parameter\n");
return -EINVAL;
}
if (!bus->bus_hdl) {
SDEROT_DBG("bus scaling not enabled\n");
if (!bus || !bus->data_paths_cnt) {
SDEROT_DBG("bus scaling not register\n");
return 0;
} else if (bus->bus_hdl < 0) {
SDEROT_ERR("invalid bus handle %d\n", bus->bus_hdl);
return -EINVAL;
}
if (bus->curr_quota_val == quota) {
@@ -120,46 +88,31 @@ static int sde_rotator_bus_scale_set_quota(struct sde_rot_bus_data_type *bus,
return 0;
}
if (!bus->bus_scale_pdata || !bus->bus_scale_pdata->num_usecases) {
SDEROT_ERR("invalid bus scale data\n");
return -EINVAL;
}
SDEROT_EVTLOG(quota);
SDEROT_DBG("quota=%llu\n", quota);
ATRACE_BEGIN("msm_bus_scale_req_rot");
ab = div_u64(quota, bus->data_paths_cnt);
if (!quota) {
new_uc_idx = 0;
} else {
struct msm_bus_vectors *vect = NULL;
struct msm_bus_scale_pdata *bw_table =
bus->bus_scale_pdata;
u64 port_quota = quota;
u32 total_axi_port_cnt;
int i;
new_uc_idx = (bus->curr_bw_uc_idx %
(bw_table->num_usecases - 1)) + 1;
total_axi_port_cnt = bw_table->usecase[new_uc_idx].num_paths;
if (total_axi_port_cnt == 0) {
SDEROT_ERR("Number of bw paths is 0\n");
return -ENODEV;
}
do_div(port_quota, total_axi_port_cnt);
for (i = 0; i < total_axi_port_cnt; i++) {
vect = &bw_table->usecase[new_uc_idx].vectors[i];
vect->ab = port_quota;
vect->ib = 0;
for (i = 0; i < bus->data_paths_cnt; i++) {
if (bus->data_bus_hdl[i]) {
ret = icc_set_bw(bus->data_bus_hdl[i], ab, ab);
if (ret)
goto err;
}
}
bus->curr_bw_uc_idx = new_uc_idx;
ATRACE_END("msm_bus_scale_req_rot");
bus->curr_quota_val = quota;
SDEROT_EVTLOG(new_uc_idx, quota);
SDEROT_DBG("uc_idx=%d quota=%llu\n", new_uc_idx, quota);
ATRACE_BEGIN("msm_bus_scale_req_rot");
ret = msm_bus_scale_client_update_request(bus->bus_hdl,
new_uc_idx);
return 0;
err:
ab = div_u64(bus->curr_quota_val, bus->data_paths_cnt);
for (j = 0; j < i; j++)
icc_set_bw(bus->data_bus_hdl[j], ab, ab);
ATRACE_END("msm_bus_scale_req_rot");
pr_err("failed to set data bus quota %llu\n", quota);
if (!bus->curr_quota_val) {
pr_err("rotator: data bus was set to 0\n");
return ret;
}
@@ -168,43 +121,40 @@ static int sde_rotator_enable_reg_bus(struct sde_rot_mgr *mgr, u64 quota)
{
int ret = 0, changed = 0;
u32 usecase_ndx = 0;
const struct sde_rot_bus_data *reg_bus_value = NULL;
if (!mgr || !mgr->reg_bus.bus_hdl)
if (!mgr || !mgr->reg_bus.data_paths_cnt)
return 0;
if (quota)
usecase_ndx = 1;
usecase_ndx = VOTE_INDEX_76_MHZ;
if (usecase_ndx != mgr->reg_bus.curr_bw_uc_idx) {
mgr->reg_bus.curr_bw_uc_idx = usecase_ndx;
if (usecase_ndx != mgr->reg_bus.curr_bw_uc_idx)
changed++;
}
SDEROT_DBG("%s, changed=%d register bus %s\n", __func__, changed,
quota ? "Enable":"Disable");
if (changed) {
ATRACE_BEGIN("msm_bus_scale_req_rot_reg");
ret = msm_bus_scale_client_update_request(mgr->reg_bus.bus_hdl,
usecase_ndx);
reg_bus_value = sde_get_rot_reg_bus_value(usecase_ndx);
ret = icc_set_bw(mgr->reg_bus.data_bus_hdl[0],
reg_bus_value->ab, reg_bus_value->ib);
ATRACE_END("msm_bus_scale_req_rot_reg");
}
if (ret) {
pr_err("rotator: set reg bus failed ab=%llu, lb=%llu\n",
reg_bus_value->ab, reg_bus_value->ib);
if (mgr->reg_bus.curr_bw_uc_idx == VOTE_INDEX_DISABLE)
pr_err("rotator: reg bus was disabled\n");
} else {
mgr->reg_bus.curr_bw_uc_idx = usecase_ndx;
}
return ret;
}
#else
static inline int sde_rotator_enable_reg_bus(struct sde_rot_mgr *mgr, u64 quota)
{
return 0;
}
static inline int sde_rotator_bus_scale_set_quota(
struct sde_rot_bus_data_type *bus, u64 quota)
{
return 0;
}
#endif
/*
* Clock rate of all open sessions working a particular hw block
* are added together to get the required rate for that hw block.
@@ -375,6 +325,7 @@ int sde_rotator_clk_ctrl(struct sde_rot_mgr *mgr, int enable)
{
int ret = 0;
int changed = 0;
int i = 0, bus_cnt = 0;
if (enable) {
if (mgr->rot_enable_clk_cnt == 0)
@@ -425,9 +376,15 @@ int sde_rotator_clk_ctrl(struct sde_rot_mgr *mgr, int enable)
goto error_rot_sub;
/* Active+Sleep */
msm_bus_scale_client_update_context(
mgr->data_bus.bus_hdl, false,
mgr->data_bus.curr_bw_uc_idx);
if (mgr->data_bus.bus_active_only) {
bus_cnt = mgr->data_bus.data_paths_cnt;
for (i = 0; i < bus_cnt; i++) {
icc_set_tag(
mgr->data_bus.data_bus_hdl[i],
(QCOM_ICC_TAG_ACTIVE_ONLY |
QCOM_ICC_TAG_SLEEP));
}
}
trace_rot_bw_ao_as_context(0);
} else {
sde_rotator_disable_clk(mgr,
@@ -440,9 +397,15 @@ int sde_rotator_clk_ctrl(struct sde_rot_mgr *mgr, int enable)
sde_rotator_disable_clk(mgr, SDE_ROTATOR_CLK_MNOC_AHB);
/* Active Only */
msm_bus_scale_client_update_context(
mgr->data_bus.bus_hdl, true,
mgr->data_bus.curr_bw_uc_idx);
if (mgr->data_bus.bus_active_only) {
bus_cnt = mgr->data_bus.data_paths_cnt;
for (i = 0; i < bus_cnt; i++) {
icc_set_tag(
mgr->data_bus.data_bus_hdl[i],
QCOM_ICC_TAG_ACTIVE_ONLY);
}
}
trace_rot_bw_ao_as_context(1);
}
}
@@ -2766,56 +2729,67 @@ static struct attribute_group sde_rotator_fs_attr_group = {
.attrs = sde_rotator_fs_attrs
};
#ifdef CONFIG_QCOM_BUS_SCALING
static int sde_rotator_parse_dt_bus(struct sde_rot_mgr *mgr,
struct platform_device *dev)
{
int ret = 0, i;
int usecases;
struct device_node *node;
char bus_name[32];
int ret = 0, i = 0;
mgr->data_bus.bus_scale_pdata = msm_bus_cl_get_pdata(dev);
if (IS_ERR_OR_NULL(mgr->data_bus.bus_scale_pdata)) {
ret = PTR_ERR(mgr->data_bus.bus_scale_pdata);
if (ret) {
SDEROT_ERR("msm_bus_cl_get_pdata failed. ret=%d\n",
ret);
mgr->data_bus.bus_scale_pdata = NULL;
mgr->reg_bus.data_bus_hdl[0] = of_icc_get(&dev->dev,
"qcom,sde-reg-bus");
if (mgr->reg_bus.data_bus_hdl[0] == NULL) {
mgr->reg_bus.data_paths_cnt = 0;
pr_debug("rotator: reg bus dt node missing\n");
goto data_bus;
} else if (IS_ERR(mgr->reg_bus.data_bus_hdl[0])) {
SDEROT_ERR("sde rotator parse reg bus failed. ret=%d\n",
ret);
mgr->reg_bus.data_bus_hdl[0] = NULL;
ret = -EINVAL;
return ret;
}
mgr->reg_bus.data_paths_cnt = 1;
data_bus:
for (i = 0; i < SDE_ROTATION_BUS_PATH_MAX; i++) {
snprintf(bus_name, 32, "%s%d", "qcom,rot-data-bus", i);
ret = of_property_match_string(pdev->dev.of_node,
"interconnect-names", bus_name);
if (ret < 0) {
if (!mgr->data_bus.data_paths_cnt) {
pr_debug("rotator: bus %s dt node missing\n", bus_name);
return 0;
} else
goto end;
} else
mgr->data_bus.data_bus_hdl[i] = of_icc_get(&pdev->dev, bus_name);
if (IS_ERR_OR_NULL(mgr->data_bus.data_bus_hdl[i])) {
SDEROT_ERR("rotator: get data bus %s failed\n",
bus_name);
break;
}
mgr->data_bus.data_paths_cnt++;
}
if (!mgr->data_bus.data_paths_cnt) {
pr_err("rotator: get none data bus path\n");
return -EINVAL;
}
end:
if (of_find_property(dev->dev.of_node,
"qcom,msm-bus,active-only", NULL)) {
mgr->data_bus.bus_active_only = true;
for (i = 0; i < mgr->data_bus.data_paths_cnt; i++) {
icc_set_tag(mgr->data_bus.data_bus_hdl[i],
QCOM_ICC_TAG_ACTIVE_ONLY);
}
}
node = of_get_child_by_name(dev->dev.of_node, "qcom,rot-reg-bus");
if (node) {
mgr->reg_bus.bus_scale_pdata
= msm_bus_pdata_from_node(dev, node);
if (IS_ERR_OR_NULL(mgr->reg_bus.bus_scale_pdata)) {
SDEROT_ERR("reg bus pdata parsing failed\n");
ret = PTR_ERR(mgr->reg_bus.bus_scale_pdata);
if (!mgr->reg_bus.bus_scale_pdata)
ret = -EINVAL;
mgr->reg_bus.bus_scale_pdata = NULL;
}
} else {
SDEROT_DBG(
"no DT entries, configuring default reg bus table\n");
mgr->reg_bus.bus_scale_pdata = &rot_reg_bus_scale_table;
usecases = mgr->reg_bus.bus_scale_pdata->num_usecases;
for (i = 0; i < usecases; i++) {
rot_reg_bus_usecases[i].num_paths = 1;
rot_reg_bus_usecases[i].vectors =
&rot_reg_bus_vectors[i];
}
}
return ret;
}
#else
static inline int sde_rotator_parse_dt_bus(struct sde_rot_mgr *mgr,
struct platform_device *dev)
{
return 0;
}
#endif
static int sde_rotator_parse_dt(struct sde_rot_mgr *mgr,
struct platform_device *dev)
@@ -2920,59 +2894,19 @@ error:
return rc;
}
#ifdef CONFIG_QCOM_BUS_SCALING
static void sde_rotator_bus_scale_unregister(struct sde_rot_mgr *mgr)
{
SDEROT_DBG("unregister bus_hdl=%x, reg_bus_hdl=%x\n",
mgr->data_bus.bus_hdl, mgr->reg_bus.bus_hdl);
int i = 0;
if (mgr->data_bus.bus_hdl)
msm_bus_scale_unregister_client(mgr->data_bus.bus_hdl);
if (mgr->reg_bus.bus_hdl)
msm_bus_scale_unregister_client(mgr->reg_bus.bus_hdl);
}
static int sde_rotator_bus_scale_register(struct sde_rot_mgr *mgr)
{
if (!mgr->data_bus.bus_scale_pdata) {
SDEROT_DBG("Bus scaling is not enabled\n");
return 0;
SDEROT_DBG("unregister sde rotator bus\n");
for (i = 0; i < mgr->data_bus.data_paths_cnt; i++) {
if (mgr->data_bus.data_bus_hdl[i])
icc_put(mgr->data_bus.data_bus_hdl[i]);
}
mgr->data_bus.bus_hdl =
msm_bus_scale_register_client(
mgr->data_bus.bus_scale_pdata);
if (!mgr->data_bus.bus_hdl) {
SDEROT_ERR("bus_client register failed\n");
return -EINVAL;
}
SDEROT_DBG("registered bus_hdl=%x\n", mgr->data_bus.bus_hdl);
if (mgr->reg_bus.bus_scale_pdata) {
mgr->reg_bus.bus_hdl =
msm_bus_scale_register_client(
mgr->reg_bus.bus_scale_pdata);
if (!mgr->reg_bus.bus_hdl) {
SDEROT_ERR("register bus_client register failed\n");
sde_rotator_bus_scale_unregister(mgr);
} else {
SDEROT_DBG("registered register bus_hdl=%x\n",
mgr->reg_bus.bus_hdl);
}
}
return 0;
if (mgr->reg_bus.data_bus_hdl[0])
icc_put(mgr->reg_bus.data_bus_hdl[0]);
}
#else
static inline void sde_rotator_bus_scale_unregister(struct sde_rot_mgr *mgr)
{
}
static inline int sde_rotator_bus_scale_register(struct sde_rot_mgr *mgr)
{
return 0;
}
#endif
static inline int sde_rotator_search_dt_clk(struct platform_device *pdev,
struct sde_rot_mgr *mgr, char *clk_name, int clk_idx,
@@ -3092,10 +3026,6 @@ static int sde_rotator_res_init(struct platform_device *pdev,
if (ret)
goto error;
ret = sde_rotator_bus_scale_register(mgr);
if (ret)
goto error;
return 0;
error:
sde_rotator_put_dt_vreg_data(&pdev->dev, &mgr->module_power);

36
rotator/sde_rotator_core.h
View File

@@ -60,6 +60,23 @@
/* use client provided clock/bandwidth parameters */
#define SDE_ROTATION_EXT_PERF 0x100000
#define SDE_ROTATION_BUS_PATH_MAX 0x2
/*
* The AMC bucket denotes constraints that are applied to hardware when
* icc_set_bw() completes, whereas the WAKE and SLEEP constraints are applied
* when the execution environment transitions between active and low power mode.
*/
#define QCOM_ICC_BUCKET_AMC 0
#define QCOM_ICC_BUCKET_WAKE 1
#define QCOM_ICC_BUCKET_SLEEP 2
#define QCOM_ICC_NUM_BUCKETS 3
#define QCOM_ICC_TAG_AMC BIT(QCOM_ICC_BUCKET_AMC)
#define QCOM_ICC_TAG_WAKE BIT(QCOM_ICC_BUCKET_WAKE)
#define QCOM_ICC_TAG_SLEEP BIT(QCOM_ICC_BUCKET_SLEEP)
#define QCOM_ICC_TAG_ACTIVE_ONLY (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE)
#define QCOM_ICC_TAG_ALWAYS (QCOM_ICC_TAG_AMC | QCOM_ICC_TAG_WAKE |\
QCOM_ICC_TAG_SLEEP)
/**********************************************************************
* configuration structures
@@ -374,18 +391,19 @@ struct sde_rot_file_private {
struct sde_rot_queue_v1 *fenceq;
};
/*
* struct sde_rot_bus_data_type - rotator bus scaling configuration
* @bus_cale_pdata: pointer to bus scaling configuration table
* @bus_hdl: msm bus scaling handle
* @curr_bw_uc_idx; current usecase index into configuration table
* @curr_quota_val: current bandwidth request in byte per second
/**
* struct sde_rot_bus_data_type: power handle struct for data bus
* @data_paths_cnt: number of rt data path ports
* @curr_quota_val: save the current bus value
* @curr_bw_uc_idx: current reg bus value index
* @bus_active_only: AMC support, can set the bus path WAKE/SLEEP
*/
struct sde_rot_bus_data_type {
struct msm_bus_scale_pdata *bus_scale_pdata;
u32 bus_hdl;
u32 curr_bw_uc_idx;
struct icc_path *data_bus_hdl[SDE_ROTATION_BUS_PATH_MAX];
u32 data_paths_cnt;
u64 curr_quota_val;
u32 curr_bw_uc_idx;
bool bus_active_only;
};
/*

1
rotator/sde_rotator_dev.h
View File

@@ -12,7 +12,6 @@
#include <linux/ktime.h>
#include <linux/iommu.h>
#include <linux/dma-buf.h>
#include <linux/msm-bus.h>
#include <linux/platform_device.h>
#include <linux/soc/qcom/llcc-qcom.h>
#include <linux/kthread.h>

2
rotator/sde_rotator_smmu.c
View File

@@ -164,7 +164,7 @@ static int sde_smmu_enable_power(struct sde_smmu_client *sde_smmu,
goto end;
}
sde_update_reg_bus_vote(sde_smmu->reg_bus_clt,
VOTE_INDEX_19_MHZ);
VOTE_INDEX_76_MHZ);
rc = sde_rot_enable_clk(mp->clk_config, mp->num_clk, true);
if (rc) {
SDEROT_ERR("clock enable failed - rc:%d\n", rc);

2
rotator/sde_rotator_util.c
View File

@@ -18,8 +18,6 @@
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/msm-bus.h>
#include <linux/msm-bus-board.h>
#include <linux/regulator/consumer.h>
#include <media/msm_media_info.h>
#include <linux/videodev2.h>