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disp: msm: sde: avoid white color solid fill staging on input fence timeout

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The issue is as follows:
Commit N:
   1. VIG sspp qseed block programmed through lutdma. LUTDMA packet with
      (ram offset, length_0) is queued to internal HW queue to enable
      scaler.
   2. Input_fence timeout seen on VIG plane.
   3. White color solid fill layer staged on VIG plane.
   4. Disable VIG sspp qseed block through LUTDMA. LUTDMA packet is queued
      by overriding buffer with (ram offset, length_1) to internal HW queue
      to disable scaler.
   5. Trigger_flush is picked by HW on vsync.

Since 2 LUTDMA packets are queued on single vsync boundary pp_done timeout
with lutdma HW hang is seen. The only way to fix this is to reset LUTDMA
in step4 and then flush the Hardware. The current SW does not support this
reset sequence, so the change avoids staging solid fill on input fence
timeout.

Change-Id: Ia243e42c863f56b11bee5aeed2dd434efcbd5d75
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
This commit is contained in:
Mahadevan
2022-11-02 12:45:54 +05:30
committed by Gerrit - the friendly Code Review server
parent 827af70599
commit 56d5776a22
1 changed files with 0 additions and 2 deletions
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2
msm/sde/sde_plane.c
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@@ -664,7 +664,6 @@ int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
SDE_ERROR_PLANE(psde, "%ums timeout on %08X fd %lld\n",
wait_ms, prefix, sde_plane_get_property(pstate,
PLANE_PROP_INPUT_FENCE));
psde->is_error = true;
sde_kms_timeline_status(plane->dev);
ret = -ETIMEDOUT;
break;
@@ -686,7 +685,6 @@ int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
SDE_INFO("plane%d spec fd signaled on bind failure fd %lld\n",
plane->base.id,
sde_plane_get_property(pstate, PLANE_PROP_INPUT_FENCE));
psde->is_error = true;
ret = 0;
break;
default: