|
@@ -10862,22 +10862,23 @@ int ipa3_plat_drv_probe(struct platform_device *pdev_p)
|
|
|
|
|
|
if (of_property_read_bool(pdev_p->dev.of_node, "qcom,arm-smmu")) {
|
|
|
if (of_property_read_bool(pdev_p->dev.of_node,
|
|
|
- "qcom,use-64-bit-dma-mask"))
|
|
|
+ "qcom,use-64-bit-dma-mask")) {
|
|
|
smmu_info.use_64_bit_dma_mask = true;
|
|
|
+ if (dma_set_mask_and_coherent(&pdev_p->dev, DMA_BIT_MASK(64))) {
|
|
|
+ IPAERR("DMA set 64bit mask failed\n");
|
|
|
+ return -EOPNOTSUPP;
|
|
|
+ }
|
|
|
+ }
|
|
|
smmu_info.arm_smmu = true;
|
|
|
} else {
|
|
|
if (of_property_read_bool(pdev_p->dev.of_node,
|
|
|
"qcom,use-64-bit-dma-mask")) {
|
|
|
- if (dma_set_mask(&pdev_p->dev, DMA_BIT_MASK(64)) ||
|
|
|
- dma_set_coherent_mask(&pdev_p->dev,
|
|
|
- DMA_BIT_MASK(64))) {
|
|
|
+ if (dma_set_mask_and_coherent(&pdev_p->dev, DMA_BIT_MASK(64))) {
|
|
|
IPAERR("DMA set 64bit mask failed\n");
|
|
|
return -EOPNOTSUPP;
|
|
|
}
|
|
|
} else {
|
|
|
- if (dma_set_mask(&pdev_p->dev, DMA_BIT_MASK(32)) ||
|
|
|
- dma_set_coherent_mask(&pdev_p->dev,
|
|
|
- DMA_BIT_MASK(32))) {
|
|
|
+ if (dma_set_mask_and_coherent(&pdev_p->dev, DMA_BIT_MASK(32))) {
|
|
|
IPAERR("DMA set 32bit mask failed\n");
|
|
|
return -EOPNOTSUPP;
|
|
|
}
|