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disp: msm: dsi: Update dsi byte interface clock calculation

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Update dsi byte interface clock as per hardware recommendation.
For Phy ver 2.0 and below: byte intf clk equals to byte clk.
For Phy ver 3.0 and above: byte intf clk equals to byte clk / 2.

Change-Id: Ic3af2e4348403aeacb2e1c73c4dc133db63a51a4
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Lipsa Rout <lrout@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This commit is contained in:
Lipsa Rout
2019-12-03 19:02:41 +05:30
committed by Satya Rama Aditya Pinapala
parent b15ed9edec
commit 5644d01f7a
7 changed files with 71 additions and 18 deletions
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14
msm/dsi/dsi_ctrl.c
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@@ -877,9 +877,9 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl,
{
int rc = 0;
u32 num_of_lanes = 0;
u32 bpp, frame_time_us;
u32 bpp, frame_time_us, byte_intf_clk_div;
u64 h_period, v_period, bit_rate, pclk_rate, bit_rate_per_lane,
byte_clk_rate;
byte_clk_rate, byte_intf_clk_rate;
struct dsi_host_common_cfg *host_cfg = &config->common_config;
struct dsi_split_link_config *split_link = &host_cfg->split_link;
struct dsi_mode_info *timing = &config->video_timing;
@@ -924,14 +924,20 @@ static int dsi_ctrl_update_link_freqs(struct dsi_ctrl *dsi_ctrl,
do_div(pclk_rate, bpp);
byte_clk_rate = bit_rate_per_lane;
do_div(byte_clk_rate, 8);
byte_intf_clk_rate = byte_clk_rate;
byte_intf_clk_div = host_cfg->byte_intf_clk_div;
do_div(byte_intf_clk_rate, byte_intf_clk_div);
DSI_CTRL_DEBUG(dsi_ctrl, "bit_clk_rate = %llu, bit_clk_rate_per_lane = %llu\n",
bit_rate, bit_rate_per_lane);
DSI_CTRL_DEBUG(dsi_ctrl, "byte_clk_rate = %llu, pclk_rate = %llu\n",
byte_clk_rate, pclk_rate);
DSI_CTRL_DEBUG(dsi_ctrl, "byte_clk_rate = %llu, byte_intf_clk = %llu\n",
byte_clk_rate, byte_intf_clk_rate);
DSI_CTRL_DEBUG(dsi_ctrl, "pclk_rate = %llu\n", pclk_rate);
dsi_ctrl->clk_freq.byte_clk_rate = byte_clk_rate;
dsi_ctrl->clk_freq.pix_clk_rate = pclk_rate;
dsi_ctrl->clk_freq.esc_clk_rate = config->esc_clk_rate_hz;
dsi_ctrl->clk_freq.byte_intf_clk_rate = byte_intf_clk_rate;
config->bit_clk_rate_hz = dsi_ctrl->clk_freq.byte_clk_rate * 8;
rc = dsi_clk_set_link_frequencies(clk_handle, dsi_ctrl->clk_freq,