samsung-sm8650/android_kernel_samsung_sm8650-modules
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

disp: msm: dsi: Update dsi byte interface clock calculation

Browse Source 
Update dsi byte interface clock as per hardware recommendation.
For Phy ver 2.0 and below: byte intf clk equals to byte clk.
For Phy ver 3.0 and above: byte intf clk equals to byte clk / 2.

Change-Id: Ic3af2e4348403aeacb2e1c73c4dc133db63a51a4
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Lipsa Rout <lrout@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This commit is contained in:
Lipsa Rout
2019-12-03 19:02:41 +05:30
committed by Satya Rama Aditya Pinapala
parent b15ed9edec
commit 5644d01f7a
7 changed files with 71 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
msm/dsi/dsi_clk_manager.c
View File

@@ -130,15 +130,16 @@ int dsi_clk_set_pixel_clk_rate(void *client, u64 pixel_clk, u32 index)
* dsi_clk_set_byte_clk_rate() - set frequency for byte clock
* @client: DSI clock client pointer.
* @byte_clk: Byte clock rate in Hz.
* @byte_intf_clk: Byte interface clock rate in Hz.
* @index: Index of the DSI controller.
* return: error code in case of failure or 0 for success.
*/
int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index)
int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk,
u64 byte_intf_clk, u32 index)
{
int rc = 0;
struct dsi_clk_client_info *c = client;
struct dsi_clk_mngr *mngr;
u64 byte_intf_rate;
mngr = c->mngr;
rc = clk_set_rate(mngr->link_clks[index].hs_clks.byte_clk, byte_clk);
@@ -148,12 +149,14 @@ int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index)
mngr->link_clks[index].freq.byte_clk_rate = byte_clk;
if (mngr->link_clks[index].hs_clks.byte_intf_clk) {
byte_intf_rate = mngr->link_clks[index].freq.byte_clk_rate / 2;
rc = clk_set_rate(mngr->link_clks[index].hs_clks.byte_intf_clk,
byte_intf_rate);
byte_intf_clk);
if (rc)
DSI_ERR("failed to set clk rate for byte intf clk=%d\n",
rc);
else
mngr->link_clks[index].freq.byte_intf_clk_rate =
byte_intf_clk;
}
return rc;
@@ -344,12 +347,10 @@ static int dsi_link_hs_clk_set_rate(struct dsi_link_hs_clk_info *link_hs_clks,
/*
* If byte_intf_clk is present, set rate for that too.
* For DPHY: byte_intf_clk_rate = byte_clk_rate / 2
* todo: this needs to be revisited when support for CPHY is added
*/
if (link_hs_clks->byte_intf_clk) {
rc = clk_set_rate(link_hs_clks->byte_intf_clk,
(l_clks->freq.byte_clk_rate / 2));
l_clks->freq.byte_intf_clk_rate);
if (rc) {
DSI_ERR("set_rate failed for byte_intf_clk rc = %d\n",
rc);