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disp: msm: dsi: Update dsi byte interface clock calculation

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Update dsi byte interface clock as per hardware recommendation.
For Phy ver 2.0 and below: byte intf clk equals to byte clk.
For Phy ver 3.0 and above: byte intf clk equals to byte clk / 2.

Change-Id: Ic3af2e4348403aeacb2e1c73c4dc133db63a51a4
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Lipsa Rout <lrout@codeaurora.org>
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This commit is contained in:
Lipsa Rout
2019-12-03 19:02:41 +05:30
committed by Satya Rama Aditya Pinapala
parent b15ed9edec
commit 5644d01f7a
7 changed files with 71 additions and 18 deletions
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6
msm/dsi/dsi_clk.h
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@@ -106,11 +106,13 @@ struct dsi_link_lp_clk_info {
/**
* struct link_clk_freq - Clock frequency information for Link clocks
* @byte_clk_rate: Frequency of DSI byte_clk in KHz.
* @byte_intf_clk_rate: Frequency of DSI byte_intf_clk in KHz.
* @pixel_clk_rate: Frequency of DSI pixel_clk in KHz.
* @esc_clk_rate: Frequency of DSI escape clock in KHz.
*/
struct link_clk_freq {
u32 byte_clk_rate;
u32 byte_intf_clk_rate;
u32 pix_clk_rate;
u32 esc_clk_rate;
};
@@ -292,10 +294,12 @@ int dsi_clk_set_pixel_clk_rate(void *client, u64 pixel_clk, u32 index);
* dsi_clk_set_byte_clk_rate() - set frequency for byte clock
* @client: DSI clock client pointer.
* @byte_clk: Pixel clock rate in Hz.
* @byte_intf_clk: Byte interface clock rate in Hz.
* @index: Index of the DSI controller.
* return: error code in case of failure or 0 for success.
*/
int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index);
int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk,
u64 byte_intf_clk, u32 index);
/**
* dsi_clk_update_parent() - update parent clocks for specified clock