Merge "disp: msm: sde: consider max of actual and default prefill lines"
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@@ -3949,6 +3949,7 @@ void dsi_panel_calc_dsi_transfer_time(struct dsi_host_common_cfg *config,
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struct dsi_mode_info *timing = &mode->timing;
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struct dsi_display_mode *display_mode;
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u32 jitter_numer, jitter_denom, prefill_lines;
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u32 default_prefill_lines, actual_prefill_lines;
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u32 min_threshold_us, prefill_time_us, max_transfer_us, packet_overhead;
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u16 bpp;
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@@ -4012,8 +4013,12 @@ void dsi_panel_calc_dsi_transfer_time(struct dsi_host_common_cfg *config,
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* Increase the prefill_lines proportionately as recommended
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* 40lines for 60fps, 60 for 90fps, 120lines for 120fps, and so on.
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*/
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prefill_lines = mult_frac(MIN_PREFILL_LINES,
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timing->refresh_rate, 60);
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default_prefill_lines = mult_frac(MIN_PREFILL_LINES, timing->refresh_rate, 60);
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actual_prefill_lines = timing->v_back_porch + timing->v_front_porch + timing->v_sync_width;
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/* consider the max of default prefill lines and actual prefill lines */
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prefill_lines = max(actual_prefill_lines, default_prefill_lines);
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prefill_time_us = mult_frac(frame_time_us, prefill_lines,
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(timing->v_active));
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@@ -1,4 +1,5 @@
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/*
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* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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@@ -691,7 +692,7 @@ int msm_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
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args->pitch = align_pitch(args->width, args->bpp);
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args->size = PAGE_ALIGN(args->pitch * args->height);
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return msm_gem_new_handle(dev, file, args->size,
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MSM_BO_SCANOUT | MSM_BO_WC, &args->handle, "dumb");
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MSM_BO_SCANOUT | MSM_BO_CACHED, &args->handle, "dumb");
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}
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int msm_gem_dumb_map_offset(struct drm_file *file, struct drm_device *dev,
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@@ -3615,6 +3615,10 @@ static void sde_crtc_atomic_begin(struct drm_crtc *crtc,
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test_and_clear_bit(SDE_CRTC_DIRTY_UIDLE, &sde_crtc->revalidate_mask);
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/* update cached_encoder_mask if new conn is added or removed */
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if (crtc->state->connectors_changed)
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sde_crtc->cached_encoder_mask = crtc->state->encoder_mask;
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/*
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* Since CP properties use AXI buffer to program the
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* HW, check if context bank is in attached state,
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@@ -5510,6 +5514,8 @@ static u32 sde_crtc_get_vblank_counter(struct drm_crtc *crtc)
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{
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struct drm_encoder *encoder;
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struct sde_crtc *sde_crtc;
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bool is_built_in;
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u32 vblank_cnt;
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if (!crtc)
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return 0;
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@@ -5520,7 +5526,14 @@ static u32 sde_crtc_get_vblank_counter(struct drm_crtc *crtc)
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if (sde_encoder_in_clone_mode(encoder))
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continue;
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return sde_encoder_get_frame_count(encoder);
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is_built_in = sde_encoder_is_built_in_display(encoder);
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vblank_cnt = sde_encoder_get_frame_count(encoder);
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SDE_EVT32(DRMID(crtc), DRMID(encoder), is_built_in, vblank_cnt);
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SDE_DEBUG("crtc:%d enc:%d is_built_in:%d vblank_cnt:%d\n",
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DRMID(crtc), DRMID(encoder), is_built_in, vblank_cnt);
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return vblank_cnt;
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}
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return 0;
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@@ -1129,12 +1129,41 @@ exit:
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phys_enc->enable_state = SDE_ENC_DISABLED;
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}
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static int sde_encoder_phys_vid_poll_for_active_region(struct sde_encoder_phys *phys_enc)
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{
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struct sde_encoder_phys_vid *vid_enc;
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struct intf_timing_params *timing;
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u32 line_cnt, v_inactive, poll_time_us, trial = 0;
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if (!phys_enc || !phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count)
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return -EINVAL;
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vid_enc = to_sde_encoder_phys_vid(phys_enc);
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timing = &vid_enc->timing_params;
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/* if programmable fetch is not enabled return early */
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if (!programmable_fetch_get_num_lines(vid_enc, timing))
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return 0;
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poll_time_us = DIV_ROUND_UP(1000000, timing->vrefresh) / MAX_POLL_CNT;
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v_inactive = timing->v_front_porch + timing->v_back_porch + timing->vsync_pulse_width;
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do {
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usleep_range(poll_time_us, poll_time_us + 5);
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line_cnt = phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf);
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trial++;
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} while ((trial < MAX_POLL_CNT) || (line_cnt < v_inactive));
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return (trial >= MAX_POLL_CNT) ? -ETIMEDOUT : 0;
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}
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static void sde_encoder_phys_vid_handle_post_kickoff(
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struct sde_encoder_phys *phys_enc)
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{
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unsigned long lock_flags;
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struct sde_encoder_phys_vid *vid_enc;
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u32 avr_mode;
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u32 ret;
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if (!phys_enc) {
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SDE_ERROR("invalid encoder\n");
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@@ -1157,6 +1186,10 @@ static void sde_encoder_phys_vid_handle_post_kickoff(
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1);
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spin_unlock_irqrestore(phys_enc->enc_spinlock,
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lock_flags);
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ret = sde_encoder_phys_vid_poll_for_active_region(phys_enc);
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if (ret)
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SDE_DEBUG_VIDENC(vid_enc, "poll for active failed ret:%d\n", ret);
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}
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phys_enc->enable_state = SDE_ENC_ENABLED;
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}
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@@ -1,5 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2009-2021, The Linux Foundation. All rights reserved.
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*/
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@@ -866,6 +867,7 @@ static void _sde_dbg_vbif_disable_block(void __iomem *mem_base, u32 wr_addr)
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MMSS_VBIF_TEST_BUS2_CTRL0 : MMSS_VBIF_TEST_BUS1_CTRL0;
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writel_relaxed(0, mem_base + disable_addr);
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writel_relaxed(BIT(0), mem_base + MMSS_VBIF_TEST_BUS_OUT_CTRL);
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wmb(); /* update test bus */
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}
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static u32 _sde_dbg_vbif_read_test_point(void __iomem *mem_base, u32 wr_addr, u32 rd_addr,
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@@ -881,6 +883,7 @@ static void _sde_dbg_vbif_clear_test_point(void __iomem *mem_base, u32 wr_addr)
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{
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writel_relaxed(0, mem_base + wr_addr);
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writel_relaxed(0, mem_base + wr_addr + 0x4);
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wmb(); /* update test point clear */
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}
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static u32 _sde_dbg_sde_read_test_point(void __iomem *mem_base, u32 wr_addr, u32 rd_addr,
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