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@@ -2922,6 +2922,7 @@ dp_primary_link_migration(struct dp_soc *soc, void *cb_ctxt,
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struct dp_peer *mld_peer = NULL;
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struct dp_peer *mld_peer = NULL;
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uint8_t primary_vdev_id;
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uint8_t primary_vdev_id;
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struct cdp_txrx_peer_params_update params = {0};
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struct cdp_txrx_peer_params_update params = {0};
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+ uint8_t tid;
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pr_soc = dp_mlo_get_soc_ref_by_chip_id(dp_mlo, pr_peer_info->chip_id);
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pr_soc = dp_mlo_get_soc_ref_by_chip_id(dp_mlo, pr_peer_info->chip_id);
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if (!pr_soc) {
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if (!pr_soc) {
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@@ -2942,6 +2943,21 @@ dp_primary_link_migration(struct dp_soc *soc, void *cb_ctxt,
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new_primary_peer->primary_link = 1;
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new_primary_peer->primary_link = 1;
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+ /*
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+ * Check if reo_qref_table_en is set and if
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+ * rx_tid qdesc for tid 0 is already setup and perform
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+ * qref write to LUT for Tid 0 and 16.
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+ *
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+ */
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+ if (hal_reo_shared_qaddr_is_enable(pr_soc->hal_soc) &&
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+ mld_peer->rx_tid[0].hw_qdesc_vaddr_unaligned) {
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+ for (tid = 0; tid < DP_MAX_TIDS; tid++)
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+ hal_reo_shared_qaddr_write(pr_soc->hal_soc,
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+ mld_peer->peer_id,
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+ tid,
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+ mld_peer->rx_tid[tid].hw_qdesc_paddr);
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+ }
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+
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if (pr_soc && pr_soc->cdp_soc.ol_ops->update_primary_link)
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if (pr_soc && pr_soc->cdp_soc.ol_ops->update_primary_link)
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pr_soc->cdp_soc.ol_ops->update_primary_link(pr_soc->ctrl_psoc,
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pr_soc->cdp_soc.ol_ops->update_primary_link(pr_soc->ctrl_psoc,
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new_primary_peer->mac_addr.raw);
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new_primary_peer->mac_addr.raw);
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