samsung-sm8650/android_kernel_samsung_sm8650-modules
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video: driver: fix core lock acquire and release sequence

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[1] Added return type to strict_check() api and bail out if
    strict_check fails.
[2] Fix all the failures with #1.
[3] Added WARN_ON() for strict_check failure.
[4] Ensured &core->lock is acquired before calling below api's.
    - __write_register
    - __write_register_masked
    - __iface_cmdq_write_relaxed
    - __suspend
    - __resume
    - venus_hfi_core_init
    - venus_hfi_core_deinit.

Change-Id: I7f0a3ca6c2aec2758220c90bff9260367f10820b
Signed-off-by: Govindaraj Rajagopal <grajagop@codeaurora.org>
Este commit está contenido en:
Govindaraj Rajagopal
2021-05-19 12:18:58 +05:30
padre 945883602d
commit 53578c8ec2
Se han modificado 8 ficheros con 194 adiciones y 104 borrados
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108
driver/variant/iris2/src/msm_vidc_iris2.c
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@@ -153,8 +153,9 @@
static int __interrupt_init_iris2(struct msm_vidc_core *vidc_core)
{
u32 mask_val = 0;
struct msm_vidc_core *core = vidc_core;
u32 mask_val = 0;
int rc = 0;
if (!core) {
d_vpr_e("%s: invalid params\n", __func__);
@@ -167,7 +168,9 @@ static int __interrupt_init_iris2(struct msm_vidc_core *vidc_core)
/* Write 0 to unmask CPU and WD interrupts */
mask_val &= ~(WRAPPER_INTR_MASK_A2HWD_BMSK_IRIS2|
WRAPPER_INTR_MASK_A2HCPU_BMSK_IRIS2);
__write_register(core, WRAPPER_INTR_MASK_IRIS2, mask_val);
rc = __write_register(core, WRAPPER_INTR_MASK_IRIS2, mask_val);
if (rc)
return rc;
return 0;
}
@@ -175,27 +178,50 @@ static int __interrupt_init_iris2(struct msm_vidc_core *vidc_core)
static int __setup_ucregion_memory_map_iris2(struct msm_vidc_core *vidc_core)
{
struct msm_vidc_core *core = vidc_core;
u32 value;
int rc = 0;
if (!core) {
d_vpr_e("%s: invalid params\n", __func__);
return -EINVAL;
}
__write_register(core, UC_REGION_ADDR_IRIS2,
(u32)core->iface_q_table.align_device_addr);
__write_register(core, UC_REGION_SIZE_IRIS2, SHARED_QSIZE);
__write_register(core, QTBL_ADDR_IRIS2,
(u32)core->iface_q_table.align_device_addr);
__write_register(core, QTBL_INFO_IRIS2, 0x01);
/* update queues vaddr for debug purpose */
__write_register(core, CPU_CS_VCICMDARG0_IRIS2,
(u32)((u64)core->iface_q_table.align_virtual_addr));
__write_register(core, CPU_CS_VCICMDARG1_IRIS2,
(u32)((u64)core->iface_q_table.align_virtual_addr >> 32));
value = (u32)core->iface_q_table.align_device_addr;
rc = __write_register(core, UC_REGION_ADDR_IRIS2, value);
if (rc)
return rc;
if(core->sfr.align_device_addr)
__write_register(core, SFR_ADDR_IRIS2,
(u32)core->sfr.align_device_addr + VIDEO_ARCH_LX);
value = SHARED_QSIZE;
rc = __write_register(core, UC_REGION_SIZE_IRIS2, value);
if (rc)
return rc;
value = (u32)core->iface_q_table.align_device_addr;
rc = __write_register(core, QTBL_ADDR_IRIS2, value);
if (rc)
return rc;
rc = __write_register(core, QTBL_INFO_IRIS2, 0x01);
if (rc)
return rc;
/* update queues vaddr for debug purpose */
value = (u32)((u64)core->iface_q_table.align_virtual_addr);
rc = __write_register(core, CPU_CS_VCICMDARG0_IRIS2, value);
if (rc)
return rc;
value = (u32)((u64)core->iface_q_table.align_virtual_addr >> 32);
rc = __write_register(core, CPU_CS_VCICMDARG1_IRIS2, value);
if (rc)
return rc;
if (core->sfr.align_device_addr) {
value = (u32)core->sfr.align_device_addr + VIDEO_ARCH_LX;
rc = __write_register(core, SFR_ADDR_IRIS2, value);
if (rc)
return rc;
}
return 0;
}
@@ -204,6 +230,7 @@ static int __power_off_iris2(struct msm_vidc_core *vidc_core)
{
u32 lpi_status, reg_status = 0, count = 0, max_count = 10;
struct msm_vidc_core *core = vidc_core;
int rc = 0;
if (!core) {
d_vpr_e("%s: invalid params\n", __func__);
@@ -218,13 +245,18 @@ static int __power_off_iris2(struct msm_vidc_core *vidc_core)
core->intr_status = 0;
/* HPG 6.1.2 Step 1 */
__write_register(core, CPU_CS_X2RPMh_IRIS2, 0x3);
rc = __write_register(core, CPU_CS_X2RPMh_IRIS2, 0x3);
if (rc)
return rc;
/* HPG 6.1.2 Step 2, noc to low power */
//if (core->res->vpu_ver == VPU_VERSION_IRIS2_1)
// goto skip_aon_mvp_noc;
__write_register(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL, 0x1);
rc = __write_register(core, AON_WRAPPER_MVP_NOC_LPI_CONTROL, 0x1);
if (rc)
return rc;
while (!reg_status && count < max_count) {
lpi_status =
__read_register(core,
@@ -240,8 +272,10 @@ static int __power_off_iris2(struct msm_vidc_core *vidc_core)
//skip_aon_mvp_noc:
/* HPG 6.1.2 Step 3, debug bridge to low power */
__write_register(core,
WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_IRIS2, 0x7);
rc = __write_register(core, WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_IRIS2, 0x7);
if (rc)
return rc;
reg_status = 0;
count = 0;
while ((reg_status != 0x7) && count < max_count) {
@@ -257,8 +291,10 @@ static int __power_off_iris2(struct msm_vidc_core *vidc_core)
d_vpr_e("DBLP Set: status %d\n", reg_status);
/* HPG 6.1.2 Step 4, debug bridge to lpi release */
__write_register(core,
WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_IRIS2, 0x0);
rc = __write_register(core, WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_IRIS2, 0x0);
if (rc)
return rc;
lpi_status = 0x1;
count = 0;
while (lpi_status && count < max_count) {
@@ -348,14 +384,17 @@ skip_power_off:
static int __raise_interrupt_iris2(struct msm_vidc_core *vidc_core)
{
struct msm_vidc_core *core = vidc_core;
int rc = 0;
if (!core) {
d_vpr_e("%s: invalid params\n", __func__);
return -EINVAL;
}
__write_register(core, CPU_IC_SOFTINT_IRIS2,
1 << CPU_IC_SOFTINT_H2A_SHFT_IRIS2);
rc = __write_register(core, CPU_IC_SOFTINT_IRIS2, 1 << CPU_IC_SOFTINT_H2A_SHFT_IRIS2);
if (rc)
return rc;
return 0;
}
@@ -419,8 +458,9 @@ static int __noc_error_info_iris2(struct msm_vidc_core *vidc_core)
static int __clear_interrupt_iris2(struct msm_vidc_core *vidc_core)
{
u32 intr_status = 0, mask = 0;
struct msm_vidc_core *core = vidc_core;
u32 intr_status = 0, mask = 0;
int rc = 0;
if (!core) {
d_vpr_e("%s: NULL core\n", __func__);
@@ -441,7 +481,9 @@ static int __clear_interrupt_iris2(struct msm_vidc_core *vidc_core)
core->spur_count++;
}
__write_register(core, CPU_CS_A2HSOFTINTCLR_IRIS2, 1);
rc = __write_register(core, CPU_CS_A2HSOFTINTCLR_IRIS2, 1);
if (rc)
return rc;
return 0;
}
@@ -459,7 +501,10 @@ static int __boot_firmware_iris2(struct msm_vidc_core *vidc_core)
ctrl_init_val = BIT(0);
__write_register(core, CTRL_INIT_IRIS2, ctrl_init_val);
rc = __write_register(core, CTRL_INIT_IRIS2, ctrl_init_val);
if (rc)
return rc;
while (!ctrl_status && count < max_tries) {
ctrl_status = __read_register(core, CTRL_STATUS_IRIS2);
if ((ctrl_status & CTRL_ERROR_STATUS__M_IRIS2) == 0x4) {
@@ -477,8 +522,13 @@ static int __boot_firmware_iris2(struct msm_vidc_core *vidc_core)
}
/* Enable interrupt before sending commands to venus */
__write_register(core, CPU_CS_H2XSOFTINTEN_IRIS2, 0x1);
__write_register(core, CPU_CS_X2RPMh_IRIS2, 0x0);
rc = __write_register(core, CPU_CS_H2XSOFTINTEN_IRIS2, 0x1);
if (rc)
return rc;
rc = __write_register(core, CPU_CS_X2RPMh_IRIS2, 0x0);
if (rc)
return rc;
return rc;
}