From 7f7c4b8e20ea33bff10f5905ac519da2b3c87636 Mon Sep 17 00:00:00 2001 From: Mahadevan Date: Wed, 29 Sep 2021 15:34:43 +0530 Subject: [PATCH] disp: msm: sde: add rev checks for diwali target Add required revision checks from display for diwali target. Change-Id: Ib165b1133eea1203de3b946b46cf39ee0ad05e47 Signed-off-by: Mahadevan --- msm/sde/sde_hw_catalog.c | 36 ++++++++++++++++++++++++++++++++++++ msm/sde/sde_hw_catalog.h | 2 ++ 2 files changed, 38 insertions(+) diff --git a/msm/sde/sde_hw_catalog.c b/msm/sde/sde_hw_catalog.c index 9dfabe8155..6d26214649 100644 --- a/msm/sde/sde_hw_catalog.c +++ b/msm/sde/sde_hw_catalog.c @@ -5128,6 +5128,42 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) sde_cfg->dither_luma_mode_support = true; sde_cfg->mdss_hw_block_size = 0x158; sde_cfg->rc_lm_flush_override = false; + } else if (IS_DIWALI_TARGET(hw_rev)) { + sde_cfg->allowed_dsc_reservation_switch = SDE_DP_DSC_RESERVATION_SWITCH; + sde_cfg->has_dedicated_cwb_support = true; + sde_cfg->has_cwb_dither = true; + sde_cfg->has_wb_ubwc = true; + sde_cfg->has_cwb_crop = true; + sde_cfg->has_qsync = true; + sde_cfg->perf.min_prefill_lines = 40; + sde_cfg->vbif_qos_nlvl = 8; + sde_cfg->ts_prefill_rev = 2; + sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0; + sde_cfg->delay_prg_fetch_start = true; + sde_cfg->sui_ns_allowed = true; + sde_cfg->sui_misr_supported = true; + sde_cfg->has_sui_blendstage = true; + sde_cfg->has_3d_merge_reset = true; + sde_cfg->has_hdr = true; + sde_cfg->has_hdr_plus = true; + sde_cfg->skip_inline_rot_threshold = true; + set_bit(SDE_MDP_DHDR_MEMPOOL_4K, &sde_cfg->mdp[0].features); + sde_cfg->has_vig_p010 = true; + sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_2_0_1; + sde_cfg->vbif_disable_inner_outer_shareable = true; + sde_cfg->dither_luma_mode_support = true; + sde_cfg->mdss_hw_block_size = 0x158; + sde_cfg->syscache_supported = true; + sde_cfg->sspp_multirect_error = true; + sde_cfg->has_fp16 = true; + set_bit(SDE_MDP_PERIPH_TOP_0_REMOVED, &sde_cfg->mdp[0].features); + sde_cfg->has_precise_vsync_ts = true; + sde_cfg->has_avr_step = true; + sde_cfg->has_trusted_vm_support = true; + sde_cfg->has_ubwc_stats = true; + sde_cfg->has_demura = true; + sde_cfg->demura_supported[SSPP_DMA1][0] = 0; + sde_cfg->demura_supported[SSPP_DMA1][1] = 1; } else { SDE_ERROR("unsupported chipset id:%X\n", hw_rev); sde_cfg->perf.min_prefill_lines = 0xffff; diff --git a/msm/sde/sde_hw_catalog.h b/msm/sde/sde_hw_catalog.h index cb2a3f4c12..b3a3b5dafb 100644 --- a/msm/sde/sde_hw_catalog.h +++ b/msm/sde/sde_hw_catalog.h @@ -49,6 +49,7 @@ #define SDE_HW_VER_700 SDE_HW_VER(7, 0, 0) /* lahaina */ #define SDE_HW_VER_720 SDE_HW_VER(7, 2, 0) /* yupik */ #define SDE_HW_VER_810 SDE_HW_VER(8, 1, 0) /* waipio */ +#define SDE_HW_VER_820 SDE_HW_VER(8, 2, 0) /* diwali */ /* Avoid using below IS_XXX macros outside catalog, use feature bit instead */ #define IS_SDE_MAJOR_SAME(rev1, rev2) \ @@ -75,6 +76,7 @@ #define IS_LAHAINA_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_700) #define IS_YUPIK_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_720) #define IS_WAIPIO_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_810) +#define IS_DIWALI_TARGET(rev) IS_SDE_MAJOR_MINOR_SAME((rev), SDE_HW_VER_820) #define SDE_HW_BLK_NAME_LEN 16