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@@ -470,7 +470,7 @@ static int cam_ife_csid_ver2_handle_rx_irq(
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CAM_DBG(CAM_ISP, "CSID:%u Enter", csid_hw->hw_intf->hw_idx);
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rc = cam_irq_controller_handle_irq(evt_id,
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- csid_hw->rx_irq_controller, CAM_IRQ_EVT_GROUP_0);
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+ csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0], CAM_IRQ_EVT_GROUP_0);
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CAM_DBG(CAM_ISP, "CSID:%u Exit (rc=%d)", csid_hw->hw_intf->hw_idx, rc);
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return (rc == IRQ_HANDLED) ? 0 : -EINVAL;
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@@ -783,18 +783,18 @@ static int cam_ife_csid_ver2_stop_csi2_in_err(
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if (csid_hw->rx_cfg.top_irq_handle)
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cam_irq_controller_disable_irq(
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- csid_hw->top_irq_controller,
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+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
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csid_hw->rx_cfg.top_irq_handle);
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if (csid_hw->rx_cfg.irq_handle)
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cam_irq_controller_disable_irq(
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- csid_hw->rx_irq_controller,
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+ csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0],
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csid_hw->rx_cfg.irq_handle);
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- if (csid_hw->rx_cfg.err_irq_handle)
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+ if (csid_hw->rx_cfg.err_irq_handle[CAM_IFE_CSID_RX_IRQ_STATUS_REG0])
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cam_irq_controller_disable_irq(
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- csid_hw->rx_irq_controller,
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- csid_hw->rx_cfg.err_irq_handle);
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+ csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0],
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+ csid_hw->rx_cfg.err_irq_handle[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]);
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return 0;
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}
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@@ -806,7 +806,7 @@ static inline void cam_ife_csid_ver2_maskout_rx_irqs(
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if (csid_hw->rx_cfg.irq_handle) {
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rc = cam_irq_controller_unsubscribe_irq(
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- csid_hw->rx_irq_controller,
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+ csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0],
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csid_hw->rx_cfg.irq_handle);
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if (rc)
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CAM_WARN(CAM_ISP,
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@@ -816,21 +816,20 @@ static inline void cam_ife_csid_ver2_maskout_rx_irqs(
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csid_hw->rx_cfg.irq_handle = 0;
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}
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- if (csid_hw->rx_cfg.err_irq_handle) {
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+ if (csid_hw->rx_cfg.err_irq_handle[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]) {
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rc = cam_irq_controller_unsubscribe_irq(
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- csid_hw->rx_irq_controller,
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- csid_hw->rx_cfg.err_irq_handle);
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+ csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0],
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+ csid_hw->rx_cfg.err_irq_handle[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]);
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if (rc)
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CAM_WARN(CAM_ISP,
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"Failed to unsubscribe rx err irq for CSID:%u rc:%d",
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csid_hw->hw_intf->hw_idx, rc);
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-
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- csid_hw->rx_cfg.err_irq_handle = 0;
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+ csid_hw->rx_cfg.err_irq_handle[CAM_IFE_CSID_RX_IRQ_STATUS_REG0] = 0;
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}
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if (csid_hw->rx_cfg.top_irq_handle) {
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rc = cam_irq_controller_unsubscribe_irq(
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- csid_hw->top_irq_controller,
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+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
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csid_hw->rx_cfg.top_irq_handle);
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if (rc)
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CAM_WARN(CAM_ISP,
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@@ -838,8 +837,9 @@ static inline void cam_ife_csid_ver2_maskout_rx_irqs(
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csid_hw->hw_intf->hw_idx, rc);
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csid_hw->rx_cfg.irq_handle = 0;
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- cam_irq_controller_unregister_dependent(csid_hw->top_irq_controller,
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- csid_hw->rx_irq_controller);
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+ cam_irq_controller_unregister_dependent(
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+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
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+ csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]);
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}
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}
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@@ -850,7 +850,7 @@ static inline void cam_ife_csid_ver2_disable_rx_evts(
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if (csid_hw->rx_cfg.irq_handle) {
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rc = cam_irq_controller_unsubscribe_irq_evt(
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- csid_hw->rx_irq_controller,
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+ csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0],
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csid_hw->rx_cfg.irq_handle);
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if (rc)
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CAM_WARN(CAM_ISP,
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@@ -860,21 +860,21 @@ static inline void cam_ife_csid_ver2_disable_rx_evts(
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csid_hw->rx_cfg.irq_handle = 0;
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}
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- if (csid_hw->rx_cfg.err_irq_handle) {
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+ if (csid_hw->rx_cfg.err_irq_handle[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]) {
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rc = cam_irq_controller_unsubscribe_irq_evt(
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- csid_hw->rx_irq_controller,
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- csid_hw->rx_cfg.err_irq_handle);
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+ csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0],
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+ csid_hw->rx_cfg.err_irq_handle[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]);
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if (rc)
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CAM_WARN(CAM_ISP,
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"Failed to unsubscribe rx err irq evt for CSID:%u rc:%d",
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csid_hw->hw_intf->hw_idx, rc);
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- csid_hw->rx_cfg.err_irq_handle = 0;
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+ csid_hw->rx_cfg.err_irq_handle[CAM_IFE_CSID_RX_IRQ_STATUS_REG0] = 0;
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}
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if (csid_hw->rx_cfg.top_irq_handle) {
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rc = cam_irq_controller_unsubscribe_irq_evt(
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- csid_hw->top_irq_controller,
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+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
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csid_hw->rx_cfg.top_irq_handle);
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if (rc)
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CAM_WARN(CAM_ISP,
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@@ -882,8 +882,9 @@ static inline void cam_ife_csid_ver2_disable_rx_evts(
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csid_hw->hw_intf->hw_idx, rc);
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csid_hw->rx_cfg.irq_handle = 0;
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- cam_irq_controller_unregister_dependent(csid_hw->top_irq_controller,
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- csid_hw->rx_irq_controller);
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+ cam_irq_controller_unregister_dependent(
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+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
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+ csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]);
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}
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}
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@@ -915,13 +916,13 @@ static int cam_ife_csid_ver2_rx_err_top_half(
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uint32_t evt_id,
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struct cam_irq_th_payload *th_payload)
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{
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- int32_t rc = 0;
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- uint32_t status = 0;
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- struct cam_ife_csid_ver2_hw *csid_hw = NULL;
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- struct cam_ife_csid_ver2_reg_info *csid_reg;
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- struct cam_ife_csid_ver2_evt_payload *evt_payload;
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- const struct cam_ife_csid_csi2_rx_reg_info *csi2_reg;
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- int discard_frame_count;
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+ int32_t rc = 0;
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+ uint32_t status = 0;
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+ struct cam_ife_csid_ver2_hw *csid_hw = NULL;
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+ struct cam_ife_csid_ver2_reg_info *csid_reg;
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+ struct cam_ife_csid_ver2_evt_payload *evt_payload;
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+ const struct cam_ife_csid_ver2_csi2_rx_reg_info *csi2_reg;
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+ int discard_frame_count;
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csid_hw = th_payload->handler_priv;
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if (!csid_hw) {
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@@ -962,13 +963,13 @@ static int cam_ife_csid_ver2_rx_err_top_half(
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status &= (~IFE_CSID_VER2_RX_CPHY_EOT_RECEPTION);
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}
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- if (status & csi2_reg->fatal_err_mask) {
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+ if (status & csi2_reg->fatal_err_mask[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]) {
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csid_hw->flags.fatal_err_detected = true;
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cam_ife_csid_ver2_stop_csi2_in_err(csid_hw);
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goto end;
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}
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- if (status & csi2_reg->part_fatal_err_mask) {
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+ if (status & csi2_reg->part_fatal_err_mask[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]) {
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if (status & IFE_CSID_VER2_RX_CPHY_SOT_RECEPTION)
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csid_hw->counters.error_irq_count++;
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@@ -997,12 +998,14 @@ end:
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}
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static int cam_ife_csid_ver2_handle_rx_debug_event(
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- struct cam_ife_csid_ver2_hw *csid_hw,
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- uint32_t bit_pos, uint32_t *rst_strobe_val)
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+ struct cam_ife_csid_ver2_hw *csid_hw,
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+ enum cam_ife_csid_rx_irq_regs rx_index,
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+ uint32_t bit_pos,
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+ uint32_t *rst_strobe_val)
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{
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struct cam_hw_soc_info *soc_info;
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struct cam_ife_csid_ver2_reg_info *csid_reg;
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- const struct cam_ife_csid_csi2_rx_reg_info *csi2_reg;
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+ const struct cam_ife_csid_ver2_csi2_rx_reg_info *csi2_reg;
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uint32_t mask, val;
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csid_reg = (struct cam_ife_csid_ver2_reg_info *)
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@@ -1099,7 +1102,7 @@ static int cam_ife_csid_ver2_handle_rx_debug_event(
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CAM_DBG(CAM_ISP,
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"CSID[%u] RX_IRQ: %s",
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csid_hw->hw_intf->hw_idx,
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- csid_reg->rx_irq_desc[bit_pos].desc);
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+ (*csid_reg->rx_irq_desc)[rx_index][bit_pos].desc);
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break;
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}
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@@ -1111,7 +1114,7 @@ static int cam_ife_csid_ver2_rx_top_half(
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struct cam_irq_th_payload *th_payload)
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{
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struct cam_ife_csid_ver2_hw *csid_hw = NULL;
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- const struct cam_ife_csid_csi2_rx_reg_info *csi2_reg;
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+ const struct cam_ife_csid_ver2_csi2_rx_reg_info *csi2_reg;
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struct cam_ife_csid_ver2_reg_info *csid_reg;
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uint32_t irq_status;
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uint32_t rst_strobe_val = 0;
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@@ -1134,7 +1137,7 @@ static int cam_ife_csid_ver2_rx_top_half(
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bit_set = irq_status & 1;
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if ((bit_set) && (BIT(bit_pos) & csid_hw->debug_info.rx_mask))
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cam_ife_csid_ver2_handle_rx_debug_event(csid_hw,
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- bit_pos, &rst_strobe_val);
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+ CAM_IFE_CSID_RX_IRQ_STATUS_REG0, bit_pos, &rst_strobe_val);
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bit_pos++;
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irq_status >>= 1;
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}
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@@ -1224,7 +1227,7 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
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void *handler_priv,
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void *evt_payload_priv)
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{
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- const struct cam_ife_csid_csi2_rx_reg_info *csi2_reg;
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+ const struct cam_ife_csid_ver2_csi2_rx_reg_info *csi2_reg;
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struct cam_ife_csid_ver2_evt_payload *payload;
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struct cam_ife_csid_ver2_hw *csid_hw = NULL;
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struct cam_ife_csid_ver2_reg_info *csid_reg;
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@@ -1255,7 +1258,8 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
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csid_hw->core_info->csid_reg;
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csi2_reg = csid_reg->csi2_reg;
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- irq_status = payload->irq_reg_val & csi2_reg->fatal_err_mask;
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+ irq_status = payload->irq_reg_val &
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+ csi2_reg->fatal_err_mask[CAM_IFE_CSID_RX_IRQ_STATUS_REG0];
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if (!csid_hw->flags.device_enabled) {
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CAM_DBG(CAM_ISP, "CSID[%u] bottom-half after stop [0x%x]",
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@@ -1361,7 +1365,8 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
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csid_hw->flags.fatal_err_detected = true;
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}
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- irq_status = payload->irq_reg_val & csi2_reg->part_fatal_err_mask;
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+ irq_status = payload->irq_reg_val &
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+ csi2_reg->part_fatal_err_mask[CAM_IFE_CSID_RX_IRQ_STATUS_REG0];
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if (irq_status) {
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len = 0;
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@@ -1375,7 +1380,8 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
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rx_irq_status |= irq_status;
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}
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- irq_status = payload->irq_reg_val & csi2_reg->non_fatal_err_mask;
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+ irq_status = payload->irq_reg_val &
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+ csi2_reg->non_fatal_err_mask[CAM_IFE_CSID_RX_IRQ_STATUS_REG0];
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if (irq_status) {
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len = 0;
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@@ -1813,30 +1819,49 @@ static int cam_ife_csid_ver2_top_err_irq_bottom_half(
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csid_reg = (struct cam_ife_csid_ver2_reg_info *)
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csid_hw->core_info->csid_reg;
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- irq_status = payload->irq_reg_val & csid_reg->cmn_reg->top_err_irq_mask;
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+ irq_status = payload->irq_reg_val &
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+ csid_reg->cmn_reg->top_err_irq_mask[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0];
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if (!irq_status) {
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CAM_ERR(CAM_ISP, "CSID:%u Unexpected Scenario", csid_hw->hw_intf->hw_idx);
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return 0;
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}
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- for (i = 0; i < csid_reg->num_top_err_irqs; i++) {
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- if (csid_reg->top_irq_desc[i].bitmask &
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- irq_status) {
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- CAM_ERR(CAM_ISP, "CSID:%u %s %s",
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- csid_hw->hw_intf->hw_idx, csid_reg->top_irq_desc[i].err_name,
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- csid_reg->top_irq_desc[i].desc);
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+ if (!csid_reg->num_top_err_irqs) {
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+ CAM_WARN_RATE_LIMIT_CUSTOM(CAM_ISP, 100, 1,
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+ "CSID:%u Unexpected Scenario no top error irqs", csid_hw->hw_intf->hw_idx);
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+ cam_ife_csid_ver2_put_evt_payload(csid_hw, &payload,
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+ &csid_hw->path_free_payload_list, &csid_hw->path_payload_lock);
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+ return 0;
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+ }
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- if (csid_reg->top_irq_desc[i].err_handler)
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- csid_reg->top_irq_desc[i].err_handler(csid_hw);
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+ for (i = 0; i < csid_reg->num_top_err_irqs[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]; i++) {
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+ if (!csid_reg->top_irq_desc) {
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+ CAM_ERR(CAM_ISP, "CSID:%u Unexpected Scenario top irq descriptor empty",
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+ csid_hw->hw_intf->hw_idx);
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+ break;
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+ }
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- event_type |= csid_reg->top_irq_desc[i].err_type;
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+ if ((*csid_reg->top_irq_desc)[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0][i].bitmask &
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+ irq_status) {
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+ CAM_ERR(CAM_ISP, "%s %s",
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+ (*csid_reg->top_irq_desc)
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+ [CAM_IFE_CSID_TOP_IRQ_STATUS_REG0][i].err_name,
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+ (*csid_reg->top_irq_desc)
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+ [CAM_IFE_CSID_TOP_IRQ_STATUS_REG0][i].desc);
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+ if ((*csid_reg->top_irq_desc)[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0][i]
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+ .err_handler)
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+ (*csid_reg->top_irq_desc)[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0][i]
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+ .err_handler(csid_hw);
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+
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+ event_type |= (*csid_reg->top_irq_desc)
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+ [CAM_IFE_CSID_TOP_IRQ_STATUS_REG0][i].err_type;
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}
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}
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if (event_type)
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cam_ife_csid_ver2_handle_event_err(csid_hw,
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- irq_status, event_type, false, NULL);
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+ irq_status, event_type, false, NULL);
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cam_ife_csid_ver2_put_evt_payload(csid_hw, &payload,
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&csid_hw->path_free_payload_list,
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@@ -2349,7 +2374,7 @@ static int cam_ife_csid_ver2_internal_reset(
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uint32_t val = 0;
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struct cam_ife_csid_ver2_reg_info *csid_reg;
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struct cam_hw_soc_info *soc_info;
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- const struct cam_ife_csid_csi2_rx_reg_info *csi2_reg;
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+ const struct cam_ife_csid_ver2_csi2_rx_reg_info *csi2_reg;
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void __iomem *mem_base;
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|
|
int rc = 0;
|
|
|
|
|
@@ -2513,7 +2538,7 @@ static inline void cam_ife_csid_ver2_maskout_path_irqs(
|
|
|
|
|
|
if (path_cfg->top_irq_handle) {
|
|
|
rc = cam_irq_controller_unsubscribe_irq(
|
|
|
- csid_hw->top_irq_controller,
|
|
|
+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
path_cfg->top_irq_handle);
|
|
|
if (rc)
|
|
|
CAM_WARN(CAM_ISP,
|
|
@@ -2523,7 +2548,7 @@ static inline void cam_ife_csid_ver2_maskout_path_irqs(
|
|
|
path_cfg->top_irq_handle = 0;
|
|
|
|
|
|
(void) cam_irq_controller_unregister_dependent(
|
|
|
- csid_hw->top_irq_controller,
|
|
|
+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
csid_hw->path_irq_controller[res_id]);
|
|
|
}
|
|
|
}
|
|
@@ -2573,7 +2598,7 @@ static inline void cam_ife_csid_ver2_disable_path_irqs_evts(
|
|
|
|
|
|
if (path_cfg->top_irq_handle) {
|
|
|
rc = cam_irq_controller_unsubscribe_irq_evt(
|
|
|
- csid_hw->top_irq_controller,
|
|
|
+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
path_cfg->top_irq_handle);
|
|
|
if (rc)
|
|
|
CAM_WARN(CAM_ISP,
|
|
@@ -2583,7 +2608,7 @@ static inline void cam_ife_csid_ver2_disable_path_irqs_evts(
|
|
|
path_cfg->top_irq_handle = 0;
|
|
|
|
|
|
(void) cam_irq_controller_unregister_dependent(
|
|
|
- csid_hw->top_irq_controller,
|
|
|
+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
csid_hw->path_irq_controller[res_id]);
|
|
|
}
|
|
|
}
|
|
@@ -3238,7 +3263,7 @@ int cam_ife_csid_ver2_release(void *hw_priv,
|
|
|
|
|
|
if (!csid_hw->counters.csi2_reserve_cnt) {
|
|
|
memset(&csid_hw->rx_cfg, 0,
|
|
|
- sizeof(struct cam_ife_csid_rx_cfg));
|
|
|
+ sizeof(struct cam_ife_csid_ver2_rx_cfg));
|
|
|
memset(&csid_hw->top_cfg, 0,
|
|
|
sizeof(struct cam_ife_csid_ver2_top_cfg));
|
|
|
memset(&csid_hw->debug_info, 0,
|
|
@@ -3714,17 +3739,30 @@ static int cam_ife_csid_ver2_path_irq_subscribe(
|
|
|
struct cam_isp_resource_node *res,
|
|
|
uint32_t irq_mask, uint32_t err_irq_mask)
|
|
|
{
|
|
|
- uint32_t top_irq_mask[CAM_IFE_CSID_IRQ_REGISTERS_MAX] = {0};
|
|
|
+ uint32_t top_irq_mask = 0;
|
|
|
struct cam_ife_csid_ver2_path_cfg *path_cfg = res->res_priv;
|
|
|
struct cam_ife_csid_ver2_reg_info *csid_reg = csid_hw->core_info->csid_reg;
|
|
|
- int rc;
|
|
|
+ int i, rc;
|
|
|
+ int top_index = -1;
|
|
|
+
|
|
|
+ for (i = CAM_IFE_CSID_TOP_IRQ_STATUS_REG0; i < csid_reg->num_top_regs; i++) {
|
|
|
+ if (csid_reg->path_reg[res->res_id]->top_irq_mask[i]) {
|
|
|
+ top_index = i;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
|
|
|
- top_irq_mask[CAM_IFE_CSID_IRQ_TOP_REG_STATUS0] =
|
|
|
- csid_reg->path_reg[res->res_id]->top_irq_mask;
|
|
|
+ if (top_index < 0) {
|
|
|
+ CAM_ERR(CAM_ISP, "csid[%d] subscribe top irq fail %s",
|
|
|
+ csid_hw->hw_intf->hw_idx, res->res_name);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ top_irq_mask = csid_reg->path_reg[res->res_id]->top_irq_mask[top_index];
|
|
|
path_cfg->top_irq_handle = cam_irq_controller_subscribe_irq(
|
|
|
- csid_hw->top_irq_controller,
|
|
|
+ csid_hw->top_irq_controller[top_index],
|
|
|
CAM_IRQ_PRIORITY_0,
|
|
|
- top_irq_mask,
|
|
|
+ &top_irq_mask,
|
|
|
res,
|
|
|
cam_ife_csid_ver2_handle_path_irq,
|
|
|
NULL, NULL, NULL, CAM_IRQ_EVT_GROUP_0);
|
|
@@ -3735,8 +3773,8 @@ static int cam_ife_csid_ver2_path_irq_subscribe(
|
|
|
return -EINVAL;
|
|
|
}
|
|
|
|
|
|
- rc = cam_irq_controller_register_dependent(csid_hw->top_irq_controller,
|
|
|
- csid_hw->path_irq_controller[res->res_id], top_irq_mask);
|
|
|
+ rc = cam_irq_controller_register_dependent(csid_hw->top_irq_controller[top_index],
|
|
|
+ csid_hw->path_irq_controller[res->res_id], &top_irq_mask);
|
|
|
|
|
|
if (rc)
|
|
|
goto unsub_top;
|
|
@@ -3784,10 +3822,10 @@ unsub_path:
|
|
|
path_cfg->irq_handle);
|
|
|
path_cfg->irq_handle = 0;
|
|
|
unreg_path:
|
|
|
- cam_irq_controller_unregister_dependent(csid_hw->top_irq_controller,
|
|
|
+ cam_irq_controller_unregister_dependent(csid_hw->top_irq_controller[top_index],
|
|
|
csid_hw->path_irq_controller[res->res_id]);
|
|
|
unsub_top:
|
|
|
- cam_irq_controller_unsubscribe_irq(csid_hw->top_irq_controller,
|
|
|
+ cam_irq_controller_unsubscribe_irq(csid_hw->top_irq_controller[top_index],
|
|
|
path_cfg->top_irq_handle);
|
|
|
path_cfg->top_irq_handle = 0;
|
|
|
return rc;
|
|
@@ -4176,7 +4214,7 @@ static int cam_ife_csid_ver2_rx_capture_config(
|
|
|
{
|
|
|
const struct cam_ife_csid_ver2_reg_info *csid_reg;
|
|
|
struct cam_hw_soc_info *soc_info;
|
|
|
- struct cam_ife_csid_rx_cfg *rx_cfg;
|
|
|
+ struct cam_ife_csid_ver2_rx_cfg *rx_cfg;
|
|
|
uint32_t vc, dt, i;
|
|
|
uint32_t val = 0;
|
|
|
|
|
@@ -4230,14 +4268,29 @@ static int cam_ife_csid_ver2_csi2_irq_subscribe(struct cam_ife_csid_ver2_hw *csi
|
|
|
uint32_t irq_mask, uint32_t err_irq_mask)
|
|
|
{
|
|
|
struct cam_ife_csid_ver2_reg_info *csid_reg = csid_hw->core_info->csid_reg;
|
|
|
- uint32_t top_irq_mask[CAM_IFE_CSID_IRQ_REGISTERS_MAX] = {0};
|
|
|
- int rc;
|
|
|
+ uint32_t top_irq_mask = 0;
|
|
|
+ int top_index = -1;
|
|
|
+ int i, rc;
|
|
|
|
|
|
- top_irq_mask[CAM_IFE_CSID_IRQ_TOP_REG_STATUS0] = csid_reg->csi2_reg->top_irq_mask;
|
|
|
+ for (i = CAM_IFE_CSID_TOP_IRQ_STATUS_REG0; i < csid_reg->num_top_regs; i++) {
|
|
|
+ if (csid_reg->csi2_reg->top_irq_mask[i]) {
|
|
|
+ top_index = i;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ if (top_index < 0) {
|
|
|
+ CAM_ERR(CAM_ISP, "CSID[%d] RX Subscribe Top Irq fail due to invalid mask",
|
|
|
+ csid_hw->hw_intf->hw_idx);
|
|
|
+ rc = -EINVAL;
|
|
|
+ return rc;
|
|
|
+ }
|
|
|
+
|
|
|
+ top_irq_mask = csid_reg->csi2_reg->top_irq_mask[top_index];
|
|
|
csid_hw->rx_cfg.top_irq_handle = cam_irq_controller_subscribe_irq(
|
|
|
- csid_hw->top_irq_controller,
|
|
|
+ csid_hw->top_irq_controller[top_index],
|
|
|
CAM_IRQ_PRIORITY_0,
|
|
|
- top_irq_mask,
|
|
|
+ &top_irq_mask,
|
|
|
csid_hw,
|
|
|
cam_ife_csid_ver2_handle_rx_irq,
|
|
|
NULL, NULL, NULL, CAM_IRQ_EVT_GROUP_0);
|
|
@@ -4249,15 +4302,17 @@ static int cam_ife_csid_ver2_csi2_irq_subscribe(struct cam_ife_csid_ver2_hw *csi
|
|
|
goto err;
|
|
|
}
|
|
|
|
|
|
- rc = cam_irq_controller_register_dependent(csid_hw->top_irq_controller,
|
|
|
- csid_hw->rx_irq_controller, top_irq_mask);
|
|
|
+ rc = cam_irq_controller_register_dependent(csid_hw->top_irq_controller[top_index],
|
|
|
+ csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0],
|
|
|
+ &top_irq_mask);
|
|
|
|
|
|
if (rc)
|
|
|
goto unsub_top;
|
|
|
|
|
|
if (irq_mask) {
|
|
|
csid_hw->rx_cfg.irq_handle = cam_irq_controller_subscribe_irq(
|
|
|
- csid_hw->rx_irq_controller,
|
|
|
+ csid_hw->rx_irq_controller
|
|
|
+ [CAM_IFE_CSID_RX_IRQ_STATUS_REG0],
|
|
|
CAM_IRQ_PRIORITY_4,
|
|
|
&irq_mask,
|
|
|
csid_hw,
|
|
@@ -4275,8 +4330,10 @@ static int cam_ife_csid_ver2_csi2_irq_subscribe(struct cam_ife_csid_ver2_hw *csi
|
|
|
}
|
|
|
}
|
|
|
|
|
|
- csid_hw->rx_cfg.err_irq_handle = cam_irq_controller_subscribe_irq(
|
|
|
- csid_hw->rx_irq_controller,
|
|
|
+ csid_hw->rx_cfg.err_irq_handle[CAM_IFE_CSID_RX_IRQ_STATUS_REG0] =
|
|
|
+ cam_irq_controller_subscribe_irq(
|
|
|
+ csid_hw->rx_irq_controller
|
|
|
+ [CAM_IFE_CSID_RX_IRQ_STATUS_REG0],
|
|
|
CAM_IRQ_PRIORITY_0,
|
|
|
&err_irq_mask,
|
|
|
csid_hw,
|
|
@@ -4286,8 +4343,8 @@ static int cam_ife_csid_ver2_csi2_irq_subscribe(struct cam_ife_csid_ver2_hw *csi
|
|
|
&tasklet_bh_api,
|
|
|
CAM_IRQ_EVT_GROUP_0);
|
|
|
|
|
|
- if (csid_hw->rx_cfg.err_irq_handle < 1) {
|
|
|
- CAM_ERR(CAM_ISP, "CSID[%u] RX err irq register fail",
|
|
|
+ if (csid_hw->rx_cfg.err_irq_handle[CAM_IFE_CSID_RX_IRQ_STATUS_REG0] < 1) {
|
|
|
+ CAM_ERR(CAM_ISP, "CSID[%d] RX err irq register fail",
|
|
|
csid_hw->hw_intf->hw_idx);
|
|
|
rc = -EINVAL;
|
|
|
goto unsub_rx;
|
|
@@ -4297,14 +4354,15 @@ static int cam_ife_csid_ver2_csi2_irq_subscribe(struct cam_ife_csid_ver2_hw *csi
|
|
|
|
|
|
unsub_rx:
|
|
|
if (csid_hw->rx_cfg.irq_handle)
|
|
|
- cam_irq_controller_unsubscribe_irq(csid_hw->rx_irq_controller,
|
|
|
- csid_hw->rx_cfg.irq_handle);
|
|
|
+ cam_irq_controller_unsubscribe_irq(
|
|
|
+ csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0],
|
|
|
+ csid_hw->rx_cfg.irq_handle);
|
|
|
csid_hw->rx_cfg.irq_handle = 0;
|
|
|
unreg_rx:
|
|
|
- cam_irq_controller_unregister_dependent(csid_hw->top_irq_controller,
|
|
|
- csid_hw->rx_irq_controller);
|
|
|
+ cam_irq_controller_unregister_dependent(csid_hw->top_irq_controller[top_index],
|
|
|
+ csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]);
|
|
|
unsub_top:
|
|
|
- cam_irq_controller_unsubscribe_irq(csid_hw->top_irq_controller,
|
|
|
+ cam_irq_controller_unsubscribe_irq(csid_hw->top_irq_controller[top_index],
|
|
|
csid_hw->rx_cfg.top_irq_handle);
|
|
|
csid_hw->rx_cfg.top_irq_handle = 0;
|
|
|
err:
|
|
@@ -4313,14 +4371,14 @@ err:
|
|
|
|
|
|
static int cam_ife_csid_ver2_enable_csi2(struct cam_ife_csid_ver2_hw *csid_hw)
|
|
|
{
|
|
|
- int rc = 0;
|
|
|
- struct cam_hw_soc_info *soc_info;
|
|
|
- const struct cam_ife_csid_ver2_reg_info *csid_reg;
|
|
|
- const struct cam_ife_csid_csi2_rx_reg_info *csi2_reg;
|
|
|
- uint32_t val = 0;
|
|
|
- void __iomem *mem_base;
|
|
|
- struct cam_ife_csid_rx_cfg *rx_cfg;
|
|
|
- int vc_full_width;
|
|
|
+ int rc = 0;
|
|
|
+ struct cam_hw_soc_info *soc_info;
|
|
|
+ const struct cam_ife_csid_ver2_reg_info *csid_reg;
|
|
|
+ const struct cam_ife_csid_ver2_csi2_rx_reg_info *csi2_reg;
|
|
|
+ uint32_t val = 0;
|
|
|
+ void __iomem *mem_base;
|
|
|
+ struct cam_ife_csid_ver2_rx_cfg *rx_cfg;
|
|
|
+ int vc_full_width;
|
|
|
|
|
|
if (csid_hw->flags.rx_enabled)
|
|
|
return 0;
|
|
@@ -4330,9 +4388,9 @@ static int cam_ife_csid_ver2_enable_csi2(struct cam_ife_csid_ver2_hw *csid_hw)
|
|
|
|
|
|
csid_reg = (struct cam_ife_csid_ver2_reg_info *)
|
|
|
csid_hw->core_info->csid_reg;
|
|
|
- csi2_reg = csid_reg->csi2_reg;
|
|
|
+ csi2_reg = csid_reg->csi2_reg;
|
|
|
soc_info = &csid_hw->hw_info->soc_info;
|
|
|
- rx_cfg = &csid_hw->rx_cfg;
|
|
|
+ rx_cfg = &csid_hw->rx_cfg;
|
|
|
mem_base = soc_info->reg_map[CAM_IFE_CSID_CLC_MEM_BASE_ID].mem_base;
|
|
|
|
|
|
/*Configure Rx cfg0 */
|
|
@@ -4376,8 +4434,9 @@ static int cam_ife_csid_ver2_enable_csi2(struct cam_ife_csid_ver2_hw *csid_hw)
|
|
|
CAM_DBG(CAM_ISP, "CSID[%u] rx_cfg1: 0x%x",
|
|
|
csid_hw->hw_intf->hw_idx, val);
|
|
|
|
|
|
- val = csi2_reg->fatal_err_mask | csi2_reg->part_fatal_err_mask |
|
|
|
- csi2_reg->non_fatal_err_mask;
|
|
|
+ val = csi2_reg->fatal_err_mask[CAM_IFE_CSID_RX_IRQ_STATUS_REG0] |
|
|
|
+ csi2_reg->part_fatal_err_mask[CAM_IFE_CSID_RX_IRQ_STATUS_REG0] |
|
|
|
+ csi2_reg->non_fatal_err_mask[CAM_IFE_CSID_RX_IRQ_STATUS_REG0];
|
|
|
|
|
|
if (csid_hw->rx_cfg.epd_supported &&
|
|
|
(csid_hw->rx_cfg.lane_type == CAM_ISP_LANE_TYPE_DPHY))
|
|
@@ -4507,8 +4566,8 @@ static int cam_ife_csid_ver2_enable_core(struct cam_ife_csid_ver2_hw *csid_hw)
|
|
|
struct cam_hw_soc_info *soc_info;
|
|
|
const struct cam_ife_csid_ver2_reg_info *csid_reg;
|
|
|
uint32_t clk_lvl;
|
|
|
- uint32_t irq_mask = 0;
|
|
|
struct cam_csid_soc_private *soc_private;
|
|
|
+ uint32_t irq_mask = 0;
|
|
|
|
|
|
csid_reg = (struct cam_ife_csid_ver2_reg_info *)csid_hw->core_info->csid_reg;
|
|
|
soc_info = &csid_hw->hw_info->soc_info;
|
|
@@ -4574,10 +4633,10 @@ static int cam_ife_csid_ver2_enable_core(struct cam_ife_csid_ver2_hw *csid_hw)
|
|
|
}
|
|
|
}
|
|
|
|
|
|
- irq_mask = csid_reg->cmn_reg->top_reset_irq_mask;
|
|
|
+ irq_mask = csid_reg->cmn_reg->top_reset_irq_mask[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0];
|
|
|
|
|
|
csid_hw->reset_irq_handle = cam_irq_controller_subscribe_irq(
|
|
|
- csid_hw->top_irq_controller,
|
|
|
+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
CAM_IRQ_PRIORITY_0,
|
|
|
&irq_mask,
|
|
|
csid_hw,
|
|
@@ -4619,7 +4678,7 @@ static int cam_ife_csid_ver2_enable_hw(
|
|
|
void __iomem *mem_base;
|
|
|
const struct cam_ife_csid_ver2_path_reg_info *path_reg = NULL;
|
|
|
uint32_t top_err_irq_mask = 0;
|
|
|
- uint32_t buf_done_irq_mask[CAM_IFE_CSID_IRQ_REGISTERS_MAX] = {0};
|
|
|
+ uint32_t buf_done_irq_mask = 0;
|
|
|
uint32_t top_info_irq_mask = 0;
|
|
|
|
|
|
if (csid_hw->flags.device_enabled) {
|
|
@@ -4634,10 +4693,11 @@ static int cam_ife_csid_ver2_enable_hw(
|
|
|
mem_base = soc_info->reg_map[CAM_IFE_CSID_CLC_MEM_BASE_ID].mem_base;
|
|
|
|
|
|
/* Clear IRQs */
|
|
|
- cam_io_w_mb(1, mem_base + csid_reg->cmn_reg->top_irq_clear_addr);
|
|
|
+ cam_io_w_mb(1, mem_base +
|
|
|
+ csid_reg->cmn_reg->top_irq_clear_addr[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]);
|
|
|
|
|
|
cam_io_w_mb(csid_reg->csi2_reg->irq_mask_all,
|
|
|
- mem_base + csid_reg->csi2_reg->irq_clear_addr);
|
|
|
+ mem_base + csid_reg->csi2_reg->irq_clear_addr[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]);
|
|
|
|
|
|
path_reg = csid_reg->path_reg[CAM_IFE_PIX_PATH_RES_IPP];
|
|
|
if (csid_reg->cmn_reg->num_pix)
|
|
@@ -4659,12 +4719,12 @@ static int cam_ife_csid_ver2_enable_hw(
|
|
|
/* Read hw version */
|
|
|
val = cam_io_r_mb(mem_base + csid_reg->cmn_reg->hw_version_addr);
|
|
|
|
|
|
- buf_done_irq_mask[CAM_IFE_CSID_IRQ_TOP_REG_STATUS0] =
|
|
|
+ buf_done_irq_mask =
|
|
|
csid_reg->cmn_reg->top_buf_done_irq_mask;
|
|
|
csid_hw->buf_done_irq_handle = cam_irq_controller_subscribe_irq(
|
|
|
- csid_hw->top_irq_controller,
|
|
|
+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
CAM_IRQ_PRIORITY_4,
|
|
|
- buf_done_irq_mask,
|
|
|
+ &buf_done_irq_mask,
|
|
|
csid_hw,
|
|
|
cam_ife_csid_ver2_handle_buf_done_irq,
|
|
|
NULL,
|
|
@@ -4679,9 +4739,10 @@ static int cam_ife_csid_ver2_enable_hw(
|
|
|
return -EINVAL;
|
|
|
}
|
|
|
|
|
|
- top_err_irq_mask = csid_reg->cmn_reg->top_err_irq_mask;
|
|
|
- csid_hw->top_err_irq_handle = cam_irq_controller_subscribe_irq(
|
|
|
- csid_hw->top_irq_controller,
|
|
|
+ top_err_irq_mask = csid_reg->cmn_reg->top_err_irq_mask[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0];
|
|
|
+ csid_hw->top_err_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0] =
|
|
|
+ cam_irq_controller_subscribe_irq(
|
|
|
+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
CAM_IRQ_PRIORITY_0,
|
|
|
&top_err_irq_mask,
|
|
|
csid_hw,
|
|
@@ -4691,18 +4752,20 @@ static int cam_ife_csid_ver2_enable_hw(
|
|
|
&tasklet_bh_api,
|
|
|
CAM_IRQ_EVT_GROUP_0);
|
|
|
|
|
|
- if (csid_hw->top_err_irq_handle < 1) {
|
|
|
- CAM_ERR(CAM_ISP, "CSID[%u] top error irq subscribe fail",
|
|
|
+ if (csid_hw->top_err_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0] < 1) {
|
|
|
+ CAM_ERR(CAM_ISP, "csid[%u] top error irq subscribe fail",
|
|
|
csid_hw->hw_intf->hw_idx);
|
|
|
rc = -EINVAL;
|
|
|
goto unsubscribe_buf_done;
|
|
|
}
|
|
|
|
|
|
- rc = cam_irq_controller_register_dependent(csid_hw->top_irq_controller,
|
|
|
- csid_hw->buf_done_irq_controller, buf_done_irq_mask);
|
|
|
+ rc = cam_irq_controller_register_dependent(csid_hw->top_irq_controller
|
|
|
+ [CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
+ csid_hw->buf_done_irq_controller, &buf_done_irq_mask);
|
|
|
|
|
|
if (rc) {
|
|
|
- cam_irq_controller_unsubscribe_irq(csid_hw->top_irq_controller,
|
|
|
+ cam_irq_controller_unsubscribe_irq(
|
|
|
+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
csid_hw->buf_done_irq_handle);
|
|
|
rc = -EINVAL;
|
|
|
goto unsubscribe_top_err;
|
|
@@ -4710,8 +4773,10 @@ static int cam_ife_csid_ver2_enable_hw(
|
|
|
|
|
|
if (csid_hw->debug_info.top_mask) {
|
|
|
top_info_irq_mask = csid_hw->debug_info.top_mask;
|
|
|
- csid_hw->top_info_irq_handle = cam_irq_controller_subscribe_irq(
|
|
|
- csid_hw->top_irq_controller,
|
|
|
+ csid_hw->top_info_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0] =
|
|
|
+ cam_irq_controller_subscribe_irq(
|
|
|
+ csid_hw->top_irq_controller
|
|
|
+ [CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
CAM_IRQ_PRIORITY_1,
|
|
|
&top_info_irq_mask,
|
|
|
csid_hw,
|
|
@@ -4721,7 +4786,7 @@ static int cam_ife_csid_ver2_enable_hw(
|
|
|
&tasklet_bh_api,
|
|
|
CAM_IRQ_EVT_GROUP_0);
|
|
|
|
|
|
- if (csid_hw->top_info_irq_handle < 1) {
|
|
|
+ if (csid_hw->top_info_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0] < 1) {
|
|
|
CAM_ERR(CAM_ISP, "CSID[%u] Subscribe Top Info Irq fail",
|
|
|
csid_hw->hw_intf->hw_idx);
|
|
|
rc = -EINVAL;
|
|
@@ -4737,11 +4802,14 @@ static int cam_ife_csid_ver2_enable_hw(
|
|
|
|
|
|
|
|
|
unsubscribe_top_err:
|
|
|
- cam_irq_controller_unsubscribe_irq(csid_hw->top_irq_controller,
|
|
|
- csid_hw->top_err_irq_handle);
|
|
|
- csid_hw->top_err_irq_handle = 0;
|
|
|
+ cam_irq_controller_unsubscribe_irq(
|
|
|
+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
+ csid_hw->top_err_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]);
|
|
|
+ csid_hw->top_err_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0] = 0;
|
|
|
+
|
|
|
unsubscribe_buf_done:
|
|
|
- cam_irq_controller_unsubscribe_irq(csid_hw->top_irq_controller,
|
|
|
+ cam_irq_controller_unsubscribe_irq(
|
|
|
+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
csid_hw->buf_done_irq_handle);
|
|
|
csid_hw->buf_done_irq_handle = 0;
|
|
|
return rc;
|
|
@@ -4815,11 +4883,11 @@ static int cam_ife_csid_ver2_disable_core(
|
|
|
|
|
|
/* Disable the top IRQ interrupt */
|
|
|
cam_io_w_mb(0, soc_info->reg_map[0].mem_base +
|
|
|
- csid_reg->cmn_reg->top_irq_mask_addr);
|
|
|
+ csid_reg->cmn_reg->top_irq_mask_addr[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]);
|
|
|
|
|
|
if (csid_hw->reset_irq_handle) {
|
|
|
rc = cam_irq_controller_unsubscribe_irq(
|
|
|
- csid_hw->top_irq_controller,
|
|
|
+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
csid_hw->reset_irq_handle);
|
|
|
if (rc)
|
|
|
CAM_WARN(CAM_ISP,
|
|
@@ -5234,7 +5302,7 @@ static void cam_ife_csid_ver2_maskout_all_irqs(
|
|
|
int i;
|
|
|
struct cam_hw_soc_info *soc_info;
|
|
|
const struct cam_ife_csid_ver2_reg_info *csid_reg;
|
|
|
- const struct cam_ife_csid_csi2_rx_reg_info *csi2_reg;
|
|
|
+ const struct cam_ife_csid_ver2_csi2_rx_reg_info *csi2_reg;
|
|
|
const struct cam_ife_csid_ver2_path_reg_info *path_reg = NULL;
|
|
|
void __iomem *mem_base;
|
|
|
struct cam_isp_resource_node *res;
|
|
@@ -5247,14 +5315,16 @@ static void cam_ife_csid_ver2_maskout_all_irqs(
|
|
|
|
|
|
/* Disable rx */
|
|
|
if (!csid_hw->flags.offline_mode)
|
|
|
- cam_io_w_mb(0x0, mem_base + csi2_reg->irq_mask_addr);
|
|
|
+ cam_io_w_mb(0x0,
|
|
|
+ mem_base + csi2_reg->irq_mask_addr[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]);
|
|
|
|
|
|
for (i = 0; i < csid_stop->num_res; i++) {
|
|
|
res = csid_stop->node_res[i];
|
|
|
path_reg = csid_reg->path_reg[res->res_id];
|
|
|
|
|
|
/* Disable path */
|
|
|
- cam_io_w_mb(0x0, mem_base + path_reg->irq_mask_addr);
|
|
|
+ cam_io_w_mb(0x0,
|
|
|
+ mem_base + path_reg->irq_mask_addr);
|
|
|
}
|
|
|
|
|
|
/* Disable buf done */
|
|
@@ -5262,8 +5332,8 @@ static void cam_ife_csid_ver2_maskout_all_irqs(
|
|
|
csid_reg->cmn_reg->buf_done_irq_mask_addr);
|
|
|
|
|
|
/* Disable top except rst_done */
|
|
|
- cam_io_w_mb(csid_reg->cmn_reg->top_reset_irq_mask,
|
|
|
- mem_base + csid_reg->cmn_reg->top_irq_mask_addr);
|
|
|
+ cam_io_w_mb(csid_reg->cmn_reg->top_reset_irq_mask[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
+ mem_base + csid_reg->cmn_reg->top_irq_mask_addr[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]);
|
|
|
}
|
|
|
|
|
|
int cam_ife_csid_ver2_stop(void *hw_priv,
|
|
@@ -5337,25 +5407,28 @@ int cam_ife_csid_ver2_stop(void *hw_priv,
|
|
|
}
|
|
|
if (csid_hw->buf_done_irq_handle) {
|
|
|
rc = cam_irq_controller_unsubscribe_irq(
|
|
|
- csid_hw->top_irq_controller,
|
|
|
+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
csid_hw->buf_done_irq_handle);
|
|
|
csid_hw->buf_done_irq_handle = 0;
|
|
|
|
|
|
- cam_irq_controller_unregister_dependent(csid_hw->top_irq_controller,
|
|
|
+ cam_irq_controller_unregister_dependent(
|
|
|
+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
csid_hw->buf_done_irq_controller);
|
|
|
}
|
|
|
|
|
|
- if (csid_hw->top_err_irq_handle) {
|
|
|
+ if (csid_hw->top_err_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]) {
|
|
|
rc = cam_irq_controller_unsubscribe_irq(
|
|
|
- csid_hw->top_irq_controller,
|
|
|
- csid_hw->top_err_irq_handle);
|
|
|
- csid_hw->top_err_irq_handle = 0;
|
|
|
+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
+ csid_hw->top_err_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]);
|
|
|
+ csid_hw->top_err_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0] = 0;
|
|
|
}
|
|
|
|
|
|
+
|
|
|
if (csid_hw->debug_info.top_mask) {
|
|
|
- cam_irq_controller_unsubscribe_irq(csid_hw->top_irq_controller,
|
|
|
- csid_hw->top_info_irq_handle);
|
|
|
- csid_hw->top_info_irq_handle = 0;
|
|
|
+ cam_irq_controller_unsubscribe_irq(
|
|
|
+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
+ csid_hw->top_info_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]);
|
|
|
+ csid_hw->top_info_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0] = 0;
|
|
|
}
|
|
|
|
|
|
cam_ife_csid_ver2_disable_csi2(false, csid_hw);
|
|
@@ -5977,7 +6050,7 @@ static int cam_ife_csid_ver2_mini_dump(
|
|
|
memcpy(&md_res->path_cfg, path_cfg, sizeof(*path_cfg));
|
|
|
}
|
|
|
|
|
|
- memcpy(&md->rx_cfg, &csid_hw->rx_cfg, sizeof(struct cam_ife_csid_rx_cfg));
|
|
|
+ memcpy(&md->rx_cfg, &csid_hw->rx_cfg, sizeof(struct cam_ife_csid_ver2_rx_cfg));
|
|
|
memcpy(&md->flags, &csid_hw->flags, sizeof(struct cam_ife_csid_hw_flags));
|
|
|
memcpy(md->cid_data, csid_hw->cid_data,
|
|
|
sizeof(struct cam_ife_csid_cid_data) * CAM_IFE_CSID_CID_MAX);
|
|
@@ -6475,7 +6548,8 @@ static irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
|
return IRQ_NONE;
|
|
|
|
|
|
return cam_irq_controller_handle_irq(irq_num,
|
|
|
- csid_hw->top_irq_controller, CAM_IRQ_EVT_GROUP_0);
|
|
|
+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
+ CAM_IRQ_EVT_GROUP_0);
|
|
|
}
|
|
|
|
|
|
static void cam_ife_csid_ver2_free_res(struct cam_ife_csid_ver2_hw *csid_hw)
|
|
@@ -6625,8 +6699,8 @@ static void cam_ife_csid_hw_deinit_irq(
|
|
|
unsigned long flags;
|
|
|
int i;
|
|
|
|
|
|
- cam_irq_controller_deinit(&csid_hw->top_irq_controller);
|
|
|
- cam_irq_controller_deinit(&csid_hw->rx_irq_controller);
|
|
|
+ cam_irq_controller_deinit(&csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]);
|
|
|
+ cam_irq_controller_deinit(&csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]);
|
|
|
cam_irq_controller_deinit(&csid_hw->buf_done_irq_controller);
|
|
|
|
|
|
for (i = 0; i < CAM_IFE_PIX_PATH_RES_MAX; i++) {
|
|
@@ -6664,8 +6738,9 @@ static int cam_ife_csid_hw_init_irq(
|
|
|
mem_base = soc_info->reg_map[CAM_IFE_CSID_CLC_MEM_BASE_ID].mem_base;
|
|
|
|
|
|
snprintf(name, CAM_CSID_IRQ_CTRL_NAME_LEN, "csid%d_top", csid_hw->hw_intf->hw_idx);
|
|
|
- rc = cam_irq_controller_init(name, mem_base, csid_reg->top_irq_reg_info,
|
|
|
- &csid_hw->top_irq_controller);
|
|
|
+ rc = cam_irq_controller_init(name, mem_base,
|
|
|
+ &csid_reg->top_irq_reg_info[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
+ &csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]);
|
|
|
|
|
|
if (rc) {
|
|
|
CAM_ERR(CAM_ISP,
|
|
@@ -6675,8 +6750,9 @@ static int cam_ife_csid_hw_init_irq(
|
|
|
}
|
|
|
|
|
|
snprintf(name, CAM_CSID_IRQ_CTRL_NAME_LEN, "csid%d_rx", csid_hw->hw_intf->hw_idx);
|
|
|
- rc = cam_irq_controller_init(name, mem_base, csid_reg->rx_irq_reg_info,
|
|
|
- &csid_hw->rx_irq_controller);
|
|
|
+ rc = cam_irq_controller_init(name, mem_base,
|
|
|
+ &csid_reg->rx_irq_reg_info[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
+ &csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]);
|
|
|
|
|
|
if (rc) {
|
|
|
CAM_ERR(CAM_ISP, "CSID:%u Failed to init CSID rx irq controller rc = %d",
|
|
@@ -6785,8 +6861,9 @@ int cam_ife_csid_ver2_irq_line_test(void *hw_priv)
|
|
|
csid_hw->hw_intf->hw_idx,
|
|
|
cam_io_r_mb(mem_base + csid_reg->cmn_reg->hw_version_addr));
|
|
|
|
|
|
- rc = cam_irq_controller_test_irq_line(csid_hw->top_irq_controller, "CSID:%u",
|
|
|
- csid_hw->hw_intf->hw_idx);
|
|
|
+ rc = cam_irq_controller_test_irq_line(
|
|
|
+ csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
|
|
|
+ "CSID:%d", csid_hw->hw_intf->hw_idx);
|
|
|
|
|
|
cam_ife_csid_disable_soc_resources(soc_info);
|
|
|
return rc;
|