msm: camera: isp: Refactoring top and rx irq related code

Refactoring top and rx irq related code, and add support
for multiple top and rx register.

CRs-Fixed: 3321317
Change-Id: Ib34485d8d7c08e2d3729920504819fe6edac6bf1
Signed-off-by: Ashish Bhimanpalliwar <[email protected]>

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid680.h

@@ -17,106 +17,110 @@
 
 #define CAM_CSID_VERSION_V680                 0x60080000
 
-static const struct cam_ife_csid_irq_desc cam_ife_csid_680_rx_irq_desc[] = {
-	{
-		.bitmask = BIT(0),
-		.desc = "DL0_EOT",
-	},
-	{
-		.bitmask = BIT(1),
-		.desc = "DL1_EOT",
-	},
-	{
-		.bitmask = BIT(2),
-		.desc = "DL2_EOT",
-	},
-	{
-		.bitmask = BIT(3),
-		.desc = "DL3_EOT",
-	},
-	{
-		.bitmask = BIT(4),
-		.desc = "DL0_SOT",
-	},
-	{
-		.bitmask = BIT(5),
-		.desc = "DL1_SOT",
-	},
-	{
-		.bitmask = BIT(6),
-		.desc = "DL2_SOT",
-	},
-	{
-		.bitmask = BIT(7),
-		.desc = "DL3_SOT",
-	},
-	{
-		.bitmask = BIT(8),
-		.desc = "LONG_PKT",
-	},
-	{
-		.bitmask = BIT(9),
-		.desc = "SHORT_PKT",
-	},
-	{
-		.bitmask = BIT(10),
-		.desc = "CPHY_PKT_HDR",
-	},
-	{
-		.bitmask = BIT(11),
-		.desc = "ERROR_CPHY_EOT_RECEPTION",
-	},
-	{
-		.bitmask = BIT(12),
-		.desc = "ERROR_CPHY_SOT_RECEPTION",
-	},
-	{
-		.bitmask = BIT(13),
-		.desc = "ERROR_CPHY_PH_CRC",
-	},
-	{
-		.bitmask = BIT(14),
-		.desc = "WARNING_ECC",
-	},
-	{
-		.bitmask = BIT(15),
-		.desc = "ERROR_LANE0_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(16),
-		.desc = "ERROR_LANE1_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(17),
-		.desc = "ERROR_LANE2_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(18),
-		.desc = "ERROR_LANE3_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(19),
-		.desc = "ERROR_CRC",
-	},
-	{
-		.bitmask = BIT(20),
-		.desc = "ERROR_ECC",
-	},
-	{
-		.bitmask = BIT(21),
-		.desc = "ERROR_MMAPPED_VC_DT",
-	},
-	{
-		.bitmask = BIT(22),
-		.desc = "ERROR_UNMAPPED_VC_DT",
-	},
-	{
-		.bitmask = BIT(23),
-		.desc = "ERROR_STREAM_UNDERFLOW",
-	},
+static uint32_t cam_ife_csid_680_num_top_regs[] = {0,};
+
+static const struct cam_ife_csid_irq_desc cam_ife_csid_680_rx_irq_desc[][32] = {
 	{
-		.bitmask = BIT(24),
-		.desc = "ERROR_UNBOUNDED_FRAME",
+		{
+			.bitmask = BIT(0),
+			.desc = "DL0_EOT",
+		},
+		{
+			.bitmask = BIT(1),
+			.desc = "DL1_EOT",
+		},
+		{
+			.bitmask = BIT(2),
+			.desc = "DL2_EOT",
+		},
+		{
+			.bitmask = BIT(3),
+			.desc = "DL3_EOT",
+		},
+		{
+			.bitmask = BIT(4),
+			.desc = "DL0_SOT",
+		},
+		{
+			.bitmask = BIT(5),
+			.desc = "DL1_SOT",
+		},
+		{
+			.bitmask = BIT(6),
+			.desc = "DL2_SOT",
+		},
+		{
+			.bitmask = BIT(7),
+			.desc = "DL3_SOT",
+		},
+		{
+			.bitmask = BIT(8),
+			.desc = "LONG_PKT",
+		},
+		{
+			.bitmask = BIT(9),
+			.desc = "SHORT_PKT",
+		},
+		{
+			.bitmask = BIT(10),
+			.desc = "CPHY_PKT_HDR",
+		},
+		{
+			.bitmask = BIT(11),
+			.desc = "ERROR_CPHY_EOT_RECEPTION",
+		},
+		{
+			.bitmask = BIT(12),
+			.desc = "ERROR_CPHY_SOT_RECEPTION",
+		},
+		{
+			.bitmask = BIT(13),
+			.desc = "ERROR_CPHY_PH_CRC",
+		},
+		{
+			.bitmask = BIT(14),
+			.desc = "WARNING_ECC",
+		},
+		{
+			.bitmask = BIT(15),
+			.desc = "ERROR_LANE0_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(16),
+			.desc = "ERROR_LANE1_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(17),
+			.desc = "ERROR_LANE2_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(18),
+			.desc = "ERROR_LANE3_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(19),
+			.desc = "ERROR_CRC",
+		},
+		{
+			.bitmask = BIT(20),
+			.desc = "ERROR_ECC",
+		},
+		{
+			.bitmask = BIT(21),
+			.desc = "ERROR_MMAPPED_VC_DT",
+		},
+		{
+			.bitmask = BIT(22),
+			.desc = "ERROR_UNMAPPED_VC_DT",
+		},
+		{
+			.bitmask = BIT(23),
+			.desc = "ERROR_STREAM_UNDERFLOW",
+		},
+		{
+			.bitmask = BIT(24),
+			.desc = "ERROR_UNBOUNDED_FRAME",
+		},
 	},
 };
 
@@ -309,19 +313,23 @@ static struct cam_irq_register_set cam_ife_csid_680_irq_reg_set[9] = {
 	},
 };
 
-static struct cam_irq_controller_reg_info cam_ife_csid_680_top_irq_reg_info = {
+static struct cam_irq_controller_reg_info cam_ife_csid_680_top_irq_reg_info[] = {
+	{
 	.num_registers = 1,
 	.irq_reg_set = &cam_ife_csid_680_irq_reg_set[CAM_IFE_CSID_IRQ_REG_TOP],
 	.global_irq_cmd_offset = 0x00000014,
 	.global_clear_bitmask  = 0x00000001,
 	.global_set_bitmask    = 0x00000010,
 	.clear_all_bitmask     = 0xFFFFFFFF,
+	},
 };
 
-static struct cam_irq_controller_reg_info cam_ife_csid_680_rx_irq_reg_info = {
+static struct cam_irq_controller_reg_info cam_ife_csid_680_rx_irq_reg_info[] = {
+	{
 	.num_registers = 1,
 	.irq_reg_set = &cam_ife_csid_680_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RX],
 	.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
 };
 
 static struct cam_irq_controller_reg_info cam_ife_csid_680_path_irq_reg_info[7] = {
@@ -487,7 +495,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                  = 0x400000,
 		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x10001,
-		.top_irq_mask                     = 0x10,
+		.top_irq_mask                     = {0x10,},
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
 };
@@ -587,7 +595,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.fatal_err_mask                   = 0x186004,
 		.non_fatal_err_mask               = 0x10000000,
 		.rup_aup_mask                     = 0x40004,
-		.top_irq_mask                     = 0x40,
+		.top_irq_mask                     = {0x40,},
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
 		.crop_drop_enable                 = false,
@@ -686,7 +694,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                  = 0x400000,
 		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x100010,
-		.top_irq_mask                     = 0x100,
+		.top_irq_mask                     = {0x100,},
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
 };
@@ -784,7 +792,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                  = 0x400000,
 		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x200020,
-		.top_irq_mask                     = 0x200,
+		.top_irq_mask                     = {0x200,},
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
 };
@@ -882,7 +890,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                  = 0x400000,
 		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x400040,
-		.top_irq_mask                     = 0x400,
+		.top_irq_mask                     = {0x400,},
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
 };
@@ -980,7 +988,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                  = 0x400000,
 		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x800080,
-		.top_irq_mask                     = 0x800,
+		.top_irq_mask                     = {0x800,},
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
 };
@@ -1078,17 +1086,17 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                 = 0x400000,
 		.eof_irq_mask                    = 0x8,
 		.rup_aup_mask                    = 0x1000100,
-		.top_irq_mask                    = 0x1000,
+		.top_irq_mask                    = {0x1000,},
 		.epoch0_shift_val                = 16,
 		.epoch1_shift_val                = 0,
 };
 
-static struct cam_ife_csid_csi2_rx_reg_info
+static struct cam_ife_csid_ver2_csi2_rx_reg_info
 	cam_ife_csid_680_csi2_reg_info = {
-		.irq_status_addr                 = 0x9C,
-		.irq_mask_addr                   = 0xA0,
-		.irq_clear_addr                  = 0xA4,
-		.irq_set_addr                    = 0xA8,
+		.irq_status_addr                 = {0x9C,},
+		.irq_mask_addr                   = {0xA0,},
+		.irq_clear_addr                  = {0xA4,},
+		.irq_set_addr                    = {0xA8,},
 		/*CSI2 rx control */
 		.cfg0_addr                       = 0x200,
 		.cfg1_addr                       = 0x204,
@@ -1155,10 +1163,10 @@ static struct cam_ife_csid_csi2_rx_reg_info
 		.short_pkt_strobe_rst_shift      = 1,
 		.cphy_pkt_strobe_rst_shift       = 2,
 		.unmapped_pkt_strobe_rst_shift   = 3,
-		.fatal_err_mask                  = 0x19FA800,
-		.part_fatal_err_mask             = 0x0001000,
-		.non_fatal_err_mask              = 0x0200000,
-		.top_irq_mask                    = 0x4,
+		.fatal_err_mask                  = {0x19FA800,},
+		.part_fatal_err_mask             = {0x0001000,},
+		.non_fatal_err_mask              = {0x0200000,},
+		.top_irq_mask                    = {0x4,},
 };
 
 static struct cam_ife_csid_ver2_common_reg_info
@@ -1172,10 +1180,10 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.rup_aup_cmd_addr                        = 0x18,
 	.offline_cmd_addr                        = 0x1C,
 	.shdr_master_slave_cfg_addr              = 0x20,
-	.top_irq_status_addr                     = 0x7C,
-	.top_irq_mask_addr                       = 0x80,
-	.top_irq_clear_addr                      = 0x84,
-	.top_irq_set_addr                        = 0x88,
+	.top_irq_status_addr                     = {0x7C,},
+	.top_irq_mask_addr                       = {0x80,},
+	.top_irq_clear_addr                      = {0x84,},
+	.top_irq_set_addr                        = {0x88,},
 	.buf_done_irq_status_addr                = 0x8C,
 	.buf_done_irq_mask_addr                  = 0x90,
 	.buf_done_irq_clear_addr                 = 0x94,
@@ -1226,7 +1234,9 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.ipp_irq_mask_all                        = 0x7FFF,
 	.rdi_irq_mask_all                        = 0x7FFF,
 	.ppp_irq_mask_all                        = 0xFFFF,
-	.top_err_irq_mask                        = 0x0,
+	.top_err_irq_mask = {
+		0x0,
+	},
 	.rst_loc_path_only_val                   = 0x0,
 	.rst_loc_complete_csid_val               = 0x1,
 	.rst_mode_frame_boundary_val             = 0x0,
@@ -1245,7 +1255,9 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.format_measure_height_shift_val         = 0x10,
 	.format_measure_width_mask_val           = 0xFFFF,
 	.format_measure_width_shift_val          = 0x0,
-	.top_reset_irq_mask                      = 0x1,
+	.top_reset_irq_mask  = {
+		0x1,
+	},
 	.top_buf_done_irq_mask                   = 0x2000,
 	.phy_sel_base_idx                        = 1,
 	.camif_irq_support                       = true,
@@ -1277,8 +1289,8 @@ static struct cam_ife_csid_ver2_top_reg_info
 };
 
 static struct cam_ife_csid_ver2_reg_info cam_ife_csid_680_reg_info = {
-	.top_irq_reg_info      = &cam_ife_csid_680_top_irq_reg_info,
-	.rx_irq_reg_info       = &cam_ife_csid_680_rx_irq_reg_info,
+	.top_irq_reg_info      = cam_ife_csid_680_top_irq_reg_info,
+	.rx_irq_reg_info       = cam_ife_csid_680_rx_irq_reg_info,
 	.path_irq_reg_info     = {
 		&cam_ife_csid_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_0],
 		&cam_ife_csid_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_1],
@@ -1330,7 +1342,10 @@ static struct cam_ife_csid_ver2_reg_info cam_ife_csid_680_reg_info = {
 	},
 	.need_top_cfg = 0x1,
 	.csid_cust_node_map = {0x1, 0x0, 0x2},
-	.rx_irq_desc        = cam_ife_csid_680_rx_irq_desc,
+	.rx_irq_desc        = &cam_ife_csid_680_rx_irq_desc,
 	.path_irq_desc      = cam_ife_csid_680_path_irq_desc,
+	.num_top_err_irqs   = cam_ife_csid_680_num_top_regs,
+	.num_top_regs       = 1,
+	.num_rx_regs        = 1,
 };
 #endif /*_CAM_IFE_CSID_680_H_ */

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid680_110.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_IFE_CSID_680_110_H_
@@ -14,9 +14,11 @@
 #include "cam_ife_csid_hw_ver2.h"
 #include "cam_irq_controller.h"
 
+static uint32_t cam_ife_csid_680_110_num_top_regs[] = {0,};
+
 static struct cam_ife_csid_ver2_reg_info cam_ife_csid_680_110_reg_info = {
-	.top_irq_reg_info      = &cam_ife_csid_680_top_irq_reg_info,
-	.rx_irq_reg_info       = &cam_ife_csid_680_rx_irq_reg_info,
+	.top_irq_reg_info      = cam_ife_csid_680_top_irq_reg_info,
+	.rx_irq_reg_info       = cam_ife_csid_680_rx_irq_reg_info,
 	.path_irq_reg_info     = {
 		&cam_ife_csid_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_0],
 		&cam_ife_csid_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_1],
@@ -68,7 +70,10 @@ static struct cam_ife_csid_ver2_reg_info cam_ife_csid_680_110_reg_info = {
 	},
 	.need_top_cfg = 0x1,
 	.csid_cust_node_map = {0x1, 0x0, 0x2},
-	.rx_irq_desc        = cam_ife_csid_680_rx_irq_desc,
+	.rx_irq_desc        = &cam_ife_csid_680_rx_irq_desc,
 	.path_irq_desc      = cam_ife_csid_680_path_irq_desc,
+	.num_top_err_irqs   = cam_ife_csid_680_110_num_top_regs,
+	.num_top_regs       = 1,
+	.num_rx_regs        = 1,
 };
 #endif /*_CAM_IFE_CSID_680_110_H_ */

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid780.h

@@ -17,106 +17,108 @@
 
 #define CAM_CSID_VERSION_V780                 0x70080000
 
-static const struct cam_ife_csid_irq_desc cam_ife_csid_780_rx_irq_desc[] = {
+static const struct cam_ife_csid_irq_desc cam_ife_csid_780_rx_irq_desc[][32] = {
 	{
-		.bitmask = BIT(0),
-		.desc = "DL0_EOT",
-	},
-	{
-		.bitmask = BIT(1),
-		.desc = "DL1_EOT",
-	},
-	{
-		.bitmask = BIT(2),
-		.desc = "DL2_EOT",
-	},
-	{
-		.bitmask = BIT(3),
-		.desc = "DL3_EOT",
-	},
-	{
-		.bitmask = BIT(4),
-		.desc = "DL0_SOT",
-	},
-	{
-		.bitmask = BIT(5),
-		.desc = "DL1_SOT",
-	},
-	{
-		.bitmask = BIT(6),
-		.desc = "DL2_SOT",
-	},
-	{
-		.bitmask = BIT(7),
-		.desc = "DL3_SOT",
-	},
-	{
-		.bitmask = BIT(8),
-		.desc = "LONG_PKT",
-	},
-	{
-		.bitmask = BIT(9),
-		.desc = "SHORT_PKT",
-	},
-	{
-		.bitmask = BIT(10),
-		.desc = "CPHY_PKT_HDR",
-	},
-	{
-		.bitmask = BIT(11),
-		.desc = "ERROR_CPHY_EOT_RECEPTION",
-	},
-	{
-		.bitmask = BIT(12),
-		.desc = "ERROR_CPHY_SOT_RECEPTION",
-	},
-	{
-		.bitmask = BIT(13),
-		.desc = "ERROR_CPHY_PH_CRC",
-	},
-	{
-		.bitmask = BIT(14),
-		.desc = "WARNING_ECC",
-	},
-	{
-		.bitmask = BIT(15),
-		.desc = "ERROR_LANE0_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(16),
-		.desc = "ERROR_LANE1_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(17),
-		.desc = "ERROR_LANE2_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(18),
-		.desc = "ERROR_LANE3_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(19),
-		.desc = "ERROR_CRC",
-	},
-	{
-		.bitmask = BIT(20),
-		.desc = "ERROR_ECC",
-	},
-	{
-		.bitmask = BIT(21),
-		.desc = "ERROR_MMAPPED_VC_DT",
-	},
-	{
-		.bitmask = BIT(22),
-		.desc = "ERROR_UNMAPPED_VC_DT",
-	},
-	{
-		.bitmask = BIT(23),
-		.desc = "ERROR_STREAM_UNDERFLOW",
-	},
-	{
-		.bitmask = BIT(24),
-		.desc = "ERROR_UNBOUNDED_FRAME",
+		{
+			.bitmask = BIT(0),
+			.desc = "DL0_EOT",
+		},
+		{
+			.bitmask = BIT(1),
+			.desc = "DL1_EOT",
+		},
+		{
+			.bitmask = BIT(2),
+			.desc = "DL2_EOT",
+		},
+		{
+			.bitmask = BIT(3),
+			.desc = "DL3_EOT",
+		},
+		{
+			.bitmask = BIT(4),
+			.desc = "DL0_SOT",
+		},
+		{
+			.bitmask = BIT(5),
+			.desc = "DL1_SOT",
+		},
+		{
+			.bitmask = BIT(6),
+			.desc = "DL2_SOT",
+		},
+		{
+			.bitmask = BIT(7),
+			.desc = "DL3_SOT",
+		},
+		{
+			.bitmask = BIT(8),
+			.desc = "LONG_PKT",
+		},
+		{
+			.bitmask = BIT(9),
+			.desc = "SHORT_PKT",
+		},
+		{
+			.bitmask = BIT(10),
+			.desc = "CPHY_PKT_HDR",
+		},
+		{
+			.bitmask = BIT(11),
+			.desc = "ERROR_CPHY_EOT_RECEPTION",
+		},
+		{
+			.bitmask = BIT(12),
+			.desc = "ERROR_CPHY_SOT_RECEPTION",
+		},
+		{
+			.bitmask = BIT(13),
+			.desc = "ERROR_CPHY_PH_CRC",
+		},
+		{
+			.bitmask = BIT(14),
+			.desc = "WARNING_ECC",
+		},
+		{
+			.bitmask = BIT(15),
+			.desc = "ERROR_LANE0_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(16),
+			.desc = "ERROR_LANE1_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(17),
+			.desc = "ERROR_LANE2_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(18),
+			.desc = "ERROR_LANE3_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(19),
+			.desc = "ERROR_CRC",
+		},
+		{
+			.bitmask = BIT(20),
+			.desc = "ERROR_ECC",
+		},
+		{
+			.bitmask = BIT(21),
+			.desc = "ERROR_MMAPPED_VC_DT",
+		},
+		{
+			.bitmask = BIT(22),
+			.desc = "ERROR_UNMAPPED_VC_DT",
+		},
+		{
+			.bitmask = BIT(23),
+			.desc = "ERROR_STREAM_UNDERFLOW",
+		},
+		{
+			.bitmask = BIT(24),
+			.desc = "ERROR_UNBOUNDED_FRAME",
+		},
 	},
 };
 
@@ -251,31 +253,33 @@ static const struct cam_ife_csid_irq_desc cam_ife_csid_780_path_irq_desc[] = {
 	},
 };
 
-static const struct cam_ife_csid_top_irq_desc cam_ife_csid_780_top_irq_desc[] = {
-	{
-		.bitmask  = BIT(1),
-		.err_type = CAM_ISP_HW_ERROR_CSID_SENSOR_SWITCH_ERROR,
-		.err_name = "FATAL_SENSOR_SWITCHING_IRQ",
-		.desc = "Fatal Error during dynamically switching between 2 sensors",
-	},
+static const struct cam_ife_csid_top_irq_desc cam_ife_csid_780_top_irq_desc[][32] = {
 	{
-		.bitmask  = BIT(18),
-		.err_name = "ERROR_NO_VOTE_DN",
-		.desc = "vote_up is asserted before IDLE is encountered in a frame",
-	},
-	{
-		.bitmask  = BIT(19),
-		.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
-		.err_name = "ERROR_VOTE_UP_LATE",
-		.desc = "vote_up is asserted at the same time as an SOF",
-		.err_handler = cam_ife_csid_hw_ver2_drv_err_handler,
-	},
-	{
-		.bitmask  = BIT(20),
-		.err_type = CAM_ISP_HW_ERROR_CSID_OUTPUT_FIFO_OVERFLOW,
-		.err_name = "ERROR_RDI_LINE_BUFFER_CONFLICT",
-		.desc = "Two or more RDIs programmed to access the shared line buffer",
-		.err_handler = cam_ife_csid_hw_ver2_rdi_line_buffer_conflict_handler,
+		{
+			.bitmask  = BIT(1),
+			.err_type = CAM_ISP_HW_ERROR_CSID_SENSOR_SWITCH_ERROR,
+			.err_name = "FATAL_SENSOR_SWITCHING_IRQ",
+			.desc = "Fatal Error during dynamically switching between 2 sensors",
+		},
+		{
+			.bitmask  = BIT(18),
+			.err_name = "ERROR_NO_VOTE_DN",
+			.desc = "vote_up is asserted before IDLE is encountered in a frame",
+		},
+		{
+			.bitmask  = BIT(19),
+			.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
+			.err_name = "ERROR_VOTE_UP_LATE",
+			.desc = "vote_up is asserted at the same time as an SOF",
+			.err_handler = cam_ife_csid_hw_ver2_drv_err_handler,
+		},
+		{
+			.bitmask  = BIT(20),
+			.err_type = CAM_ISP_HW_ERROR_CSID_OUTPUT_FIFO_OVERFLOW,
+			.err_name = "ERROR_RDI_LINE_BUFFER_CONFLICT",
+			.desc = "Two or more RDIs programmed to access the shared line buffer",
+			.err_handler = cam_ife_csid_hw_ver2_rdi_line_buffer_conflict_handler,
+		},
 	},
 };
 
@@ -339,19 +343,25 @@ static struct cam_irq_register_set cam_ife_csid_780_irq_reg_set[9] = {
 	},
 };
 
-static struct cam_irq_controller_reg_info cam_ife_csid_780_top_irq_reg_info = {
+static struct cam_irq_controller_reg_info cam_ife_csid_780_top_irq_reg_info[] = {
+	{
 	.num_registers = 1,
 	.irq_reg_set = &cam_ife_csid_780_irq_reg_set[CAM_IFE_CSID_IRQ_REG_TOP],
 	.global_irq_cmd_offset = 0x00000014,
 	.global_clear_bitmask  = 0x00000001,
 	.global_set_bitmask    = 0x00000010,
 	.clear_all_bitmask     = 0xFFFFFFFF,
+	},
 };
 
-static struct cam_irq_controller_reg_info cam_ife_csid_780_rx_irq_reg_info = {
+static uint32_t cam_ife_csid_780_num_top_regs[] = {ARRAY_SIZE(cam_ife_csid_780_top_irq_reg_info),};
+
+static struct cam_irq_controller_reg_info cam_ife_csid_780_rx_irq_reg_info[] = {
+	{
 	.num_registers = 1,
 	.irq_reg_set = &cam_ife_csid_780_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RX],
 	.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
 };
 
 static struct cam_irq_controller_reg_info cam_ife_csid_780_path_irq_reg_info[7] = {
@@ -520,7 +530,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                  = 0x400000,
 		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x10001,
-		.top_irq_mask                     = 0x10,
+		.top_irq_mask                     = {0x10,},
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
 };
@@ -621,7 +631,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.fatal_err_mask                   = 0x20186001,
 		.non_fatal_err_mask               = 0x12000006,
 		.rup_aup_mask                     = 0x40004,
-		.top_irq_mask                     = 0x40,
+		.top_irq_mask                     = {0x40,},
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
 		.sof_retiming_dis_shift           = 5,
@@ -728,7 +738,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                  = 0x400000,
 		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x100010,
-		.top_irq_mask                     = 0x100,
+		.top_irq_mask                     = {0x100,},
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
 		.pix_store_en_shift_val           = 10,
@@ -836,7 +846,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                  = 0x400000,
 		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x200020,
-		.top_irq_mask                     = 0x200,
+		.top_irq_mask                     = {0x200,},
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
 		.pix_store_en_shift_val           = 10,
@@ -943,7 +953,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                  = 0x400000,
 		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x400040,
-		.top_irq_mask                     = 0x400,
+		.top_irq_mask                     = {0x400,},
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
 		.pix_store_en_shift_val           = 10,
@@ -1048,7 +1058,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                  = 0x400000,
 		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x800080,
-		.top_irq_mask                     = 0x800,
+		.top_irq_mask                     = {0x800,},
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
 		.sof_retiming_dis_shift           = 5,
@@ -1152,18 +1162,18 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                 = 0x400000,
 		.eof_irq_mask                    = 0x8,
 		.rup_aup_mask                    = 0x1000100,
-		.top_irq_mask                    = 0x1000,
+		.top_irq_mask                    = {0x1000,},
 		.epoch0_shift_val                = 16,
 		.epoch1_shift_val                = 0,
 		.sof_retiming_dis_shift          = 5,
 };
 
-static struct cam_ife_csid_csi2_rx_reg_info
+static struct cam_ife_csid_ver2_csi2_rx_reg_info
 	cam_ife_csid_780_csi2_reg_info = {
-		.irq_status_addr                 = 0x9C,
-		.irq_mask_addr                   = 0xA0,
-		.irq_clear_addr                  = 0xA4,
-		.irq_set_addr                    = 0xA8,
+		.irq_status_addr                 = {0x9C,},
+		.irq_mask_addr                   = {0xA0,},
+		.irq_clear_addr                  = {0xA4,},
+		.irq_set_addr                    = {0xA8,},
 		/*CSI2 rx control */
 		.cfg0_addr                       = 0x200,
 		.cfg1_addr                       = 0x204,
@@ -1232,10 +1242,10 @@ static struct cam_ife_csid_csi2_rx_reg_info
 		.short_pkt_strobe_rst_shift      = 1,
 		.cphy_pkt_strobe_rst_shift       = 2,
 		.unmapped_pkt_strobe_rst_shift   = 3,
-		.fatal_err_mask                  = 0x19FA800,
-		.part_fatal_err_mask             = 0x0001000,
-		.non_fatal_err_mask              = 0x0200000,
-		.top_irq_mask                    = 0x4,
+		.fatal_err_mask                  = {0x19FA800,},
+		.part_fatal_err_mask             = {0x0001000,},
+		.non_fatal_err_mask              = {0x0200000,},
+		.top_irq_mask                    = {0x4,},
 };
 
 static struct cam_ife_csid_ver2_common_reg_info
@@ -1249,10 +1259,10 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.rup_aup_cmd_addr                        = 0x18,
 	.offline_cmd_addr                        = 0x1C,
 	.shdr_master_slave_cfg_addr              = 0x20,
-	.top_irq_status_addr                     = 0x7C,
-	.top_irq_mask_addr                       = 0x80,
-	.top_irq_clear_addr                      = 0x84,
-	.top_irq_set_addr                        = 0x88,
+	.top_irq_status_addr                     = {0x7C,},
+	.top_irq_mask_addr                       = {0x80,},
+	.top_irq_clear_addr                      = {0x84,},
+	.top_irq_set_addr                        = {0x88,},
 	.buf_done_irq_status_addr                = 0x8C,
 	.buf_done_irq_mask_addr                  = 0x90,
 	.buf_done_irq_clear_addr                 = 0x94,
@@ -1315,7 +1325,7 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.ipp_irq_mask_all                        = 0x7FFF,
 	.rdi_irq_mask_all                        = 0x7FFF,
 	.ppp_irq_mask_all                        = 0xFFFF,
-	.top_err_irq_mask                        = 0x180002,
+	.top_err_irq_mask                        = {0x180002,},
 	.rst_loc_path_only_val                   = 0x0,
 	.rst_loc_complete_csid_val               = 0x1,
 	.rst_mode_frame_boundary_val             = 0x0,
@@ -1324,7 +1334,7 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.rst_cmd_sw_reset_complete_val           = 0x2,
 	.rst_cmd_irq_ctrl_only_val               = 0x4,
 	.timestamp_strobe_val                    = 0x2,
-	.top_reset_irq_mask                      = 0x1,
+	.top_reset_irq_mask                      = {0x1,},
 	.rst_location_shift_val                  = 4,
 	.rst_mode_shift_val                      = 0,
 	.epoch_factor                            = 50,
@@ -1392,8 +1402,8 @@ static struct cam_ife_csid_ver2_top_reg_info
 };
 
 static struct cam_ife_csid_ver2_reg_info cam_ife_csid_780_reg_info = {
-	.top_irq_reg_info      = &cam_ife_csid_780_top_irq_reg_info,
-	.rx_irq_reg_info       = &cam_ife_csid_780_rx_irq_reg_info,
+	.top_irq_reg_info      = cam_ife_csid_780_top_irq_reg_info,
+	.rx_irq_reg_info       = cam_ife_csid_780_rx_irq_reg_info,
 	.path_irq_reg_info     = {
 		&cam_ife_csid_780_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_0],
 		&cam_ife_csid_780_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_1],
@@ -1445,9 +1455,11 @@ static struct cam_ife_csid_ver2_reg_info cam_ife_csid_780_reg_info = {
 	},
 	.need_top_cfg = 0x1,
 	.csid_cust_node_map = {0x1, 0x0, 0x2},
-	.rx_irq_desc        = cam_ife_csid_780_rx_irq_desc,
+	.rx_irq_desc        = &cam_ife_csid_780_rx_irq_desc,
 	.path_irq_desc      = cam_ife_csid_780_path_irq_desc,
-	.top_irq_desc       = cam_ife_csid_780_top_irq_desc,
-	.num_top_err_irqs   = ARRAY_SIZE(cam_ife_csid_780_top_irq_desc),
+	.top_irq_desc       = &cam_ife_csid_780_top_irq_desc,
+	.num_top_err_irqs   = cam_ife_csid_780_num_top_regs,
+	.num_top_regs       = 1,
+	.num_rx_regs       = 1,
 };
 #endif /*_CAM_IFE_CSID_780_H_ */

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid880.h

@@ -19,114 +19,116 @@
 
 /* Offsets might not match due to csid secure regs at beginning of reg space */
 
-static const struct cam_ife_csid_irq_desc cam_ife_csid_880_rx_irq_desc[] = {
+static const struct cam_ife_csid_irq_desc cam_ife_csid_880_rx_irq_desc[][32] = {
 	{
-		.bitmask = BIT(0),
-		.desc = "DL0_EOT",
-	},
-	{
-		.bitmask = BIT(1),
-		.desc = "DL1_EOT",
-	},
-	{
-		.bitmask = BIT(2),
-		.desc = "DL2_EOT",
-	},
-	{
-		.bitmask = BIT(3),
-		.desc = "DL3_EOT",
-	},
-	{
-		.bitmask = BIT(4),
-		.desc = "DL0_SOT",
-	},
-	{
-		.bitmask = BIT(5),
-		.desc = "DL1_SOT",
-	},
-	{
-		.bitmask = BIT(6),
-		.desc = "DL2_SOT",
-	},
-	{
-		.bitmask = BIT(7),
-		.desc = "DL3_SOT",
-	},
-	{
-		.bitmask = BIT(8),
-		.desc = "LONG_PKT",
-	},
-	{
-		.bitmask = BIT(9),
-		.desc = "SHORT_PKT",
-	},
-	{
-		.bitmask = BIT(10),
-		.desc = "CPHY_PKT_HDR",
-	},
-	{
-		.bitmask = BIT(11),
-		.desc = "ERROR_CPHY_EOT_RECEPTION",
-	},
-	{
-		.bitmask = BIT(12),
-		.desc = "ERROR_CPHY_SOT_RECEPTION",
-	},
-	{
-		.bitmask = BIT(13),
-		.desc = "ERROR_CPHY_PH_CRC",
-	},
-	{
-		.bitmask = BIT(14),
-		.desc = "WARNING_ECC",
-	},
-	{
-		.bitmask = BIT(15),
-		.desc = "ERROR_LANE0_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(16),
-		.desc = "ERROR_LANE1_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(17),
-		.desc = "ERROR_LANE2_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(18),
-		.desc = "ERROR_LANE3_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(19),
-		.desc = "ERROR_CRC",
-	},
-	{
-		.bitmask = BIT(20),
-		.desc = "ERROR_ECC",
-	},
-	{
-		.bitmask = BIT(21),
-		.desc = "ERROR_MMAPPED_VC_DT",
-	},
-	{
-		.bitmask = BIT(22),
-		.desc = "ERROR_UNMAPPED_VC_DT",
-	},
-	{
-		.bitmask = BIT(23),
-		.desc = "ERROR_STREAM_UNDERFLOW",
-	},
-	{
-		.bitmask = BIT(24),
-		.desc = "ERROR_UNBOUNDED_FRAME",
-	},
-	{
-		.bitmask = BIT(25),
-		.desc = "ERROR_ILLEGAL_PROGRAMMING_IRQ",
-	},
-	{
-		.bitmask = BIT(26),
-		.desc = "INFO_SENSOR_MODE_ID_CHANGE_IRQ",
+		{
+			.bitmask = BIT(0),
+			.desc = "DL0_EOT",
+		},
+		{
+			.bitmask = BIT(1),
+			.desc = "DL1_EOT",
+		},
+		{
+			.bitmask = BIT(2),
+			.desc = "DL2_EOT",
+		},
+		{
+			.bitmask = BIT(3),
+			.desc = "DL3_EOT",
+		},
+		{
+			.bitmask = BIT(4),
+			.desc = "DL0_SOT",
+		},
+		{
+			.bitmask = BIT(5),
+			.desc = "DL1_SOT",
+		},
+		{
+			.bitmask = BIT(6),
+			.desc = "DL2_SOT",
+		},
+		{
+			.bitmask = BIT(7),
+			.desc = "DL3_SOT",
+		},
+		{
+			.bitmask = BIT(8),
+			.desc = "LONG_PKT",
+		},
+		{
+			.bitmask = BIT(9),
+			.desc = "SHORT_PKT",
+		},
+		{
+			.bitmask = BIT(10),
+			.desc = "CPHY_PKT_HDR",
+		},
+		{
+			.bitmask = BIT(11),
+			.desc = "ERROR_CPHY_EOT_RECEPTION",
+		},
+		{
+			.bitmask = BIT(12),
+			.desc = "ERROR_CPHY_SOT_RECEPTION",
+		},
+		{
+			.bitmask = BIT(13),
+			.desc = "ERROR_CPHY_PH_CRC",
+		},
+		{
+			.bitmask = BIT(14),
+			.desc = "WARNING_ECC",
+		},
+		{
+			.bitmask = BIT(15),
+			.desc = "ERROR_LANE0_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(16),
+			.desc = "ERROR_LANE1_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(17),
+			.desc = "ERROR_LANE2_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(18),
+			.desc = "ERROR_LANE3_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(19),
+			.desc = "ERROR_CRC",
+		},
+		{
+			.bitmask = BIT(20),
+			.desc = "ERROR_ECC",
+		},
+		{
+			.bitmask = BIT(21),
+			.desc = "ERROR_MMAPPED_VC_DT",
+		},
+		{
+			.bitmask = BIT(22),
+			.desc = "ERROR_UNMAPPED_VC_DT",
+		},
+		{
+			.bitmask = BIT(23),
+			.desc = "ERROR_STREAM_UNDERFLOW",
+		},
+		{
+			.bitmask = BIT(24),
+			.desc = "ERROR_UNBOUNDED_FRAME",
+		},
+		{
+			.bitmask = BIT(25),
+			.desc = "ERROR_ILLEGAL_PROGRAMMING_IRQ",
+		},
+		{
+			.bitmask = BIT(26),
+			.desc = "INFO_SENSOR_MODE_ID_CHANGE_IRQ",
+		},
 	},
 };
 
@@ -261,34 +263,40 @@ static const struct cam_ife_csid_irq_desc cam_ife_csid_880_path_irq_desc[] = {
 	},
 };
 
-static const struct cam_ife_csid_top_irq_desc cam_ife_csid_880_top_irq_desc[] = {
+static const struct cam_ife_csid_top_irq_desc cam_ife_csid_880_top_irq_desc[][32] = {
 	{
-		.bitmask  = BIT(1),
-		.err_type = CAM_ISP_HW_ERROR_CSID_SENSOR_SWITCH_ERROR,
-		.err_name = "FATAL_SENSOR_SWITCHING_IRQ",
-		.desc = "Fatal Error during dynamically switching between 2 sensors",
-	},
-	{
-		.bitmask  = BIT(18),
-		.err_name = "ERROR_NO_VOTE_DN",
-		.desc = "vote_up is asserted before IDLE is encountered in a frame",
-	},
-	{
-		.bitmask  = BIT(19),
-		.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
-		.err_name = "ERROR_VOTE_UP_LATE",
-		.desc = "vote_up is asserted at the same time as an SOF",
-		.err_handler = cam_ife_csid_hw_ver2_drv_err_handler,
-	},
-	{
-		.bitmask  = BIT(20),
-		.err_type = CAM_ISP_HW_ERROR_CSID_OUTPUT_FIFO_OVERFLOW,
-		.err_name = "ERROR_RDI_LINE_BUFFER_CONFLICT",
-		.desc = "Two or more RDIs programmed to access the shared line buffer",
-		.err_handler = cam_ife_csid_hw_ver2_rdi_line_buffer_conflict_handler,
+		{
+			.bitmask  = BIT(1),
+			.err_type = CAM_ISP_HW_ERROR_CSID_SENSOR_SWITCH_ERROR,
+			.err_name = "FATAL_SENSOR_SWITCHING_IRQ",
+			.desc = "Fatal Error during dynamically switching between 2 sensors",
+		},
+		{
+			.bitmask  = BIT(18),
+			.err_name = "ERROR_NO_VOTE_DN",
+			.desc = "vote_up is asserted before IDLE is encountered in a frame",
+		},
+		{
+			.bitmask  = BIT(19),
+			.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
+			.err_name = "ERROR_VOTE_UP_LATE",
+			.desc = "vote_up is asserted at the same time as an SOF",
+			.err_handler = cam_ife_csid_hw_ver2_drv_err_handler,
+		},
+		{
+			.bitmask  = BIT(20),
+			.err_type = CAM_ISP_HW_ERROR_CSID_OUTPUT_FIFO_OVERFLOW,
+			.err_name = "ERROR_RDI_LINE_BUFFER_CONFLICT",
+			.desc = "Two or more RDIs programmed to access the shared line buffer",
+			.err_handler = cam_ife_csid_hw_ver2_rdi_line_buffer_conflict_handler,
+		},
 	},
 };
 
+static const uint32_t cam_ife_csid_880_num_top_irq_desc[] = {
+	ARRAY_SIZE(cam_ife_csid_880_top_irq_desc[0]),
+};
+
 static struct cam_irq_register_set cam_ife_csid_880_irq_reg_set[9] = {
 	/* Top */
 	{
@@ -349,19 +357,23 @@ static struct cam_irq_register_set cam_ife_csid_880_irq_reg_set[9] = {
 	},
 };
 
-static struct cam_irq_controller_reg_info cam_ife_csid_880_top_irq_reg_info = {
-	.num_registers = 1,
-	.irq_reg_set = &cam_ife_csid_880_irq_reg_set[CAM_IFE_CSID_IRQ_REG_TOP],
-	.global_irq_cmd_offset = 0x00000014,
-	.global_clear_bitmask  = 0x00000001,
-	.global_set_bitmask    = 0x00000010,
-	.clear_all_bitmask     = 0xFFFFFFFF,
+static struct cam_irq_controller_reg_info cam_ife_csid_880_top_irq_reg_info[] = {
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_880_irq_reg_set[CAM_IFE_CSID_IRQ_REG_TOP],
+		.global_irq_cmd_offset = 0x00000014,
+		.global_clear_bitmask  = 0x00000001,
+		.global_set_bitmask    = 0x00000010,
+		.clear_all_bitmask     = 0xFFFFFFFF,
+	},
 };
 
-static struct cam_irq_controller_reg_info cam_ife_csid_880_rx_irq_reg_info = {
-	.num_registers = 1,
-	.irq_reg_set = &cam_ife_csid_880_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RX],
-	.global_irq_cmd_offset = 0, /* intentionally set to zero */
+static struct cam_irq_controller_reg_info cam_ife_csid_880_rx_irq_reg_info[] = {
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_880_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RX],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
 };
 
 static struct cam_irq_controller_reg_info cam_ife_csid_880_path_irq_reg_info[7] = {
@@ -533,7 +545,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                  = 0x400000,
 		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x10001,
-		.top_irq_mask                     = 0x10,
+		.top_irq_mask                     = {0x10,},
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
 };
@@ -637,7 +649,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.fatal_err_mask                   = 0x20186001,
 		.non_fatal_err_mask               = 0x12000004,
 		.rup_aup_mask                     = 0x40004,
-		.top_irq_mask                     = 0x40,
+		.top_irq_mask                     = {0x40,},
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
 		.sof_retiming_dis_shift           = 5,
@@ -747,7 +759,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                  = 0x400000,
 		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x100010,
-		.top_irq_mask                     = 0x100,
+		.top_irq_mask                     = {0x100,},
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
 		.pix_store_en_shift_val           = 10,
@@ -858,7 +870,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                  = 0x400000,
 		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x200020,
-		.top_irq_mask                     = 0x200,
+		.top_irq_mask                     = {0x200,},
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
 		.pix_store_en_shift_val           = 10,
@@ -968,7 +980,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                  = 0x400000,
 		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x400040,
-		.top_irq_mask                     = 0x400,
+		.top_irq_mask                     = {0x400,},
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
 		.pix_store_en_shift_val           = 10,
@@ -1076,7 +1088,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                  = 0x400000,
 		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x800080,
-		.top_irq_mask                     = 0x800,
+		.top_irq_mask                     = {0x800,},
 		.epoch0_shift_val                 = 16,
 		.epoch1_shift_val                 = 0,
 		.sof_retiming_dis_shift           = 5,
@@ -1177,24 +1189,24 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en               = 1,
 		.fatal_err_mask                  = 0x20186001,
 		.non_fatal_err_mask              = 0x12000004,
-		.sof_irq_mask                     = 0x10,
-		.rup_irq_mask                     = 0x800000,
-		.epoch0_irq_mask                  = 0x200000,
-		.epoch1_irq_mask                  = 0x400000,
-		.eof_irq_mask                     = 0x8,
+		.sof_irq_mask                    = 0x10,
+		.rup_irq_mask                    = 0x800000,
+		.epoch0_irq_mask                 = 0x200000,
+		.epoch1_irq_mask                 = 0x400000,
+		.eof_irq_mask                    = 0x8,
 		.rup_aup_mask                    = 0x1000100,
-		.top_irq_mask                    = 0x1000,
+		.top_irq_mask                    = {0x1000,},
 		.epoch0_shift_val                = 16,
 		.epoch1_shift_val                = 0,
 		.sof_retiming_dis_shift          = 5,
 };
 
-static struct cam_ife_csid_csi2_rx_reg_info
+static struct cam_ife_csid_ver2_csi2_rx_reg_info
 	cam_ife_csid_880_csi2_reg_info = {
-		.irq_status_addr                 = 0x009C,
-		.irq_mask_addr                   = 0x00A0,
-		.irq_clear_addr                  = 0x00A4,
-		.irq_set_addr                    = 0x00A8,
+		.irq_status_addr                 = {0x009C,},
+		.irq_mask_addr                   = {0x00A0,},
+		.irq_clear_addr                  = {0x00A4,},
+		.irq_set_addr                    = {0x00A8,},
 		/*CSI2 rx control */
 		.cfg0_addr                       = 0x0200,
 		.cfg1_addr                       = 0x0204,
@@ -1263,10 +1275,10 @@ static struct cam_ife_csid_csi2_rx_reg_info
 		.short_pkt_strobe_rst_shift      = 1,
 		.cphy_pkt_strobe_rst_shift       = 2,
 		.unmapped_pkt_strobe_rst_shift   = 3,
-		.fatal_err_mask                  = 0x19FA800,
-		.part_fatal_err_mask             = 0x0001000,
-		.non_fatal_err_mask              = 0x0200000,
-		.top_irq_mask                    = 0x4,
+		.fatal_err_mask                  = {0x19FA800,},
+		.part_fatal_err_mask             = {0x0001000,},
+		.non_fatal_err_mask              = {0x0200000,},
+		.top_irq_mask                    = {0x4,},
 };
 
 static struct cam_ife_csid_ver2_common_reg_info
@@ -1280,10 +1292,10 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.rup_aup_cmd_addr                        = 0x0018,
 	.offline_cmd_addr                        = 0x001C,
 	.shdr_master_slave_cfg_addr              = 0x0020,
-	.top_irq_status_addr                     = 0x007C,
-	.top_irq_mask_addr                       = 0x0080,
-	.top_irq_clear_addr                      = 0x0084,
-	.top_irq_set_addr                        = 0x0088,
+	.top_irq_status_addr                     = {0x007C,},
+	.top_irq_mask_addr                       = {0x0080,},
+	.top_irq_clear_addr                      = {0x0084,},
+	.top_irq_set_addr                        = {0x0088,},
 	.buf_done_irq_status_addr                = 0x008C,
 	.buf_done_irq_mask_addr                  = 0x0090,
 	.buf_done_irq_clear_addr                 = 0x0094,
@@ -1346,7 +1358,9 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.ipp_irq_mask_all                        = 0x7FFF,
 	.rdi_irq_mask_all                        = 0x7FFF,
 	.ppp_irq_mask_all                        = 0xFFFF,
-	.top_err_irq_mask                        = 0x180002,
+	.top_err_irq_mask = {
+		0x180002,
+	},
 	.rst_loc_path_only_val                   = 0x0,
 	.rst_loc_complete_csid_val               = 0x1,
 	.rst_mode_frame_boundary_val             = 0x0,
@@ -1355,7 +1369,9 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.rst_cmd_sw_reset_complete_val           = 0x2,
 	.rst_cmd_irq_ctrl_only_val               = 0x4,
 	.timestamp_strobe_val                    = 0x2,
-	.top_reset_irq_mask                      = 0x1,
+	.top_reset_irq_mask = {
+		0x1,
+	},
 	.rst_location_shift_val                  = 4,
 	.rst_mode_shift_val                      = 0,
 	.epoch_factor                            = 50,
@@ -1423,8 +1439,8 @@ static struct cam_ife_csid_ver2_top_reg_info
 };
 
 static struct cam_ife_csid_ver2_reg_info cam_ife_csid_880_reg_info = {
-	.top_irq_reg_info      = &cam_ife_csid_880_top_irq_reg_info,
-	.rx_irq_reg_info       = &cam_ife_csid_880_rx_irq_reg_info,
+	.top_irq_reg_info      = cam_ife_csid_880_top_irq_reg_info,
+	.rx_irq_reg_info       = cam_ife_csid_880_rx_irq_reg_info,
 	.path_irq_reg_info     = {
 		&cam_ife_csid_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_0],
 		&cam_ife_csid_880_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_1],
@@ -1479,9 +1495,11 @@ static struct cam_ife_csid_ver2_reg_info cam_ife_csid_880_reg_info = {
 	},
 	.need_top_cfg = 0x1,
 	.csid_cust_node_map = {0x1, 0x0, 0x2},
-	.rx_irq_desc        = cam_ife_csid_880_rx_irq_desc,
+	.rx_irq_desc        = &cam_ife_csid_880_rx_irq_desc,
 	.path_irq_desc      = cam_ife_csid_880_path_irq_desc,
-	.top_irq_desc       = cam_ife_csid_880_top_irq_desc,
-	.num_top_err_irqs   = ARRAY_SIZE(cam_ife_csid_880_top_irq_desc),
+	.top_irq_desc       = &cam_ife_csid_880_top_irq_desc,
+	.num_top_err_irqs   = cam_ife_csid_880_num_top_irq_desc,
+	.num_top_regs       = 1,
+	.num_rx_regs        = 1,
 };
 #endif /*_CAM_IFE_CSID_880_H_ */

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c

@@ -470,7 +470,7 @@ static int cam_ife_csid_ver2_handle_rx_irq(
 
 	CAM_DBG(CAM_ISP, "CSID:%u Enter", csid_hw->hw_intf->hw_idx);
 	rc = cam_irq_controller_handle_irq(evt_id,
-		csid_hw->rx_irq_controller, CAM_IRQ_EVT_GROUP_0);
+		csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0], CAM_IRQ_EVT_GROUP_0);
 	CAM_DBG(CAM_ISP, "CSID:%u Exit (rc=%d)", csid_hw->hw_intf->hw_idx, rc);
 
 	return (rc == IRQ_HANDLED) ? 0 : -EINVAL;
@@ -783,18 +783,18 @@ static int cam_ife_csid_ver2_stop_csi2_in_err(
 
 	if (csid_hw->rx_cfg.top_irq_handle)
 		cam_irq_controller_disable_irq(
-			csid_hw->top_irq_controller,
+			csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
 			csid_hw->rx_cfg.top_irq_handle);
 
 	if (csid_hw->rx_cfg.irq_handle)
 		cam_irq_controller_disable_irq(
-			csid_hw->rx_irq_controller,
+			csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0],
 			csid_hw->rx_cfg.irq_handle);
 
-	if (csid_hw->rx_cfg.err_irq_handle)
+	if (csid_hw->rx_cfg.err_irq_handle[CAM_IFE_CSID_RX_IRQ_STATUS_REG0])
 		cam_irq_controller_disable_irq(
-			csid_hw->rx_irq_controller,
-			csid_hw->rx_cfg.err_irq_handle);
+			csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0],
+			csid_hw->rx_cfg.err_irq_handle[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]);
 
 	return 0;
 }
@@ -806,7 +806,7 @@ static inline void cam_ife_csid_ver2_maskout_rx_irqs(
 
 	if (csid_hw->rx_cfg.irq_handle) {
 		rc = cam_irq_controller_unsubscribe_irq(
-			csid_hw->rx_irq_controller,
+			csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0],
 			csid_hw->rx_cfg.irq_handle);
 		if (rc)
 			CAM_WARN(CAM_ISP,
@@ -816,21 +816,20 @@ static inline void cam_ife_csid_ver2_maskout_rx_irqs(
 		csid_hw->rx_cfg.irq_handle = 0;
 	}
 
-	if (csid_hw->rx_cfg.err_irq_handle) {
+	if (csid_hw->rx_cfg.err_irq_handle[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]) {
 		rc = cam_irq_controller_unsubscribe_irq(
-			csid_hw->rx_irq_controller,
-			csid_hw->rx_cfg.err_irq_handle);
+			csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0],
+			csid_hw->rx_cfg.err_irq_handle[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]);
 		if (rc)
 			CAM_WARN(CAM_ISP,
 				"Failed to unsubscribe rx err irq for CSID:%u rc:%d",
 				csid_hw->hw_intf->hw_idx, rc);
-
-		csid_hw->rx_cfg.err_irq_handle = 0;
+		csid_hw->rx_cfg.err_irq_handle[CAM_IFE_CSID_RX_IRQ_STATUS_REG0] = 0;
 	}
 
 	if (csid_hw->rx_cfg.top_irq_handle) {
 		rc = cam_irq_controller_unsubscribe_irq(
-			csid_hw->top_irq_controller,
+			csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
 			csid_hw->rx_cfg.top_irq_handle);
 		if (rc)
 			CAM_WARN(CAM_ISP,
@@ -838,8 +837,9 @@ static inline void cam_ife_csid_ver2_maskout_rx_irqs(
 				csid_hw->hw_intf->hw_idx, rc);
 
 		csid_hw->rx_cfg.irq_handle = 0;
-		cam_irq_controller_unregister_dependent(csid_hw->top_irq_controller,
-			csid_hw->rx_irq_controller);
+		cam_irq_controller_unregister_dependent(
+			csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
+			csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]);
 	}
 }
 
@@ -850,7 +850,7 @@ static inline void cam_ife_csid_ver2_disable_rx_evts(
 
 	if (csid_hw->rx_cfg.irq_handle) {
 		rc = cam_irq_controller_unsubscribe_irq_evt(
-			csid_hw->rx_irq_controller,
+			csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0],
 			csid_hw->rx_cfg.irq_handle);
 		if (rc)
 			CAM_WARN(CAM_ISP,
@@ -860,21 +860,21 @@ static inline void cam_ife_csid_ver2_disable_rx_evts(
 		csid_hw->rx_cfg.irq_handle = 0;
 	}
 
-	if (csid_hw->rx_cfg.err_irq_handle) {
+	if (csid_hw->rx_cfg.err_irq_handle[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]) {
 		rc = cam_irq_controller_unsubscribe_irq_evt(
-			csid_hw->rx_irq_controller,
-			csid_hw->rx_cfg.err_irq_handle);
+			csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0],
+			csid_hw->rx_cfg.err_irq_handle[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]);
 		if (rc)
 			CAM_WARN(CAM_ISP,
 				"Failed to unsubscribe rx err irq evt for CSID:%u rc:%d",
 				csid_hw->hw_intf->hw_idx, rc);
 
-		csid_hw->rx_cfg.err_irq_handle = 0;
+		csid_hw->rx_cfg.err_irq_handle[CAM_IFE_CSID_RX_IRQ_STATUS_REG0] = 0;
 	}
 
 	if (csid_hw->rx_cfg.top_irq_handle) {
 		rc = cam_irq_controller_unsubscribe_irq_evt(
-			csid_hw->top_irq_controller,
+			csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
 			csid_hw->rx_cfg.top_irq_handle);
 		if (rc)
 			CAM_WARN(CAM_ISP,
@@ -882,8 +882,9 @@ static inline void cam_ife_csid_ver2_disable_rx_evts(
 				csid_hw->hw_intf->hw_idx, rc);
 
 		csid_hw->rx_cfg.irq_handle = 0;
-		cam_irq_controller_unregister_dependent(csid_hw->top_irq_controller,
-			csid_hw->rx_irq_controller);
+		cam_irq_controller_unregister_dependent(
+			csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
+			csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]);
 	}
 }
 
@@ -915,13 +916,13 @@ static int cam_ife_csid_ver2_rx_err_top_half(
 	uint32_t                                   evt_id,
 	struct cam_irq_th_payload                 *th_payload)
 {
-	int32_t                                          rc = 0;
-	uint32_t                                         status = 0;
-	struct cam_ife_csid_ver2_hw                     *csid_hw = NULL;
-	struct cam_ife_csid_ver2_reg_info               *csid_reg;
-	struct cam_ife_csid_ver2_evt_payload            *evt_payload;
-	const struct cam_ife_csid_csi2_rx_reg_info      *csi2_reg;
-	int                                              discard_frame_count;
+	int32_t                                               rc = 0;
+	uint32_t                                              status = 0;
+	struct cam_ife_csid_ver2_hw                          *csid_hw = NULL;
+	struct cam_ife_csid_ver2_reg_info                    *csid_reg;
+	struct cam_ife_csid_ver2_evt_payload                 *evt_payload;
+	const struct cam_ife_csid_ver2_csi2_rx_reg_info      *csi2_reg;
+	int                                                   discard_frame_count;
 
 	csid_hw = th_payload->handler_priv;
 	if (!csid_hw) {
@@ -962,13 +963,13 @@ static int cam_ife_csid_ver2_rx_err_top_half(
 		status &= (~IFE_CSID_VER2_RX_CPHY_EOT_RECEPTION);
 	}
 
-	if (status & csi2_reg->fatal_err_mask) {
+	if (status & csi2_reg->fatal_err_mask[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]) {
 		csid_hw->flags.fatal_err_detected = true;
 		cam_ife_csid_ver2_stop_csi2_in_err(csid_hw);
 		goto end;
 	}
 
-	if (status & csi2_reg->part_fatal_err_mask) {
+	if (status & csi2_reg->part_fatal_err_mask[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]) {
 		if (status & IFE_CSID_VER2_RX_CPHY_SOT_RECEPTION)
 			csid_hw->counters.error_irq_count++;
 
@@ -997,12 +998,14 @@ end:
 }
 
 static int cam_ife_csid_ver2_handle_rx_debug_event(
-	struct cam_ife_csid_ver2_hw *csid_hw,
-	uint32_t bit_pos, uint32_t *rst_strobe_val)
+	struct cam_ife_csid_ver2_hw   *csid_hw,
+	enum cam_ife_csid_rx_irq_regs  rx_index,
+	uint32_t                       bit_pos,
+	uint32_t                      *rst_strobe_val)
 {
 	struct cam_hw_soc_info              *soc_info;
 	struct cam_ife_csid_ver2_reg_info *csid_reg;
-	const struct cam_ife_csid_csi2_rx_reg_info *csi2_reg;
+	const struct cam_ife_csid_ver2_csi2_rx_reg_info *csi2_reg;
 	uint32_t mask, val;
 
 	csid_reg = (struct cam_ife_csid_ver2_reg_info *)
@@ -1099,7 +1102,7 @@ static int cam_ife_csid_ver2_handle_rx_debug_event(
 		CAM_DBG(CAM_ISP,
 			"CSID[%u] RX_IRQ: %s",
 			csid_hw->hw_intf->hw_idx,
-			csid_reg->rx_irq_desc[bit_pos].desc);
+			(*csid_reg->rx_irq_desc)[rx_index][bit_pos].desc);
 		break;
 	}
 
@@ -1111,7 +1114,7 @@ static int cam_ife_csid_ver2_rx_top_half(
 	struct cam_irq_th_payload                 *th_payload)
 {
 	struct cam_ife_csid_ver2_hw                *csid_hw = NULL;
-	const struct cam_ife_csid_csi2_rx_reg_info *csi2_reg;
+	const struct cam_ife_csid_ver2_csi2_rx_reg_info *csi2_reg;
 	struct cam_ife_csid_ver2_reg_info          *csid_reg;
 	uint32_t                                    irq_status;
 	uint32_t                                    rst_strobe_val = 0;
@@ -1134,7 +1137,7 @@ static int cam_ife_csid_ver2_rx_top_half(
 		bit_set = irq_status & 1;
 		if ((bit_set) && (BIT(bit_pos) & csid_hw->debug_info.rx_mask))
 			cam_ife_csid_ver2_handle_rx_debug_event(csid_hw,
-				bit_pos, &rst_strobe_val);
+				CAM_IFE_CSID_RX_IRQ_STATUS_REG0, bit_pos, &rst_strobe_val);
 		bit_pos++;
 		irq_status >>= 1;
 	}
@@ -1224,7 +1227,7 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
 	void                                      *handler_priv,
 	void                                      *evt_payload_priv)
 {
-	const struct cam_ife_csid_csi2_rx_reg_info *csi2_reg;
+	const struct cam_ife_csid_ver2_csi2_rx_reg_info *csi2_reg;
 	struct cam_ife_csid_ver2_evt_payload       *payload;
 	struct cam_ife_csid_ver2_hw                *csid_hw = NULL;
 	struct cam_ife_csid_ver2_reg_info          *csid_reg;
@@ -1255,7 +1258,8 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
 			csid_hw->core_info->csid_reg;
 	csi2_reg = csid_reg->csi2_reg;
 
-	irq_status = payload->irq_reg_val & csi2_reg->fatal_err_mask;
+	irq_status = payload->irq_reg_val &
+			csi2_reg->fatal_err_mask[CAM_IFE_CSID_RX_IRQ_STATUS_REG0];
 
 	if (!csid_hw->flags.device_enabled) {
 		CAM_DBG(CAM_ISP, "CSID[%u] bottom-half after stop [0x%x]",
@@ -1361,7 +1365,8 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
 		csid_hw->flags.fatal_err_detected = true;
 	}
 
-	irq_status = payload->irq_reg_val & csi2_reg->part_fatal_err_mask;
+	irq_status = payload->irq_reg_val &
+			csi2_reg->part_fatal_err_mask[CAM_IFE_CSID_RX_IRQ_STATUS_REG0];
 
 	if (irq_status) {
 		len = 0;
@@ -1375,7 +1380,8 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
 		rx_irq_status |= irq_status;
 	}
 
-	irq_status = payload->irq_reg_val & csi2_reg->non_fatal_err_mask;
+	irq_status = payload->irq_reg_val &
+			csi2_reg->non_fatal_err_mask[CAM_IFE_CSID_RX_IRQ_STATUS_REG0];
 
 	if (irq_status) {
 		len = 0;
@@ -1813,30 +1819,49 @@ static int cam_ife_csid_ver2_top_err_irq_bottom_half(
 	csid_reg = (struct cam_ife_csid_ver2_reg_info *)
 			csid_hw->core_info->csid_reg;
 
-	irq_status = payload->irq_reg_val & csid_reg->cmn_reg->top_err_irq_mask;
+	irq_status = payload->irq_reg_val &
+		csid_reg->cmn_reg->top_err_irq_mask[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0];
 
 	if (!irq_status) {
 		CAM_ERR(CAM_ISP, "CSID:%u Unexpected Scenario", csid_hw->hw_intf->hw_idx);
 		return 0;
 	}
 
-	for (i = 0; i < csid_reg->num_top_err_irqs; i++) {
-		if (csid_reg->top_irq_desc[i].bitmask &
-			irq_status) {
-			CAM_ERR(CAM_ISP, "CSID:%u %s %s",
-				csid_hw->hw_intf->hw_idx, csid_reg->top_irq_desc[i].err_name,
-				csid_reg->top_irq_desc[i].desc);
+	if (!csid_reg->num_top_err_irqs) {
+		CAM_WARN_RATE_LIMIT_CUSTOM(CAM_ISP, 100, 1,
+			"CSID:%u Unexpected Scenario no top error irqs", csid_hw->hw_intf->hw_idx);
+		cam_ife_csid_ver2_put_evt_payload(csid_hw, &payload,
+			&csid_hw->path_free_payload_list, &csid_hw->path_payload_lock);
+		return 0;
+	}
 
-			if (csid_reg->top_irq_desc[i].err_handler)
-				csid_reg->top_irq_desc[i].err_handler(csid_hw);
+	for (i = 0; i < csid_reg->num_top_err_irqs[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]; i++) {
+		if (!csid_reg->top_irq_desc) {
+			CAM_ERR(CAM_ISP, "CSID:%u Unexpected Scenario top irq descriptor empty",
+				csid_hw->hw_intf->hw_idx);
+			break;
+		}
 
-			event_type |= csid_reg->top_irq_desc[i].err_type;
+		if ((*csid_reg->top_irq_desc)[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0][i].bitmask &
+				irq_status) {
+			CAM_ERR(CAM_ISP, "%s %s",
+					(*csid_reg->top_irq_desc)
+					[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0][i].err_name,
+					(*csid_reg->top_irq_desc)
+					[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0][i].desc);
+			if ((*csid_reg->top_irq_desc)[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0][i]
+				.err_handler)
+				(*csid_reg->top_irq_desc)[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0][i]
+					.err_handler(csid_hw);
+
+			event_type |= (*csid_reg->top_irq_desc)
+				[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0][i].err_type;
 		}
 	}
 
 	if (event_type)
 		cam_ife_csid_ver2_handle_event_err(csid_hw,
-			irq_status, event_type, false, NULL);
+				irq_status, event_type, false, NULL);
 
 	cam_ife_csid_ver2_put_evt_payload(csid_hw, &payload,
 		&csid_hw->path_free_payload_list,
@@ -2349,7 +2374,7 @@ static int cam_ife_csid_ver2_internal_reset(
 	uint32_t val = 0;
 	struct cam_ife_csid_ver2_reg_info *csid_reg;
 	struct cam_hw_soc_info                *soc_info;
-	const struct cam_ife_csid_csi2_rx_reg_info *csi2_reg;
+	const struct cam_ife_csid_ver2_csi2_rx_reg_info *csi2_reg;
 	void __iomem *mem_base;
 	int rc = 0;
 
@@ -2513,7 +2538,7 @@ static inline void cam_ife_csid_ver2_maskout_path_irqs(
 
 	if (path_cfg->top_irq_handle) {
 		rc = cam_irq_controller_unsubscribe_irq(
-			csid_hw->top_irq_controller,
+			csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
 			path_cfg->top_irq_handle);
 		if (rc)
 			CAM_WARN(CAM_ISP,
@@ -2523,7 +2548,7 @@ static inline void cam_ife_csid_ver2_maskout_path_irqs(
 		path_cfg->top_irq_handle = 0;
 
 		(void) cam_irq_controller_unregister_dependent(
-			csid_hw->top_irq_controller,
+			csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
 			csid_hw->path_irq_controller[res_id]);
 	}
 }
@@ -2573,7 +2598,7 @@ static inline void cam_ife_csid_ver2_disable_path_irqs_evts(
 
 	if (path_cfg->top_irq_handle) {
 		rc = cam_irq_controller_unsubscribe_irq_evt(
-			csid_hw->top_irq_controller,
+			csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
 			path_cfg->top_irq_handle);
 		if (rc)
 			CAM_WARN(CAM_ISP,
@@ -2583,7 +2608,7 @@ static inline void cam_ife_csid_ver2_disable_path_irqs_evts(
 		path_cfg->top_irq_handle = 0;
 
 		(void) cam_irq_controller_unregister_dependent(
-			csid_hw->top_irq_controller,
+			csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
 			csid_hw->path_irq_controller[res_id]);
 	}
 }
@@ -3238,7 +3263,7 @@ int cam_ife_csid_ver2_release(void *hw_priv,
 
 	if (!csid_hw->counters.csi2_reserve_cnt) {
 		memset(&csid_hw->rx_cfg, 0,
-			sizeof(struct cam_ife_csid_rx_cfg));
+			sizeof(struct cam_ife_csid_ver2_rx_cfg));
 		memset(&csid_hw->top_cfg, 0,
 			sizeof(struct cam_ife_csid_ver2_top_cfg));
 		memset(&csid_hw->debug_info, 0,
@@ -3714,17 +3739,30 @@ static int cam_ife_csid_ver2_path_irq_subscribe(
 	struct cam_isp_resource_node *res,
 	uint32_t irq_mask, uint32_t err_irq_mask)
 {
-	uint32_t top_irq_mask[CAM_IFE_CSID_IRQ_REGISTERS_MAX] = {0};
+	uint32_t top_irq_mask = 0;
 	struct cam_ife_csid_ver2_path_cfg *path_cfg = res->res_priv;
 	struct cam_ife_csid_ver2_reg_info *csid_reg = csid_hw->core_info->csid_reg;
-	int rc;
+	int i, rc;
+	int top_index = -1;
+
+	for (i = CAM_IFE_CSID_TOP_IRQ_STATUS_REG0; i < csid_reg->num_top_regs; i++) {
+		if (csid_reg->path_reg[res->res_id]->top_irq_mask[i]) {
+			top_index = i;
+			break;
+		}
+	}
 
-	top_irq_mask[CAM_IFE_CSID_IRQ_TOP_REG_STATUS0] =
-		csid_reg->path_reg[res->res_id]->top_irq_mask;
+	if (top_index < 0) {
+		CAM_ERR(CAM_ISP, "csid[%d] subscribe top irq fail %s",
+			csid_hw->hw_intf->hw_idx, res->res_name);
+		return -EINVAL;
+	}
+
+	top_irq_mask = csid_reg->path_reg[res->res_id]->top_irq_mask[top_index];
 	path_cfg->top_irq_handle = cam_irq_controller_subscribe_irq(
-		csid_hw->top_irq_controller,
+		csid_hw->top_irq_controller[top_index],
 		CAM_IRQ_PRIORITY_0,
-		top_irq_mask,
+		&top_irq_mask,
 		res,
 		cam_ife_csid_ver2_handle_path_irq,
 		NULL, NULL, NULL, CAM_IRQ_EVT_GROUP_0);
@@ -3735,8 +3773,8 @@ static int cam_ife_csid_ver2_path_irq_subscribe(
 		return -EINVAL;
 	}
 
-	rc = cam_irq_controller_register_dependent(csid_hw->top_irq_controller,
-		csid_hw->path_irq_controller[res->res_id], top_irq_mask);
+	rc = cam_irq_controller_register_dependent(csid_hw->top_irq_controller[top_index],
+		csid_hw->path_irq_controller[res->res_id], &top_irq_mask);
 
 	if (rc)
 		goto unsub_top;
@@ -3784,10 +3822,10 @@ unsub_path:
 			path_cfg->irq_handle);
 	path_cfg->irq_handle = 0;
 unreg_path:
-	cam_irq_controller_unregister_dependent(csid_hw->top_irq_controller,
+	cam_irq_controller_unregister_dependent(csid_hw->top_irq_controller[top_index],
 		csid_hw->path_irq_controller[res->res_id]);
 unsub_top:
-	cam_irq_controller_unsubscribe_irq(csid_hw->top_irq_controller,
+	cam_irq_controller_unsubscribe_irq(csid_hw->top_irq_controller[top_index],
 			path_cfg->top_irq_handle);
 	path_cfg->top_irq_handle = 0;
 	return rc;
@@ -4176,7 +4214,7 @@ static int cam_ife_csid_ver2_rx_capture_config(
 {
 	const struct cam_ife_csid_ver2_reg_info   *csid_reg;
 	struct cam_hw_soc_info                    *soc_info;
-	struct cam_ife_csid_rx_cfg                *rx_cfg;
+	struct cam_ife_csid_ver2_rx_cfg                *rx_cfg;
 	uint32_t vc, dt, i;
 	uint32_t val = 0;
 
@@ -4230,14 +4268,29 @@ static int cam_ife_csid_ver2_csi2_irq_subscribe(struct cam_ife_csid_ver2_hw *csi
 	uint32_t irq_mask, uint32_t err_irq_mask)
 {
 	struct cam_ife_csid_ver2_reg_info *csid_reg = csid_hw->core_info->csid_reg;
-	uint32_t top_irq_mask[CAM_IFE_CSID_IRQ_REGISTERS_MAX] = {0};
-	int rc;
+	uint32_t top_irq_mask = 0;
+	int top_index = -1;
+	int i, rc;
 
-	top_irq_mask[CAM_IFE_CSID_IRQ_TOP_REG_STATUS0] = csid_reg->csi2_reg->top_irq_mask;
+	for (i = CAM_IFE_CSID_TOP_IRQ_STATUS_REG0; i < csid_reg->num_top_regs; i++) {
+		if (csid_reg->csi2_reg->top_irq_mask[i]) {
+			top_index = i;
+			break;
+		}
+	}
+
+	if (top_index < 0) {
+		CAM_ERR(CAM_ISP, "CSID[%d] RX Subscribe Top Irq fail due to invalid mask",
+			csid_hw->hw_intf->hw_idx);
+		rc = -EINVAL;
+		return rc;
+	}
+
+	top_irq_mask = csid_reg->csi2_reg->top_irq_mask[top_index];
 	csid_hw->rx_cfg.top_irq_handle = cam_irq_controller_subscribe_irq(
-		csid_hw->top_irq_controller,
+		csid_hw->top_irq_controller[top_index],
 		CAM_IRQ_PRIORITY_0,
-		top_irq_mask,
+		&top_irq_mask,
 		csid_hw,
 		cam_ife_csid_ver2_handle_rx_irq,
 		NULL, NULL, NULL, CAM_IRQ_EVT_GROUP_0);
@@ -4249,15 +4302,17 @@ static int cam_ife_csid_ver2_csi2_irq_subscribe(struct cam_ife_csid_ver2_hw *csi
 		goto err;
 	}
 
-	rc = cam_irq_controller_register_dependent(csid_hw->top_irq_controller,
-		csid_hw->rx_irq_controller, top_irq_mask);
+	rc = cam_irq_controller_register_dependent(csid_hw->top_irq_controller[top_index],
+		csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0],
+		&top_irq_mask);
 
 	if (rc)
 		goto unsub_top;
 
 	if (irq_mask) {
 		csid_hw->rx_cfg.irq_handle = cam_irq_controller_subscribe_irq(
-						csid_hw->rx_irq_controller,
+						csid_hw->rx_irq_controller
+						[CAM_IFE_CSID_RX_IRQ_STATUS_REG0],
 						CAM_IRQ_PRIORITY_4,
 						&irq_mask,
 						csid_hw,
@@ -4275,8 +4330,10 @@ static int cam_ife_csid_ver2_csi2_irq_subscribe(struct cam_ife_csid_ver2_hw *csi
 		}
 	}
 
-	csid_hw->rx_cfg.err_irq_handle = cam_irq_controller_subscribe_irq(
-						csid_hw->rx_irq_controller,
+	csid_hw->rx_cfg.err_irq_handle[CAM_IFE_CSID_RX_IRQ_STATUS_REG0] =
+					cam_irq_controller_subscribe_irq(
+						csid_hw->rx_irq_controller
+						[CAM_IFE_CSID_RX_IRQ_STATUS_REG0],
 						CAM_IRQ_PRIORITY_0,
 						&err_irq_mask,
 						csid_hw,
@@ -4286,8 +4343,8 @@ static int cam_ife_csid_ver2_csi2_irq_subscribe(struct cam_ife_csid_ver2_hw *csi
 						&tasklet_bh_api,
 						CAM_IRQ_EVT_GROUP_0);
 
-	if (csid_hw->rx_cfg.err_irq_handle < 1) {
-		CAM_ERR(CAM_ISP, "CSID[%u] RX err irq register fail",
+	if (csid_hw->rx_cfg.err_irq_handle[CAM_IFE_CSID_RX_IRQ_STATUS_REG0] < 1) {
+		CAM_ERR(CAM_ISP, "CSID[%d] RX err irq register fail",
 			csid_hw->hw_intf->hw_idx);
 		rc = -EINVAL;
 		goto unsub_rx;
@@ -4297,14 +4354,15 @@ static int cam_ife_csid_ver2_csi2_irq_subscribe(struct cam_ife_csid_ver2_hw *csi
 
 unsub_rx:
 	if (csid_hw->rx_cfg.irq_handle)
-		cam_irq_controller_unsubscribe_irq(csid_hw->rx_irq_controller,
-				csid_hw->rx_cfg.irq_handle);
+		cam_irq_controller_unsubscribe_irq(
+		csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0],
+		csid_hw->rx_cfg.irq_handle);
 	csid_hw->rx_cfg.irq_handle = 0;
 unreg_rx:
-	cam_irq_controller_unregister_dependent(csid_hw->top_irq_controller,
-		csid_hw->rx_irq_controller);
+	cam_irq_controller_unregister_dependent(csid_hw->top_irq_controller[top_index],
+		csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]);
 unsub_top:
-	cam_irq_controller_unsubscribe_irq(csid_hw->top_irq_controller,
+	cam_irq_controller_unsubscribe_irq(csid_hw->top_irq_controller[top_index],
 			csid_hw->rx_cfg.top_irq_handle);
 	csid_hw->rx_cfg.top_irq_handle = 0;
 err:
@@ -4313,14 +4371,14 @@ err:
 
 static int cam_ife_csid_ver2_enable_csi2(struct cam_ife_csid_ver2_hw *csid_hw)
 {
-	int rc = 0;
-	struct cam_hw_soc_info              *soc_info;
-	const struct cam_ife_csid_ver2_reg_info *csid_reg;
-	const struct cam_ife_csid_csi2_rx_reg_info  *csi2_reg;
-	uint32_t val = 0;
-	void __iomem *mem_base;
-	struct cam_ife_csid_rx_cfg          *rx_cfg;
-	int vc_full_width;
+	int                                             rc = 0;
+	struct cam_hw_soc_info                          *soc_info;
+	const struct cam_ife_csid_ver2_reg_info         *csid_reg;
+	const struct cam_ife_csid_ver2_csi2_rx_reg_info *csi2_reg;
+	uint32_t                                        val = 0;
+	void __iomem                                    *mem_base;
+	struct cam_ife_csid_ver2_rx_cfg                 *rx_cfg;
+	int                                             vc_full_width;
 
 	if (csid_hw->flags.rx_enabled)
 		return 0;
@@ -4330,9 +4388,9 @@ static int cam_ife_csid_ver2_enable_csi2(struct cam_ife_csid_ver2_hw *csid_hw)
 
 	csid_reg = (struct cam_ife_csid_ver2_reg_info *)
 			csid_hw->core_info->csid_reg;
-	csi2_reg  = csid_reg->csi2_reg;
+	csi2_reg = csid_reg->csi2_reg;
 	soc_info = &csid_hw->hw_info->soc_info;
-	rx_cfg  = &csid_hw->rx_cfg;
+	rx_cfg = &csid_hw->rx_cfg;
 	mem_base = soc_info->reg_map[CAM_IFE_CSID_CLC_MEM_BASE_ID].mem_base;
 
 	/*Configure Rx cfg0 */
@@ -4376,8 +4434,9 @@ static int cam_ife_csid_ver2_enable_csi2(struct cam_ife_csid_ver2_hw *csid_hw)
 	CAM_DBG(CAM_ISP, "CSID[%u] rx_cfg1: 0x%x",
 		csid_hw->hw_intf->hw_idx, val);
 
-	val = csi2_reg->fatal_err_mask | csi2_reg->part_fatal_err_mask |
-		csi2_reg->non_fatal_err_mask;
+	val = csi2_reg->fatal_err_mask[CAM_IFE_CSID_RX_IRQ_STATUS_REG0] |
+		csi2_reg->part_fatal_err_mask[CAM_IFE_CSID_RX_IRQ_STATUS_REG0] |
+		csi2_reg->non_fatal_err_mask[CAM_IFE_CSID_RX_IRQ_STATUS_REG0];
 
 	if (csid_hw->rx_cfg.epd_supported &&
 		(csid_hw->rx_cfg.lane_type == CAM_ISP_LANE_TYPE_DPHY))
@@ -4507,8 +4566,8 @@ static int cam_ife_csid_ver2_enable_core(struct cam_ife_csid_ver2_hw *csid_hw)
 	struct cam_hw_soc_info              *soc_info;
 	const struct cam_ife_csid_ver2_reg_info *csid_reg;
 	uint32_t clk_lvl;
-	uint32_t irq_mask = 0;
 	struct cam_csid_soc_private *soc_private;
+	uint32_t irq_mask = 0;
 
 	csid_reg = (struct cam_ife_csid_ver2_reg_info *)csid_hw->core_info->csid_reg;
 	soc_info = &csid_hw->hw_info->soc_info;
@@ -4574,10 +4633,10 @@ static int cam_ife_csid_ver2_enable_core(struct cam_ife_csid_ver2_hw *csid_hw)
 		}
 	}
 
-	irq_mask = csid_reg->cmn_reg->top_reset_irq_mask;
+	irq_mask = csid_reg->cmn_reg->top_reset_irq_mask[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0];
 
 	csid_hw->reset_irq_handle = cam_irq_controller_subscribe_irq(
-		csid_hw->top_irq_controller,
+		csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
 		CAM_IRQ_PRIORITY_0,
 		&irq_mask,
 		csid_hw,
@@ -4619,7 +4678,7 @@ static int cam_ife_csid_ver2_enable_hw(
 	void __iomem *mem_base;
 	const struct cam_ife_csid_ver2_path_reg_info *path_reg = NULL;
 	uint32_t top_err_irq_mask = 0;
-	uint32_t buf_done_irq_mask[CAM_IFE_CSID_IRQ_REGISTERS_MAX] = {0};
+	uint32_t buf_done_irq_mask = 0;
 	uint32_t top_info_irq_mask = 0;
 
 	if (csid_hw->flags.device_enabled) {
@@ -4634,10 +4693,11 @@ static int cam_ife_csid_ver2_enable_hw(
 	mem_base = soc_info->reg_map[CAM_IFE_CSID_CLC_MEM_BASE_ID].mem_base;
 
 	/* Clear IRQs */
-	cam_io_w_mb(1, mem_base + csid_reg->cmn_reg->top_irq_clear_addr);
+	cam_io_w_mb(1, mem_base +
+		csid_reg->cmn_reg->top_irq_clear_addr[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]);
 
 	cam_io_w_mb(csid_reg->csi2_reg->irq_mask_all,
-		mem_base + csid_reg->csi2_reg->irq_clear_addr);
+		mem_base + csid_reg->csi2_reg->irq_clear_addr[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]);
 
 	path_reg = csid_reg->path_reg[CAM_IFE_PIX_PATH_RES_IPP];
 	if (csid_reg->cmn_reg->num_pix)
@@ -4659,12 +4719,12 @@ static int cam_ife_csid_ver2_enable_hw(
 	/* Read hw version */
 	val = cam_io_r_mb(mem_base + csid_reg->cmn_reg->hw_version_addr);
 
-	buf_done_irq_mask[CAM_IFE_CSID_IRQ_TOP_REG_STATUS0] =
+	buf_done_irq_mask =
 		csid_reg->cmn_reg->top_buf_done_irq_mask;
 	csid_hw->buf_done_irq_handle = cam_irq_controller_subscribe_irq(
-		csid_hw->top_irq_controller,
+		csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
 		CAM_IRQ_PRIORITY_4,
-		buf_done_irq_mask,
+		&buf_done_irq_mask,
 		csid_hw,
 		cam_ife_csid_ver2_handle_buf_done_irq,
 		NULL,
@@ -4679,9 +4739,10 @@ static int cam_ife_csid_ver2_enable_hw(
 		return -EINVAL;
 	}
 
-	top_err_irq_mask = csid_reg->cmn_reg->top_err_irq_mask;
-	csid_hw->top_err_irq_handle = cam_irq_controller_subscribe_irq(
-		csid_hw->top_irq_controller,
+	top_err_irq_mask = csid_reg->cmn_reg->top_err_irq_mask[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0];
+	csid_hw->top_err_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0] =
+		cam_irq_controller_subscribe_irq(
+		csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
 		CAM_IRQ_PRIORITY_0,
 		&top_err_irq_mask,
 		csid_hw,
@@ -4691,18 +4752,20 @@ static int cam_ife_csid_ver2_enable_hw(
 		&tasklet_bh_api,
 		CAM_IRQ_EVT_GROUP_0);
 
-	if (csid_hw->top_err_irq_handle < 1) {
-		CAM_ERR(CAM_ISP, "CSID[%u] top error irq subscribe fail",
+	if (csid_hw->top_err_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0] < 1) {
+		CAM_ERR(CAM_ISP, "csid[%u] top error irq subscribe fail",
 			csid_hw->hw_intf->hw_idx);
 		rc = -EINVAL;
 		goto unsubscribe_buf_done;
 	}
 
-	rc = cam_irq_controller_register_dependent(csid_hw->top_irq_controller,
-		csid_hw->buf_done_irq_controller, buf_done_irq_mask);
+	rc = cam_irq_controller_register_dependent(csid_hw->top_irq_controller
+		[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
+		csid_hw->buf_done_irq_controller, &buf_done_irq_mask);
 
 	if (rc) {
-		cam_irq_controller_unsubscribe_irq(csid_hw->top_irq_controller,
+		cam_irq_controller_unsubscribe_irq(
+			csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
 			csid_hw->buf_done_irq_handle);
 		rc = -EINVAL;
 		goto unsubscribe_top_err;
@@ -4710,8 +4773,10 @@ static int cam_ife_csid_ver2_enable_hw(
 
 	if (csid_hw->debug_info.top_mask) {
 		top_info_irq_mask = csid_hw->debug_info.top_mask;
-		csid_hw->top_info_irq_handle = cam_irq_controller_subscribe_irq(
-						csid_hw->top_irq_controller,
+		csid_hw->top_info_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0] =
+						cam_irq_controller_subscribe_irq(
+						csid_hw->top_irq_controller
+						[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
 						CAM_IRQ_PRIORITY_1,
 						&top_info_irq_mask,
 						csid_hw,
@@ -4721,7 +4786,7 @@ static int cam_ife_csid_ver2_enable_hw(
 						&tasklet_bh_api,
 						CAM_IRQ_EVT_GROUP_0);
 
-		if (csid_hw->top_info_irq_handle < 1) {
+		if (csid_hw->top_info_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0] < 1) {
 			CAM_ERR(CAM_ISP, "CSID[%u] Subscribe Top Info Irq fail",
 				csid_hw->hw_intf->hw_idx);
 			rc = -EINVAL;
@@ -4737,11 +4802,14 @@ static int cam_ife_csid_ver2_enable_hw(
 
 
 unsubscribe_top_err:
-	cam_irq_controller_unsubscribe_irq(csid_hw->top_irq_controller,
-		csid_hw->top_err_irq_handle);
-	csid_hw->top_err_irq_handle = 0;
+	cam_irq_controller_unsubscribe_irq(
+		csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
+		csid_hw->top_err_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]);
+	csid_hw->top_err_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0] = 0;
+
 unsubscribe_buf_done:
-	cam_irq_controller_unsubscribe_irq(csid_hw->top_irq_controller,
+	cam_irq_controller_unsubscribe_irq(
+		csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
 		csid_hw->buf_done_irq_handle);
 	csid_hw->buf_done_irq_handle = 0;
 	return rc;
@@ -4815,11 +4883,11 @@ static int cam_ife_csid_ver2_disable_core(
 
 	/* Disable the top IRQ interrupt */
 	cam_io_w_mb(0, soc_info->reg_map[0].mem_base +
-		csid_reg->cmn_reg->top_irq_mask_addr);
+		csid_reg->cmn_reg->top_irq_mask_addr[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]);
 
 	if (csid_hw->reset_irq_handle) {
 		rc = cam_irq_controller_unsubscribe_irq(
-			csid_hw->top_irq_controller,
+			csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
 			csid_hw->reset_irq_handle);
 		if (rc)
 			CAM_WARN(CAM_ISP,
@@ -5234,7 +5302,7 @@ static void cam_ife_csid_ver2_maskout_all_irqs(
 	int i;
 	struct cam_hw_soc_info *soc_info;
 	const struct cam_ife_csid_ver2_reg_info *csid_reg;
-	const struct cam_ife_csid_csi2_rx_reg_info *csi2_reg;
+	const struct cam_ife_csid_ver2_csi2_rx_reg_info *csi2_reg;
 	const struct cam_ife_csid_ver2_path_reg_info *path_reg = NULL;
 	void __iomem *mem_base;
 	struct cam_isp_resource_node           *res;
@@ -5247,14 +5315,16 @@ static void cam_ife_csid_ver2_maskout_all_irqs(
 
 	/* Disable rx */
 	if (!csid_hw->flags.offline_mode)
-		cam_io_w_mb(0x0, mem_base + csi2_reg->irq_mask_addr);
+		cam_io_w_mb(0x0,
+			mem_base + csi2_reg->irq_mask_addr[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]);
 
 	for (i = 0; i < csid_stop->num_res; i++) {
 		res = csid_stop->node_res[i];
 		path_reg = csid_reg->path_reg[res->res_id];
 
 		/* Disable path */
-		cam_io_w_mb(0x0, mem_base + path_reg->irq_mask_addr);
+		cam_io_w_mb(0x0,
+			mem_base + path_reg->irq_mask_addr);
 	}
 
 	/* Disable buf done */
@@ -5262,8 +5332,8 @@ static void cam_ife_csid_ver2_maskout_all_irqs(
 		csid_reg->cmn_reg->buf_done_irq_mask_addr);
 
 	/* Disable top except rst_done */
-	cam_io_w_mb(csid_reg->cmn_reg->top_reset_irq_mask,
-		mem_base + csid_reg->cmn_reg->top_irq_mask_addr);
+	cam_io_w_mb(csid_reg->cmn_reg->top_reset_irq_mask[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
+		mem_base + csid_reg->cmn_reg->top_irq_mask_addr[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]);
 }
 
 int cam_ife_csid_ver2_stop(void *hw_priv,
@@ -5337,25 +5407,28 @@ int cam_ife_csid_ver2_stop(void *hw_priv,
 	}
 	if (csid_hw->buf_done_irq_handle) {
 		rc = cam_irq_controller_unsubscribe_irq(
-			csid_hw->top_irq_controller,
+			csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
 			csid_hw->buf_done_irq_handle);
 		csid_hw->buf_done_irq_handle = 0;
 
-		cam_irq_controller_unregister_dependent(csid_hw->top_irq_controller,
+		cam_irq_controller_unregister_dependent(
+			csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
 			csid_hw->buf_done_irq_controller);
 	}
 
-	if (csid_hw->top_err_irq_handle) {
+	if (csid_hw->top_err_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]) {
 		rc = cam_irq_controller_unsubscribe_irq(
-			csid_hw->top_irq_controller,
-			csid_hw->top_err_irq_handle);
-		csid_hw->top_err_irq_handle = 0;
+			csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
+			csid_hw->top_err_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]);
+		csid_hw->top_err_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0] = 0;
 	}
 
+
 	if (csid_hw->debug_info.top_mask) {
-		cam_irq_controller_unsubscribe_irq(csid_hw->top_irq_controller,
-			csid_hw->top_info_irq_handle);
-		csid_hw->top_info_irq_handle = 0;
+		cam_irq_controller_unsubscribe_irq(
+			csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
+			csid_hw->top_info_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]);
+		csid_hw->top_info_irq_handle[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0] = 0;
 	}
 
 	cam_ife_csid_ver2_disable_csi2(false, csid_hw);
@@ -5977,7 +6050,7 @@ static int cam_ife_csid_ver2_mini_dump(
 		memcpy(&md_res->path_cfg, path_cfg, sizeof(*path_cfg));
 	}
 
-	memcpy(&md->rx_cfg, &csid_hw->rx_cfg, sizeof(struct cam_ife_csid_rx_cfg));
+	memcpy(&md->rx_cfg, &csid_hw->rx_cfg, sizeof(struct cam_ife_csid_ver2_rx_cfg));
 	memcpy(&md->flags, &csid_hw->flags, sizeof(struct cam_ife_csid_hw_flags));
 	memcpy(md->cid_data, csid_hw->cid_data,
 		sizeof(struct cam_ife_csid_cid_data) * CAM_IFE_CSID_CID_MAX);
@@ -6475,7 +6548,8 @@ static irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
 		return IRQ_NONE;
 
 	return cam_irq_controller_handle_irq(irq_num,
-		csid_hw->top_irq_controller, CAM_IRQ_EVT_GROUP_0);
+		csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
+		CAM_IRQ_EVT_GROUP_0);
 }
 
 static void cam_ife_csid_ver2_free_res(struct cam_ife_csid_ver2_hw *csid_hw)
@@ -6625,8 +6699,8 @@ static void cam_ife_csid_hw_deinit_irq(
 	unsigned long flags;
 	int i;
 
-	cam_irq_controller_deinit(&csid_hw->top_irq_controller);
-	cam_irq_controller_deinit(&csid_hw->rx_irq_controller);
+	cam_irq_controller_deinit(&csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]);
+	cam_irq_controller_deinit(&csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]);
 	cam_irq_controller_deinit(&csid_hw->buf_done_irq_controller);
 
 	for (i = 0; i < CAM_IFE_PIX_PATH_RES_MAX; i++) {
@@ -6664,8 +6738,9 @@ static int cam_ife_csid_hw_init_irq(
 	mem_base = soc_info->reg_map[CAM_IFE_CSID_CLC_MEM_BASE_ID].mem_base;
 
 	snprintf(name, CAM_CSID_IRQ_CTRL_NAME_LEN, "csid%d_top", csid_hw->hw_intf->hw_idx);
-	rc = cam_irq_controller_init(name, mem_base, csid_reg->top_irq_reg_info,
-		&csid_hw->top_irq_controller);
+	rc = cam_irq_controller_init(name, mem_base,
+		&csid_reg->top_irq_reg_info[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
+		&csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0]);
 
 	if (rc) {
 		CAM_ERR(CAM_ISP,
@@ -6675,8 +6750,9 @@ static int cam_ife_csid_hw_init_irq(
 	}
 
 	snprintf(name, CAM_CSID_IRQ_CTRL_NAME_LEN, "csid%d_rx", csid_hw->hw_intf->hw_idx);
-	rc = cam_irq_controller_init(name, mem_base, csid_reg->rx_irq_reg_info,
-		&csid_hw->rx_irq_controller);
+	rc = cam_irq_controller_init(name, mem_base,
+		&csid_reg->rx_irq_reg_info[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
+		&csid_hw->rx_irq_controller[CAM_IFE_CSID_RX_IRQ_STATUS_REG0]);
 
 	if (rc) {
 		CAM_ERR(CAM_ISP, "CSID:%u Failed to init CSID rx irq controller rc = %d",
@@ -6785,8 +6861,9 @@ int cam_ife_csid_ver2_irq_line_test(void *hw_priv)
 		csid_hw->hw_intf->hw_idx,
 		cam_io_r_mb(mem_base + csid_reg->cmn_reg->hw_version_addr));
 
-	rc = cam_irq_controller_test_irq_line(csid_hw->top_irq_controller, "CSID:%u",
-		csid_hw->hw_intf->hw_idx);
+	rc = cam_irq_controller_test_irq_line(
+		csid_hw->top_irq_controller[CAM_IFE_CSID_TOP_IRQ_STATUS_REG0],
+		"CSID:%d", csid_hw->hw_intf->hw_idx);
 
 	cam_ife_csid_disable_soc_resources(soc_info);
 	return rc;

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.h

@@ -133,6 +133,105 @@ struct cam_ife_csid_ver2_camif_data {
 	uint32_t epoch1;
 };
 
+struct cam_ife_csid_ver2_rx_cfg  {
+	uint32_t phy_sel;
+	uint32_t lane_type;
+	uint32_t lane_num;
+	uint32_t lane_cfg;
+	uint32_t tpg_mux_sel;
+	uint32_t tpg_num_sel;
+	uint32_t mup;
+	uint32_t epd_supported;
+	uint32_t top_irq_handle;
+	uint32_t rx2_irq_handle;
+	uint32_t irq_handle;
+	uint32_t err_irq_handle[CAM_IFE_CSID_RX_IRQ_STATUS_REG_MAX];
+	bool     dynamic_sensor_switch_en;
+};
+
+struct cam_ife_csid_ver2_csi2_rx_reg_info {
+	uint32_t irq_status_addr[CAM_IFE_CSID_RX_IRQ_STATUS_REG_MAX];
+	uint32_t irq_mask_addr[CAM_IFE_CSID_RX_IRQ_STATUS_REG_MAX];
+	uint32_t irq_clear_addr[CAM_IFE_CSID_RX_IRQ_STATUS_REG_MAX];
+	uint32_t irq_set_addr[CAM_IFE_CSID_RX_IRQ_STATUS_REG_MAX];
+	uint32_t cfg0_addr;
+	uint32_t cfg1_addr;
+	uint32_t capture_ctrl_addr;
+	uint32_t rst_strobes_addr;
+	uint32_t de_scramble_cfg0_addr;
+	uint32_t de_scramble_cfg1_addr;
+	uint32_t cap_unmap_long_pkt_hdr_0_addr;
+	uint32_t cap_unmap_long_pkt_hdr_1_addr;
+	uint32_t captured_short_pkt_0_addr;
+	uint32_t captured_short_pkt_1_addr;
+	uint32_t captured_long_pkt_0_addr;
+	uint32_t captured_long_pkt_1_addr;
+	uint32_t captured_long_pkt_ftr_addr;
+	uint32_t captured_cphy_pkt_hdr_addr;
+	uint32_t lane0_misr_addr;
+	uint32_t lane1_misr_addr;
+	uint32_t lane2_misr_addr;
+	uint32_t lane3_misr_addr;
+	uint32_t total_pkts_rcvd_addr;
+	uint32_t stats_ecc_addr;
+	uint32_t total_crc_err_addr;
+	uint32_t de_scramble_type3_cfg0_addr;
+	uint32_t de_scramble_type3_cfg1_addr;
+	uint32_t de_scramble_type2_cfg0_addr;
+	uint32_t de_scramble_type2_cfg1_addr;
+	uint32_t de_scramble_type1_cfg0_addr;
+	uint32_t de_scramble_type1_cfg1_addr;
+	uint32_t de_scramble_type0_cfg0_addr;
+	uint32_t de_scramble_type0_cfg1_addr;
+
+	/*configurations */
+	uint32_t rst_srb_all;
+	uint32_t rst_done_shift_val;
+	uint32_t irq_mask_all;
+	uint32_t misr_enable_shift_val;
+	uint32_t vc_mode_shift_val;
+	uint32_t capture_long_pkt_en_shift;
+	uint32_t capture_short_pkt_en_shift;
+	uint32_t capture_cphy_pkt_en_shift;
+	uint32_t capture_long_pkt_dt_shift;
+	uint32_t capture_long_pkt_vc_shift;
+	uint32_t capture_short_pkt_vc_shift;
+	uint32_t capture_cphy_pkt_dt_shift;
+	uint32_t capture_cphy_pkt_vc_shift;
+	uint32_t ecc_correction_shift_en;
+	uint32_t phy_bist_shift_en;
+	uint32_t epd_mode_shift_en;
+	uint32_t eotp_shift_en;
+	uint32_t dyn_sensor_switch_shift_en;
+	uint32_t rup_aup_latch_shift;
+	bool     rup_aup_latch_supported;
+	uint32_t phy_num_mask;
+	uint32_t vc_mask;
+	uint32_t wc_mask;
+	uint32_t dt_mask;
+	uint32_t vc_shift;
+	uint32_t dt_shift;
+	uint32_t wc_shift;
+	uint32_t calc_crc_mask;
+	uint32_t expected_crc_mask;
+	uint32_t calc_crc_shift;
+	uint32_t lane_num_shift;
+	uint32_t lane_cfg_shift;
+	uint32_t phy_type_shift;
+	uint32_t phy_num_shift;
+	uint32_t tpg_mux_en_shift;
+	uint32_t tpg_num_sel_shift;
+	uint32_t long_pkt_strobe_rst_shift;
+	uint32_t short_pkt_strobe_rst_shift;
+	uint32_t cphy_pkt_strobe_rst_shift;
+	uint32_t unmapped_pkt_strobe_rst_shift;
+	uint32_t fatal_err_mask[CAM_IFE_CSID_RX_IRQ_STATUS_REG_MAX];
+	uint32_t part_fatal_err_mask[CAM_IFE_CSID_RX_IRQ_STATUS_REG_MAX];
+	uint32_t non_fatal_err_mask[CAM_IFE_CSID_RX_IRQ_STATUS_REG_MAX];
+	uint32_t debug_irq_mask[CAM_IFE_CSID_RX_IRQ_STATUS_REG_MAX];
+	uint32_t top_irq_mask[CAM_IFE_CSID_TOP_IRQ_STATUS_REG_MAX];
+};
+
 /*
  *struct cam_ife_csid_ver2_rup_aup_mask: place holder for rup/aup mask parameter
  *
@@ -393,7 +492,7 @@ struct cam_ife_csid_ver2_path_reg_info {
 	uint32_t rup_mask;
 	uint32_t aup_mask;
 	uint32_t rup_aup_set_mask;
-	uint32_t top_irq_mask;
+	uint32_t top_irq_mask[CAM_IFE_CSID_TOP_IRQ_STATUS_REG_MAX];
 	uint32_t epoch0_cfg_val;
 	uint32_t epoch1_cfg_val;
 	uint32_t epoch0_shift_val;
@@ -415,10 +514,10 @@ struct cam_ife_csid_ver2_common_reg_info {
 	uint32_t aup_cmd_addr;
 	uint32_t offline_cmd_addr;
 	uint32_t shdr_master_slave_cfg_addr;
-	uint32_t top_irq_status_addr;
-	uint32_t top_irq_mask_addr;
-	uint32_t top_irq_clear_addr;
-	uint32_t top_irq_set_addr;
+	uint32_t top_irq_status_addr[CAM_IFE_CSID_TOP_IRQ_STATUS_REG_MAX];
+	uint32_t top_irq_mask_addr[CAM_IFE_CSID_TOP_IRQ_STATUS_REG_MAX];
+	uint32_t top_irq_clear_addr[CAM_IFE_CSID_TOP_IRQ_STATUS_REG_MAX];
+	uint32_t top_irq_set_addr[CAM_IFE_CSID_TOP_IRQ_STATUS_REG_MAX];
 	uint32_t irq_cmd_addr;
 	uint32_t buf_done_irq_status_addr;
 	uint32_t buf_done_irq_mask_addr;
@@ -550,8 +649,8 @@ struct cam_ife_csid_ver2_common_reg_info {
 	uint32_t rdi_irq_mask_all;
 	uint32_t ppp_irq_mask_all;
 	uint32_t udi_irq_mask_all;
-	uint32_t top_err_irq_mask;
-	uint32_t top_reset_irq_mask;
+	uint32_t top_err_irq_mask[CAM_IFE_CSID_TOP_IRQ_STATUS_REG_MAX];
+	uint32_t top_reset_irq_mask[CAM_IFE_CSID_TOP_IRQ_STATUS_REG_MAX];
 	uint32_t top_buf_done_irq_mask;
 	uint32_t epoch_factor;
 	uint32_t decode_format_payload_only;
@@ -592,7 +691,7 @@ struct cam_ife_csid_ver2_reg_info {
 	struct cam_irq_controller_reg_info               *path_irq_reg_info[
 		CAM_IFE_PIX_PATH_RES_MAX];
 	const struct cam_ife_csid_ver2_common_reg_info   *cmn_reg;
-	const struct cam_ife_csid_csi2_rx_reg_info       *csi2_reg;
+	const struct cam_ife_csid_ver2_csi2_rx_reg_info  *csi2_reg;
 	const struct cam_ife_csid_ver2_path_reg_info     *path_reg[
 						    CAM_IFE_PIX_PATH_RES_MAX];
 	const struct cam_ife_csid_ver2_top_reg_info      *top_reg;
@@ -601,10 +700,13 @@ struct cam_ife_csid_ver2_reg_info {
 		    CAM_IFE_CSID_HW_NUM_MAX];
 	const int                                         input_core_sel[
 		    CAM_IFE_CSID_HW_NUM_MAX][CAM_IFE_CSID_INPUT_CORE_SEL_MAX];
-	const struct cam_ife_csid_irq_desc               *rx_irq_desc;
+	const struct cam_ife_csid_irq_desc               (*rx_irq_desc)[][32];
 	const struct cam_ife_csid_irq_desc               *path_irq_desc;
-	const struct cam_ife_csid_top_irq_desc           *top_irq_desc;
-	const uint32_t                                    num_top_err_irqs;
+	const struct cam_ife_csid_top_irq_desc           (*top_irq_desc)[][32];
+	const uint32_t                                   *num_top_err_irqs;
+	const uint32_t                                   *num_rx_err_irqs;
+	const uint32_t                                    num_top_regs;
+	const uint32_t                                    num_rx_regs;
 };
 
 /*
@@ -653,7 +755,7 @@ struct cam_ife_csid_ver2_hw {
 						    [CAM_IFE_PIX_PATH_RES_MAX];
 	struct cam_ife_csid_cid_data           cid_data[CAM_IFE_CSID_CID_MAX];
 	struct cam_ife_csid_ver2_top_cfg       top_cfg;
-	struct cam_ife_csid_rx_cfg             rx_cfg;
+	struct cam_ife_csid_ver2_rx_cfg        rx_cfg;
 	struct cam_ife_csid_hw_counters        counters;
 	struct cam_ife_csid_hw_flags           flags;
 	struct cam_ife_csid_debug_info         debug_info;
@@ -667,8 +769,10 @@ struct cam_ife_csid_ver2_hw {
 	spinlock_t                             lock_state;
 	spinlock_t                             path_payload_lock;
 	spinlock_t                             rx_payload_lock;
-	void                                  *top_irq_controller;
-	void                                  *rx_irq_controller;
+	void                                  *top_irq_controller
+						[CAM_IFE_CSID_TOP_IRQ_STATUS_REG_MAX];
+	void                                  *rx_irq_controller
+						[CAM_IFE_CSID_RX_IRQ_STATUS_REG_MAX];
 	void                                  *path_irq_controller[CAM_IFE_PIX_PATH_RES_MAX];
 	void                                  *buf_done_irq_controller;
 	struct cam_hw_intf                    *hw_intf;
@@ -684,8 +788,10 @@ struct cam_ife_csid_ver2_hw {
 	void                                  *tasklet;
 	int                                    reset_irq_handle;
 	int                                    buf_done_irq_handle;
-	int                                    top_err_irq_handle;
-	int                                    top_info_irq_handle;
+	int                                    top_err_irq_handle
+						[CAM_IFE_CSID_TOP_IRQ_STATUS_REG_MAX];
+	int                                    top_info_irq_handle
+						[CAM_IFE_CSID_TOP_IRQ_STATUS_REG_MAX];
 	enum cam_isp_hw_sync_mode              sync_mode;
 	uint32_t                               mup;
 	atomic_t                               discard_frame_per_path;
@@ -718,7 +824,7 @@ struct cam_ife_csid_ver2_res_mini_dump {
 struct cam_ife_csid_ver2_mini_dump_data {
 	struct cam_ife_csid_ver2_res_mini_dump  res[CAM_IFE_PIX_PATH_RES_MAX];
 	struct cam_ife_csid_hw_flags            flags;
-	struct cam_ife_csid_rx_cfg              rx_cfg;
+	struct cam_ife_csid_ver2_rx_cfg         rx_cfg;
 	struct cam_ife_csid_cid_data            cid_data[CAM_IFE_CSID_CID_MAX];
 	uint64_t                                clk_rate;
 	uint8_t                                 hw_state;

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite680.h

@@ -13,107 +13,112 @@
 #include "cam_irq_controller.h"
 #include "cam_isp_hw_mgr_intf.h"
 
-static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_680_rx_irq_desc[] = {
-	{
-		.bitmask = BIT(0),
-		.desc = "DL0_EOT",
-	},
-	{
-		.bitmask = BIT(1),
-		.desc = "DL1_EOT",
-	},
-	{
-		.bitmask = BIT(2),
-		.desc = "DL2_EOT",
-	},
-	{
-		.bitmask = BIT(3),
-		.desc = "DL3_EOT",
-	},
-	{
-		.bitmask = BIT(4),
-		.desc = "DL0_SOT",
-	},
-	{
-		.bitmask = BIT(5),
-		.desc = "DL1_SOT",
-	},
-	{
-		.bitmask = BIT(6),
-		.desc = "DL2_SOT",
-	},
-	{
-		.bitmask = BIT(7),
-		.desc = "DL3_SOT",
-	},
-	{
-		.bitmask = BIT(8),
-		.desc = "LONG_PKT",
-	},
-	{
-		.bitmask = BIT(9),
-		.desc = "SHORT_PKT",
-	},
-	{
-		.bitmask = BIT(10),
-		.desc = "CPHY_PKT_HDR",
-	},
-	{
-		.bitmask = BIT(11),
-		.desc = "ERROR_CPHY_EOT_RECEPTION",
-	},
-	{
-		.bitmask = BIT(12),
-		.desc = "ERROR_CPHY_SOT_RECEPTION",
-	},
-	{
-		.bitmask = BIT(13),
-		.desc = "ERROR_CPHY_PH_CRC",
-	},
-	{
-		.bitmask = BIT(14),
-		.desc = "WARNING_ECC",
-	},
-	{
-		.bitmask = BIT(15),
-		.desc = "ERROR_LANE0_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(16),
-		.desc = "ERROR_LANE1_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(17),
-		.desc = "ERROR_LANE2_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(18),
-		.desc = "ERROR_LANE3_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(19),
-		.desc = "ERROR_CRC",
-	},
-	{
-		.bitmask = BIT(20),
-		.desc = "ERROR_ECC",
-	},
-	{
-		.bitmask = BIT(21),
-		.desc = "ERROR_MMAPPED_VC_DT",
-	},
-	{
-		.bitmask = BIT(22),
-		.desc = "ERROR_UNMAPPED_VC_DT",
-	},
-	{
-		.bitmask = BIT(23),
-		.desc = "ERROR_STREAM_UNDERFLOW",
-	},
+static uint32_t cam_ife_csid_680_lite_num_top_regs[] = {0,};
+
+static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_680_rx_irq_desc[][32] = {
 	{
-		.bitmask = BIT(24),
-		.desc = "ERROR_UNBOUNDED_FRAME",
+		{
+			.bitmask = BIT(0),
+			.desc = "DL0_EOT",
+		},
+		{
+			.bitmask = BIT(1),
+			.desc = "DL1_EOT",
+		},
+		{
+			.bitmask = BIT(2),
+			.desc = "DL2_EOT",
+		},
+		{
+			.bitmask = BIT(3),
+			.desc = "DL3_EOT",
+		},
+		{
+			.bitmask = BIT(4),
+			.desc = "DL0_SOT",
+		},
+		{
+			.bitmask = BIT(5),
+			.desc = "DL1_SOT",
+		},
+		{
+			.bitmask = BIT(6),
+			.desc = "DL2_SOT",
+		},
+		{
+			.bitmask = BIT(7),
+			.desc = "DL3_SOT",
+		},
+		{
+			.bitmask = BIT(8),
+			.desc = "LONG_PKT",
+		},
+		{
+			.bitmask = BIT(9),
+			.desc = "SHORT_PKT",
+		},
+		{
+			.bitmask = BIT(10),
+			.desc = "CPHY_PKT_HDR",
+		},
+		{
+			.bitmask = BIT(11),
+			.desc = "ERROR_CPHY_EOT_RECEPTION",
+		},
+		{
+			.bitmask = BIT(12),
+			.desc = "ERROR_CPHY_SOT_RECEPTION",
+		},
+		{
+			.bitmask = BIT(13),
+			.desc = "ERROR_CPHY_PH_CRC",
+		},
+		{
+			.bitmask = BIT(14),
+			.desc = "WARNING_ECC",
+		},
+		{
+			.bitmask = BIT(15),
+			.desc = "ERROR_LANE0_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(16),
+			.desc = "ERROR_LANE1_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(17),
+			.desc = "ERROR_LANE2_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(18),
+			.desc = "ERROR_LANE3_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(19),
+			.desc = "ERROR_CRC",
+		},
+		{
+			.bitmask = BIT(20),
+			.desc = "ERROR_ECC",
+		},
+		{
+			.bitmask = BIT(21),
+			.desc = "ERROR_MMAPPED_VC_DT",
+		},
+		{
+			.bitmask = BIT(22),
+			.desc = "ERROR_UNMAPPED_VC_DT",
+		},
+		{
+			.bitmask = BIT(23),
+			.desc = "ERROR_STREAM_UNDERFLOW",
+		},
+		{
+			.bitmask = BIT(24),
+			.desc = "ERROR_UNBOUNDED_FRAME",
+		},
 	},
+	{}
 };
 
 static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_680_path_irq_desc[] = {
@@ -364,10 +369,10 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.rup_aup_cmd_addr                        = 0x18,
 	.offline_cmd_addr                        = 0x1C,
 	.shdr_master_slave_cfg_addr              = 0x20,
-	.top_irq_status_addr                     = 0x7C,
-	.top_irq_mask_addr                       = 0x80,
-	.top_irq_clear_addr                      = 0x84,
-	.top_irq_set_addr                        = 0x88,
+	.top_irq_status_addr                     = {0x7C,},
+	.top_irq_mask_addr                       = {0x80,},
+	.top_irq_clear_addr                      = {0x84,},
+	.top_irq_set_addr                        = {0x88,},
 	.buf_done_irq_status_addr                = 0x8C,
 	.buf_done_irq_mask_addr                  = 0x90,
 	.buf_done_irq_clear_addr                 = 0x94,
@@ -420,7 +425,7 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.rst_cmd_sw_reset_complete_val                = 0x2,
 	.rst_cmd_irq_ctrl_only_val                    = 0x4,
 	.timestamp_strobe_val                         = 0x2,
-	.top_reset_irq_mask                           = 0x1,
+	.top_reset_irq_mask                           = {0x1,},
 	.top_buf_done_irq_mask                        = 0x2000,
 	.global_reset                                 = 1,
 	.rup_supported                                = 1,
@@ -429,12 +434,12 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.camif_irq_support                            = true,
 };
 
-static struct cam_ife_csid_csi2_rx_reg_info
+static struct cam_ife_csid_ver2_csi2_rx_reg_info
 	cam_ife_csid_lite_680_csi2_reg_info = {
-		.irq_status_addr                      = 0x9C,
-		.irq_mask_addr                        = 0xA0,
-		.irq_clear_addr                       = 0xA4,
-		.irq_set_addr                         = 0xA8,
+		.irq_status_addr                      = {0x9C,},
+		.irq_mask_addr                        = {0xA0,},
+		.irq_clear_addr                       = {0xA4,},
+		.irq_set_addr                         = {0xA8,},
 		/*CSI2 rx control */
 		.cfg0_addr                            = 0x200,
 		.cfg1_addr                            = 0x204,
@@ -501,10 +506,10 @@ static struct cam_ife_csid_csi2_rx_reg_info
 		.short_pkt_strobe_rst_shift           = 1,
 		.cphy_pkt_strobe_rst_shift            = 2,
 		.unmapped_pkt_strobe_rst_shift        = 3,
-		.fatal_err_mask                       = 0x19FA800,
-		.part_fatal_err_mask                  = 0x0001000,
-		.non_fatal_err_mask                   = 0x0200000,
-		.top_irq_mask                         = 0x4,
+		.top_irq_mask                         = {0x4,},
+		.fatal_err_mask                       = {0x19FA800,},
+		.part_fatal_err_mask                  = {0x0001000,},
+		.non_fatal_err_mask                   = {0x0200000,},
 };
 
 static struct cam_ife_csid_ver2_path_reg_info
@@ -599,7 +604,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                  = 0x400000,
 		.eof_irq_mask                     = 0x8,
 		.rup_aup_mask                     = 0x10001,
-		.top_irq_mask                     = 0x10,
+		.top_irq_mask                     = {0x10,},
 };
 
 static struct cam_ife_csid_ver2_path_reg_info
@@ -691,7 +696,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                = 0x400000,
 		.eof_irq_mask                   = 0x8,
 		.rup_aup_mask                   = 0x100010,
-		.top_irq_mask                   = 0x100,
+		.top_irq_mask                   = {0x100,},
 		.epoch0_shift_val               = 16,
 		.epoch1_shift_val               = 0,
 };
@@ -785,7 +790,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                = 0x400000,
 		.eof_irq_mask                   = 0x8,
 		.rup_aup_mask                   = 0x200020,
-		.top_irq_mask                   = 0x200,
+		.top_irq_mask                   = {0x200,},
 		.epoch0_shift_val               = 16,
 		.epoch1_shift_val               = 0,
 };
@@ -879,7 +884,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                = 0x400000,
 		.eof_irq_mask                   = 0x8,
 		.rup_aup_mask                   = 0x400040,
-		.top_irq_mask                   = 0x400,
+		.top_irq_mask                   = {0x400,},
 		.epoch0_shift_val               = 16,
 		.epoch1_shift_val               = 0,
 };
@@ -973,7 +978,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                = 0x400000,
 		.eof_irq_mask                   = 0x8,
 		.rup_aup_mask                   = 0x800080,
-		.top_irq_mask                   = 0x800,
+		.top_irq_mask                   = {0x800,},
 		.epoch0_shift_val               = 16,
 		.epoch1_shift_val               = 0,
 };
@@ -999,7 +1004,10 @@ static struct cam_ife_csid_ver2_reg_info cam_ife_csid_lite_680_reg_info = {
 	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_2] = &cam_ife_csid_lite_680_rdi_2_reg_info,
 	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_3] = &cam_ife_csid_lite_680_rdi_3_reg_info,
 	.need_top_cfg = 0,
-	.rx_irq_desc        = cam_ife_csid_lite_680_rx_irq_desc,
+	.rx_irq_desc        = &cam_ife_csid_lite_680_rx_irq_desc,
 	.path_irq_desc      = cam_ife_csid_lite_680_path_irq_desc,
+	.num_top_err_irqs   = cam_ife_csid_680_lite_num_top_regs,
+	.num_top_regs       = 1,
+	.num_rx_regs        = 1,
 };
 #endif /* _CAM_IFE_CSID_LITE_680_H_ */

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite780.h

@@ -13,109 +13,113 @@
 #include "cam_irq_controller.h"
 #include "cam_isp_hw_mgr_intf.h"
 
-static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_780_rx_irq_desc[] = {
+static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_780_rx_irq_desc[][32] = {
 	{
-		.bitmask = BIT(0),
-		.desc = "DL0_EOT",
-	},
-	{
-		.bitmask = BIT(1),
-		.desc = "DL1_EOT",
-	},
-	{
-		.bitmask = BIT(2),
-		.desc = "DL2_EOT",
-	},
-	{
-		.bitmask = BIT(3),
-		.desc = "DL3_EOT",
-	},
-	{
-		.bitmask = BIT(4),
-		.desc = "DL0_SOT",
-	},
-	{
-		.bitmask = BIT(5),
-		.desc = "DL1_SOT",
-	},
-	{
-		.bitmask = BIT(6),
-		.desc = "DL2_SOT",
-	},
-	{
-		.bitmask = BIT(7),
-		.desc = "DL3_SOT",
-	},
-	{
-		.bitmask = BIT(8),
-		.desc = "LONG_PKT",
-	},
-	{
-		.bitmask = BIT(9),
-		.desc = "SHORT_PKT",
-	},
-	{
-		.bitmask = BIT(10),
-		.desc = "CPHY_PKT_HDR",
-	},
-	{
-		.bitmask = BIT(11),
-		.desc = "ERROR_CPHY_EOT_RECEPTION",
-	},
-	{
-		.bitmask = BIT(12),
-		.desc = "ERROR_CPHY_SOT_RECEPTION",
-	},
-	{
-		.bitmask = BIT(13),
-		.desc = "ERROR_CPHY_PH_CRC",
-	},
-	{
-		.bitmask = BIT(14),
-		.desc = "WARNING_ECC",
-	},
-	{
-		.bitmask = BIT(15),
-		.desc = "ERROR_LANE0_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(16),
-		.desc = "ERROR_LANE1_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(17),
-		.desc = "ERROR_LANE2_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(18),
-		.desc = "ERROR_LANE3_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(19),
-		.desc = "ERROR_CRC",
-	},
-	{
-		.bitmask = BIT(20),
-		.desc = "ERROR_ECC",
-	},
-	{
-		.bitmask = BIT(21),
-		.desc = "ERROR_MMAPPED_VC_DT",
-	},
-	{
-		.bitmask = BIT(22),
-		.desc = "ERROR_UNMAPPED_VC_DT",
-	},
-	{
-		.bitmask = BIT(23),
-		.desc = "ERROR_STREAM_UNDERFLOW",
-	},
-	{
-		.bitmask = BIT(24),
-		.desc = "ERROR_UNBOUNDED_FRAME",
+		{
+			.bitmask = BIT(0),
+			.desc = "DL0_EOT",
+		},
+		{
+			.bitmask = BIT(1),
+			.desc = "DL1_EOT",
+		},
+		{
+			.bitmask = BIT(2),
+			.desc = "DL2_EOT",
+		},
+		{
+			.bitmask = BIT(3),
+			.desc = "DL3_EOT",
+		},
+		{
+			.bitmask = BIT(4),
+			.desc = "DL0_SOT",
+		},
+		{
+			.bitmask = BIT(5),
+			.desc = "DL1_SOT",
+		},
+		{
+			.bitmask = BIT(6),
+			.desc = "DL2_SOT",
+		},
+		{
+			.bitmask = BIT(7),
+			.desc = "DL3_SOT",
+		},
+		{
+			.bitmask = BIT(8),
+			.desc = "LONG_PKT",
+		},
+		{
+			.bitmask = BIT(9),
+			.desc = "SHORT_PKT",
+		},
+		{
+			.bitmask = BIT(10),
+			.desc = "CPHY_PKT_HDR",
+		},
+		{
+			.bitmask = BIT(11),
+			.desc = "ERROR_CPHY_EOT_RECEPTION",
+		},
+		{
+			.bitmask = BIT(12),
+			.desc = "ERROR_CPHY_SOT_RECEPTION",
+		},
+		{
+			.bitmask = BIT(13),
+			.desc = "ERROR_CPHY_PH_CRC",
+		},
+		{
+			.bitmask = BIT(14),
+			.desc = "WARNING_ECC",
+		},
+		{
+			.bitmask = BIT(15),
+			.desc = "ERROR_LANE0_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(16),
+			.desc = "ERROR_LANE1_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(17),
+			.desc = "ERROR_LANE2_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(18),
+			.desc = "ERROR_LANE3_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(19),
+			.desc = "ERROR_CRC",
+		},
+		{
+			.bitmask = BIT(20),
+			.desc = "ERROR_ECC",
+		},
+		{
+			.bitmask = BIT(21),
+			.desc = "ERROR_MMAPPED_VC_DT",
+		},
+		{
+			.bitmask = BIT(22),
+			.desc = "ERROR_UNMAPPED_VC_DT",
+		},
+		{
+			.bitmask = BIT(23),
+			.desc = "ERROR_STREAM_UNDERFLOW",
+		},
+		{
+			.bitmask = BIT(24),
+			.desc = "ERROR_UNBOUNDED_FRAME",
+		},
 	},
 };
 
+
+
 static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_780_path_irq_desc[] = {
 	{
 		.bitmask = BIT(0),
@@ -247,34 +251,40 @@ static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_780_path_irq_desc[]
 	},
 };
 
-static const struct cam_ife_csid_top_irq_desc cam_ife_csid_lite_780_top_irq_desc[] = {
-	{
-		.bitmask  = BIT(1),
-		.err_type = CAM_ISP_HW_ERROR_CSID_SENSOR_SWITCH_ERROR,
-		.err_name = "FATAL_SENSOR_SWITCHING_IRQ",
-		.desc = "Fatal Error duirng dynamically switching between 2 sensors",
-	},
+static const struct cam_ife_csid_top_irq_desc cam_ife_csid_lite_780_top_irq_desc[][32] = {
 	{
-		.bitmask  = BIT(18),
-		.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
-		.err_name = "ERROR_NO_VOTE_DN",
-		.desc = "vote_up is asserted before IDLE is encountered in a frame",
-	},
-	{
-		.bitmask  = BIT(19),
-		.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
-		.err_name = "ERROR_VOTE_UP_LATE",
-		.desc = "vote_up is asserted at the same time as an SOF",
-	},
-	{
-		.bitmask  = BIT(20),
-		.err_type = CAM_ISP_HW_ERROR_CSID_OUTPUT_FIFO_OVERFLOW,
-		.err_name = "ERROR_RDI_LINE_BUFFER_CONFLICT",
-		.desc = "Two or more RDIs programmed to access the shared line buffer",
-		.err_handler = cam_ife_csid_hw_ver2_rdi_line_buffer_conflict_handler,
+		{
+			.bitmask  = BIT(1),
+			.err_type = CAM_ISP_HW_ERROR_CSID_SENSOR_SWITCH_ERROR,
+			.err_name = "FATAL_SENSOR_SWITCHING_IRQ",
+			.desc = "Fatal Error duirng dynamically switching between 2 sensors",
+		},
+		{
+			.bitmask  = BIT(18),
+			.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
+			.err_name = "ERROR_NO_VOTE_DN",
+			.desc = "vote_up is asserted before IDLE is encountered in a frame",
+		},
+		{
+			.bitmask  = BIT(19),
+			.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
+			.err_name = "ERROR_VOTE_UP_LATE",
+			.desc = "vote_up is asserted at the same time as an SOF",
+		},
+		{
+			.bitmask  = BIT(20),
+			.err_type = CAM_ISP_HW_ERROR_CSID_OUTPUT_FIFO_OVERFLOW,
+			.err_name = "ERROR_RDI_LINE_BUFFER_CONFLICT",
+			.desc = "Two or more RDIs programmed to access the shared line buffer",
+			.err_handler = cam_ife_csid_hw_ver2_rdi_line_buffer_conflict_handler,
+		},
 	},
 };
 
+static const uint32_t cam_ife_csid_lite_780_num_top_irq_desc[] = {
+	ARRAY_SIZE(cam_ife_csid_lite_780_top_irq_desc[0]),
+};
+
 static struct cam_irq_register_set cam_ife_csid_lite_780_irq_reg_set[9] = {
 	/* Top */
 	{
@@ -396,10 +406,10 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.rup_aup_cmd_addr                             = 0x18,
 	.offline_cmd_addr                             = 0x1C,
 	.shdr_master_slave_cfg_addr                   = 0x20,
-	.top_irq_status_addr                          = 0x7C,
-	.top_irq_mask_addr                            = 0x80,
-	.top_irq_clear_addr                           = 0x84,
-	.top_irq_set_addr                             = 0x88,
+	.top_irq_status_addr                          = {0x7C,},
+	.top_irq_mask_addr                            = {0x80,},
+	.top_irq_clear_addr                           = {0x84,},
+	.top_irq_set_addr                             = {0x88,},
 	.buf_done_irq_status_addr                     = 0x8C,
 	.buf_done_irq_mask_addr                       = 0x90,
 	.buf_done_irq_clear_addr                      = 0x94,
@@ -463,7 +473,9 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.format_measure_height_shift_val              = 0x10,
 	.format_measure_width_mask_val                = 0xFFFF,
 	.format_measure_width_shift_val               = 0x0,
-	.top_reset_irq_mask                           = 0x1,
+	.top_reset_irq_mask = {
+		0x1,
+	},
 	.top_buf_done_irq_mask                        = 0x2000,
 	.decode_format_payload_only                   = 0xF,
 	.phy_sel_base_idx                             = 1,
@@ -471,12 +483,12 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.camif_irq_support                            = true,
 };
 
-static struct cam_ife_csid_csi2_rx_reg_info
+static struct cam_ife_csid_ver2_csi2_rx_reg_info
 	cam_ife_csid_lite_780_csi2_reg_info = {
-		.irq_status_addr                      = 0x9C,
-		.irq_mask_addr                        = 0xA0,
-		.irq_clear_addr                       = 0xA4,
-		.irq_set_addr                         = 0xA8,
+		.irq_status_addr                      = {0x9C,},
+		.irq_mask_addr                        = {0xA0,},
+		.irq_clear_addr                       = {0xA4,},
+		.irq_set_addr                         = {0xA8,},
 		/*CSI2 rx control */
 		.cfg0_addr                            = 0x200,
 		.cfg1_addr                            = 0x204,
@@ -545,10 +557,10 @@ static struct cam_ife_csid_csi2_rx_reg_info
 		.short_pkt_strobe_rst_shift           = 1,
 		.cphy_pkt_strobe_rst_shift            = 2,
 		.unmapped_pkt_strobe_rst_shift        = 3,
-		.fatal_err_mask                       = 0x19FA800,
-		.part_fatal_err_mask                  = 0x0001000,
-		.non_fatal_err_mask                   = 0x0200000,
-		.top_irq_mask                         = 0x4,
+		.top_irq_mask                         = {0x4,},
+		.fatal_err_mask                       = {0x19FA800,},
+		.part_fatal_err_mask                  = {0x0001000,},
+		.non_fatal_err_mask                   = {0x0200000,},
 };
 
 static struct cam_ife_csid_ver2_path_reg_info
@@ -643,7 +655,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                      = 0x400000,
 		.eof_irq_mask                         = 0x8,
 		.rup_aup_mask                         = 0x10001,
-		.top_irq_mask                         = 0x10,
+		.top_irq_mask                         = {0x10,},
 };
 
 static struct cam_ife_csid_ver2_path_reg_info
@@ -730,13 +742,13 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en                   = 1,
 		.fatal_err_mask                      = 0x20186001,
 		.non_fatal_err_mask                  = 0x12000004,
-		.sof_irq_mask                         = 0x10,
-		.rup_irq_mask                         = 0x800000,
-		.epoch0_irq_mask                      = 0x200000,
-		.epoch1_irq_mask                      = 0x400000,
-		.eof_irq_mask                         = 0x8,
+		.sof_irq_mask                        = 0x10,
+		.rup_irq_mask                        = 0x800000,
+		.epoch0_irq_mask                     = 0x200000,
+		.epoch1_irq_mask                     = 0x400000,
+		.eof_irq_mask                        = 0x8,
 		.rup_aup_mask                        = 0x100010,
-		.top_irq_mask                        = 0x100,
+		.top_irq_mask                        = {0x100,},
 };
 
 static struct cam_ife_csid_ver2_path_reg_info
@@ -822,13 +834,13 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en                   = 1,
 		.fatal_err_mask                      = 0x20186001,
 		.non_fatal_err_mask                  = 0x12000004,
-		.sof_irq_mask                         = 0x10,
-		.rup_irq_mask                         = 0x800000,
-		.epoch0_irq_mask                      = 0x200000,
-		.epoch1_irq_mask                      = 0x400000,
-		.eof_irq_mask                         = 0x8,
+		.sof_irq_mask                        = 0x10,
+		.rup_irq_mask                        = 0x800000,
+		.epoch0_irq_mask                     = 0x200000,
+		.epoch1_irq_mask                     = 0x400000,
+		.eof_irq_mask                        = 0x8,
 		.rup_aup_mask                        = 0x200020,
-		.top_irq_mask                        = 0x200,
+		.top_irq_mask                        = {0x200,},
 };
 
 static struct cam_ife_csid_ver2_path_reg_info
@@ -914,13 +926,13 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en                   = 1,
 		.fatal_err_mask                      = 0x20186001,
 		.non_fatal_err_mask                  = 0x12000004,
-		.sof_irq_mask                         = 0x10,
-		.rup_irq_mask                         = 0x800000,
-		.epoch0_irq_mask                      = 0x200000,
-		.epoch1_irq_mask                      = 0x400000,
-		.eof_irq_mask                         = 0x8,
+		.sof_irq_mask                        = 0x10,
+		.rup_irq_mask                        = 0x800000,
+		.epoch0_irq_mask                     = 0x200000,
+		.epoch1_irq_mask                     = 0x400000,
+		.eof_irq_mask                        = 0x8,
 		.rup_aup_mask                        = 0x400040,
-		.top_irq_mask                        = 0x400,
+		.top_irq_mask                        = {0x400,},
 };
 
 static struct cam_ife_csid_ver2_path_reg_info
@@ -1006,13 +1018,13 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.ccif_violation_en                   = 1,
 		.fatal_err_mask                      = 0x20186001,
 		.non_fatal_err_mask                  = 0x12000004,
-		.sof_irq_mask                         = 0x10,
-		.rup_irq_mask                         = 0x800000,
-		.epoch0_irq_mask                      = 0x200000,
-		.epoch1_irq_mask                      = 0x400000,
-		.eof_irq_mask                         = 0x8,
+		.sof_irq_mask                        = 0x10,
+		.rup_irq_mask                        = 0x800000,
+		.epoch0_irq_mask                     = 0x200000,
+		.epoch1_irq_mask                     = 0x400000,
+		.eof_irq_mask                        = 0x8,
 		.rup_aup_mask                        = 0x800080,
-		.top_irq_mask                        = 0x800,
+		.top_irq_mask                        = {0x800,},
 };
 
 static struct cam_ife_csid_ver2_reg_info cam_ife_csid_lite_780_reg_info = {
@@ -1037,9 +1049,11 @@ static struct cam_ife_csid_ver2_reg_info cam_ife_csid_lite_780_reg_info = {
 	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_2] = &cam_ife_csid_lite_780_rdi_2_reg_info,
 	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_3] = &cam_ife_csid_lite_780_rdi_3_reg_info,
 	.need_top_cfg = 0,
-	.rx_irq_desc        = cam_ife_csid_lite_780_rx_irq_desc,
+	.rx_irq_desc        = &cam_ife_csid_lite_780_rx_irq_desc,
 	.path_irq_desc      = cam_ife_csid_lite_780_path_irq_desc,
-	.top_irq_desc       = cam_ife_csid_lite_780_top_irq_desc,
-	.num_top_err_irqs   = ARRAY_SIZE(cam_ife_csid_lite_780_top_irq_desc),
+	.top_irq_desc       = &cam_ife_csid_lite_780_top_irq_desc,
+	.num_top_err_irqs   = cam_ife_csid_lite_780_num_top_irq_desc,
+	.num_top_regs       = 1,
+	.num_rx_regs        = 1,
 };
 #endif /* _CAM_IFE_CSID_LITE_780_H_ */

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite880.h

@@ -15,114 +15,116 @@
 
 /* Offsets might not match due to csid secure regs at beginning of reg space */
 
-static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_880_rx_irq_desc[] = {
+static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_880_rx_irq_desc[][32] = {
 	{
-		.bitmask = BIT(0),
-		.desc = "DL0_EOT",
-	},
-	{
-		.bitmask = BIT(1),
-		.desc = "DL1_EOT",
-	},
-	{
-		.bitmask = BIT(2),
-		.desc = "DL2_EOT",
-	},
-	{
-		.bitmask = BIT(3),
-		.desc = "DL3_EOT",
-	},
-	{
-		.bitmask = BIT(4),
-		.desc = "DL0_SOT",
-	},
-	{
-		.bitmask = BIT(5),
-		.desc = "DL1_SOT",
-	},
-	{
-		.bitmask = BIT(6),
-		.desc = "DL2_SOT",
-	},
-	{
-		.bitmask = BIT(7),
-		.desc = "DL3_SOT",
-	},
-	{
-		.bitmask = BIT(8),
-		.desc = "LONG_PKT",
-	},
-	{
-		.bitmask = BIT(9),
-		.desc = "SHORT_PKT",
-	},
-	{
-		.bitmask = BIT(10),
-		.desc = "CPHY_PKT_HDR",
-	},
-	{
-		.bitmask = BIT(11),
-		.desc = "ERROR_CPHY_EOT_RECEPTION",
-	},
-	{
-		.bitmask = BIT(12),
-		.desc = "ERROR_CPHY_SOT_RECEPTION",
-	},
-	{
-		.bitmask = BIT(13),
-		.desc = "ERROR_CPHY_PH_CRC",
-	},
-	{
-		.bitmask = BIT(14),
-		.desc = "WARNING_ECC",
-	},
-	{
-		.bitmask = BIT(15),
-		.desc = "ERROR_LANE0_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(16),
-		.desc = "ERROR_LANE1_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(17),
-		.desc = "ERROR_LANE2_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(18),
-		.desc = "ERROR_LANE3_FIFO_OVERFLOW",
-	},
-	{
-		.bitmask = BIT(19),
-		.desc = "ERROR_CRC",
-	},
-	{
-		.bitmask = BIT(20),
-		.desc = "ERROR_ECC",
-	},
-	{
-		.bitmask = BIT(21),
-		.desc = "ERROR_MMAPPED_VC_DT",
-	},
-	{
-		.bitmask = BIT(22),
-		.desc = "ERROR_UNMAPPED_VC_DT",
-	},
-	{
-		.bitmask = BIT(23),
-		.desc = "ERROR_STREAM_UNDERFLOW",
-	},
-	{
-		.bitmask = BIT(24),
-		.desc = "ERROR_UNBOUNDED_FRAME",
-	},
-	{
-		.bitmask = BIT(25),
-		.desc = "ERROR_ILLEGAL_PROGRAMMING_IRQ",
-	},
-	{
-		.bitmask = BIT(26),
-		.desc = "INFO_SENSOR_MODE_ID_CHANGE_IRQ",
+		{
+			.bitmask = BIT(0),
+			.desc = "DL0_EOT",
+		},
+		{
+			.bitmask = BIT(1),
+			.desc = "DL1_EOT",
+		},
+		{
+			.bitmask = BIT(2),
+			.desc = "DL2_EOT",
+		},
+		{
+			.bitmask = BIT(3),
+			.desc = "DL3_EOT",
+		},
+		{
+			.bitmask = BIT(4),
+			.desc = "DL0_SOT",
+		},
+		{
+			.bitmask = BIT(5),
+			.desc = "DL1_SOT",
+		},
+		{
+			.bitmask = BIT(6),
+			.desc = "DL2_SOT",
+		},
+		{
+			.bitmask = BIT(7),
+			.desc = "DL3_SOT",
+		},
+		{
+			.bitmask = BIT(8),
+			.desc = "LONG_PKT",
+		},
+		{
+			.bitmask = BIT(9),
+			.desc = "SHORT_PKT",
+		},
+		{
+			.bitmask = BIT(10),
+			.desc = "CPHY_PKT_HDR",
+		},
+		{
+			.bitmask = BIT(11),
+			.desc = "ERROR_CPHY_EOT_RECEPTION",
+		},
+		{
+			.bitmask = BIT(12),
+			.desc = "ERROR_CPHY_SOT_RECEPTION",
+		},
+		{
+			.bitmask = BIT(13),
+			.desc = "ERROR_CPHY_PH_CRC",
+		},
+		{
+			.bitmask = BIT(14),
+			.desc = "WARNING_ECC",
+		},
+		{
+			.bitmask = BIT(15),
+			.desc = "ERROR_LANE0_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(16),
+			.desc = "ERROR_LANE1_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(17),
+			.desc = "ERROR_LANE2_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(18),
+			.desc = "ERROR_LANE3_FIFO_OVERFLOW",
+		},
+		{
+			.bitmask = BIT(19),
+			.desc = "ERROR_CRC",
+		},
+		{
+			.bitmask = BIT(20),
+			.desc = "ERROR_ECC",
+		},
+		{
+			.bitmask = BIT(21),
+			.desc = "ERROR_MMAPPED_VC_DT",
+		},
+		{
+			.bitmask = BIT(22),
+			.desc = "ERROR_UNMAPPED_VC_DT",
+		},
+		{
+			.bitmask = BIT(23),
+			.desc = "ERROR_STREAM_UNDERFLOW",
+		},
+		{
+			.bitmask = BIT(24),
+			.desc = "ERROR_UNBOUNDED_FRAME",
+		},
+		{
+			.bitmask = BIT(25),
+			.desc = "ERROR_ILLEGAL_PROGRAMMING_IRQ",
+		},
+		{
+			.bitmask = BIT(26),
+			.desc = "INFO_SENSOR_MODE_ID_CHANGE_IRQ",
+		},
 	},
 };
 
@@ -257,34 +259,39 @@ static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_880_path_irq_desc[]
 	},
 };
 
-static const struct cam_ife_csid_top_irq_desc cam_ife_csid_lite_880_top_irq_desc[] = {
-	{
-		.bitmask  = BIT(1),
-		.err_type = CAM_ISP_HW_ERROR_CSID_SENSOR_SWITCH_ERROR,
-		.err_name = "FATAL_SENSOR_SWITCHING_IRQ",
-		.desc = "Fatal Error duirng dynamically switching between 2 sensors",
-	},
-	{
-		.bitmask  = BIT(18),
-		.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
-		.err_name = "ERROR_NO_VOTE_DN",
-		.desc = "vote_up is asserted before IDLE is encountered in a frame",
-	},
-	{
-		.bitmask  = BIT(19),
-		.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
-		.err_name = "ERROR_VOTE_UP_LATE",
-		.desc = "vote_up is asserted at the same time as an SOF",
-	},
+static const struct cam_ife_csid_top_irq_desc cam_ife_csid_lite_880_top_irq_desc[][32] = {
 	{
-		.bitmask  = BIT(20),
-		.err_type = CAM_ISP_HW_ERROR_CSID_OUTPUT_FIFO_OVERFLOW,
-		.err_name = "ERROR_RDI_LINE_BUFFER_CONFLICT",
-		.desc = "Two or more RDIs programmed to access the shared line buffer",
-		.err_handler = cam_ife_csid_hw_ver2_rdi_line_buffer_conflict_handler,
+		{
+			.bitmask  = BIT(1),
+			.err_type = CAM_ISP_HW_ERROR_CSID_SENSOR_SWITCH_ERROR,
+			.err_name = "FATAL_SENSOR_SWITCHING_IRQ",
+			.desc = "Fatal Error duirng dynamically switching between 2 sensors",
+		},
+		{
+			.bitmask  = BIT(18),
+			.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
+			.err_name = "ERROR_NO_VOTE_DN",
+			.desc = "vote_up is asserted before IDLE is encountered in a frame",
+		},
+		{
+			.bitmask  = BIT(19),
+			.err_type = CAM_ISP_HW_ERROR_RECOVERY_OVERFLOW,
+			.err_name = "ERROR_VOTE_UP_LATE",
+			.desc = "vote_up is asserted at the same time as an SOF",
+		},
+		{
+			.bitmask  = BIT(20),
+			.err_type = CAM_ISP_HW_ERROR_CSID_OUTPUT_FIFO_OVERFLOW,
+			.err_name = "ERROR_RDI_LINE_BUFFER_CONFLICT",
+			.desc = "Two or more RDIs programmed to access the shared line buffer",
+			.err_handler = cam_ife_csid_hw_ver2_rdi_line_buffer_conflict_handler,
+		},
 	},
 };
 
+static const uint32_t cam_ife_csid_lite_880_num_top_irq_desc[] = {
+			ARRAY_SIZE(cam_ife_csid_lite_880_top_irq_desc[0])};
+
 static struct cam_irq_register_set cam_ife_csid_lite_880_irq_reg_set[9] = {
 	/* Top */
 	{
@@ -405,10 +412,10 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.rup_aup_cmd_addr                             = 0x0018,
 	.offline_cmd_addr                             = 0x001C,
 	.shdr_master_slave_cfg_addr                   = 0x0020,
-	.top_irq_status_addr                          = 0x007C,
-	.top_irq_mask_addr                            = 0x0080,
-	.top_irq_clear_addr                           = 0x0084,
-	.top_irq_set_addr                             = 0x0088,
+	.top_irq_status_addr                          = {0x007C,},
+	.top_irq_mask_addr                            = {0x0080,},
+	.top_irq_clear_addr                           = {0x0084,},
+	.top_irq_set_addr                             = {0x0088,},
 	.buf_done_irq_status_addr                     = 0x008C,
 	.buf_done_irq_mask_addr                       = 0x0090,
 	.buf_done_irq_clear_addr                      = 0x0094,
@@ -472,7 +479,7 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.format_measure_height_shift_val              = 0x10,
 	.format_measure_width_mask_val                = 0xFFFF,
 	.format_measure_width_shift_val               = 0x0,
-	.top_reset_irq_mask                           = 0x1,
+	.top_reset_irq_mask                           = {0x1,},
 	.top_buf_done_irq_mask                        = 0x2000,
 	.decode_format_payload_only                   = 0xF,
 	.phy_sel_base_idx                             = 1,
@@ -480,12 +487,12 @@ static struct cam_ife_csid_ver2_common_reg_info
 	.camif_irq_support                            = true,
 };
 
-static struct cam_ife_csid_csi2_rx_reg_info
+static struct cam_ife_csid_ver2_csi2_rx_reg_info
 	cam_ife_csid_lite_880_csi2_reg_info = {
-		.irq_status_addr                      = 0x009C,
-		.irq_mask_addr                        = 0x00A0,
-		.irq_clear_addr                       = 0x00A4,
-		.irq_set_addr                         = 0x00A8,
+		.irq_status_addr                      = {0x009C,},
+		.irq_mask_addr                        = {0x00A0,},
+		.irq_clear_addr                       = {0x00A4,},
+		.irq_set_addr                         = {0x00A8,},
 		/*CSI2 rx control */
 		.cfg0_addr                            = 0x0200,
 		.cfg1_addr                            = 0x0204,
@@ -554,10 +561,10 @@ static struct cam_ife_csid_csi2_rx_reg_info
 		.short_pkt_strobe_rst_shift           = 1,
 		.cphy_pkt_strobe_rst_shift            = 2,
 		.unmapped_pkt_strobe_rst_shift        = 3,
-		.fatal_err_mask                       = 0x19FA800,
-		.part_fatal_err_mask                  = 0x0001000,
-		.non_fatal_err_mask                   = 0x0200000,
-		.top_irq_mask                         = 0x4,
+		.top_irq_mask                         = {0x4,},
+		.fatal_err_mask                       = {0x19FA800,},
+		.part_fatal_err_mask                  = {0x0001000,},
+		.non_fatal_err_mask                   = {0x0200000,},
 };
 
 static struct cam_ife_csid_ver2_path_reg_info
@@ -652,7 +659,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                      = 0x400000,
 		.eof_irq_mask                         = 0x8,
 		.rup_aup_mask                         = 0x10001,
-		.top_irq_mask                         = 0x10,
+		.top_irq_mask                         = {0x10,},
 };
 
 static struct cam_ife_csid_ver2_path_reg_info
@@ -745,7 +752,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                     = 0x400000,
 		.eof_irq_mask                        = 0x8,
 		.rup_aup_mask                        = 0x100010,
-		.top_irq_mask                        = 0x100,
+		.top_irq_mask                        = {0x100,},
 };
 
 static struct cam_ife_csid_ver2_path_reg_info
@@ -838,7 +845,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                     = 0x400000,
 		.eof_irq_mask                        = 0x8,
 		.rup_aup_mask                        = 0x200020,
-		.top_irq_mask                        = 0x200,
+		.top_irq_mask                        = {0x200,},
 };
 
 static struct cam_ife_csid_ver2_path_reg_info
@@ -931,7 +938,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                     = 0x400000,
 		.eof_irq_mask                        = 0x8,
 		.rup_aup_mask                        = 0x400040,
-		.top_irq_mask                        = 0x400,
+		.top_irq_mask                        = {0x400,},
 };
 
 static struct cam_ife_csid_ver2_path_reg_info
@@ -1024,7 +1031,7 @@ static struct cam_ife_csid_ver2_path_reg_info
 		.epoch1_irq_mask                     = 0x400000,
 		.eof_irq_mask                        = 0x8,
 		.rup_aup_mask                        = 0x800080,
-		.top_irq_mask                        = 0x800,
+		.top_irq_mask                        = {0x800,},
 };
 
 static struct cam_ife_csid_ver2_reg_info cam_ife_csid_lite_880_reg_info = {
@@ -1048,9 +1055,11 @@ static struct cam_ife_csid_ver2_reg_info cam_ife_csid_lite_880_reg_info = {
 	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_2] = &cam_ife_csid_lite_880_rdi_2_reg_info,
 	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_3] = &cam_ife_csid_lite_880_rdi_3_reg_info,
 	.need_top_cfg = 0,
-	.rx_irq_desc        = cam_ife_csid_lite_880_rx_irq_desc,
+	.rx_irq_desc        = &cam_ife_csid_lite_880_rx_irq_desc,
 	.path_irq_desc      = cam_ife_csid_lite_880_path_irq_desc,
-	.top_irq_desc       = cam_ife_csid_lite_880_top_irq_desc,
-	.num_top_err_irqs   = ARRAY_SIZE(cam_ife_csid_lite_880_top_irq_desc),
+	.top_irq_desc       = &cam_ife_csid_lite_880_top_irq_desc,
+	.num_top_err_irqs   = cam_ife_csid_lite_880_num_top_irq_desc,
+	.num_top_regs       = 1,
+	.num_rx_regs        = 1,
 };
 #endif /* _CAM_IFE_CSID_LITE_780_H_ */

drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h

@@ -24,6 +24,22 @@ enum cam_ife_csid_hw_irq_regs {
 	CAM_IFE_CSID_IRQ_REGISTERS_MAX,
 };
 
+/**
+ * enum cam_ife_csid_top_irq_regs - Specify the top irq reg
+ */
+enum cam_ife_csid_top_irq_regs {
+	CAM_IFE_CSID_TOP_IRQ_STATUS_REG0,
+	CAM_IFE_CSID_TOP_IRQ_STATUS_REG_MAX,
+};
+
+/**
+ * enum cam_ife_csid_rx_irq_regs - Specify the rx irq reg
+ */
+enum cam_ife_csid_rx_irq_regs {
+	CAM_IFE_CSID_RX_IRQ_STATUS_REG0,
+	CAM_IFE_CSID_RX_IRQ_STATUS_REG_MAX,
+};
+
 /**
  * enum cam_ife_csid_input_core_type - Specify the csid input core
  */