From 5298a2471e1ffc2dfa3d91a3094344acc6d33e54 Mon Sep 17 00:00:00 2001 From: Jigar Agrawal Date: Fri, 28 Aug 2020 19:32:46 -0700 Subject: [PATCH] msm: camera: cdm: Support CDM2.1 for new Chipset Add support single-context CDM for CDM2.1. CRs-fixed: 2770438 Change-Id: I894ebc9fc770fe25c7cd1c18099d3c06af319245 Signed-off-by: Jigar Agrawal --- drivers/cam_cdm/cam_cdm.h | 5 +- drivers/cam_cdm/cam_cdm_hw_core.c | 99 ++++++++++--------- drivers/cam_cdm/cam_cdm_intf_api.h | 1 + drivers/cam_cdm/cam_cdm_soc.c | 4 + drivers/cam_cdm/cam_cdm_soc.h | 2 +- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c | 25 +++-- drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h | 3 +- drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c | 10 +- .../hw_utils/cam_isp_packet_parser.c | 5 +- .../hw_utils/include/cam_isp_packet_parser.h | 17 +++- .../isp_hw_mgr/isp_hw/include/cam_isp_hw.h | 3 + .../isp_hw/include/cam_vfe_hw_intf.h | 1 + 12 files changed, 107 insertions(+), 68 deletions(-) diff --git a/drivers/cam_cdm/cam_cdm.h b/drivers/cam_cdm/cam_cdm.h index 714bff32c3..540c03b018 100644 --- a/drivers/cam_cdm/cam_cdm.h +++ b/drivers/cam_cdm/cam_cdm.h @@ -503,7 +503,6 @@ struct cam_cdm_bl_fifo { * @gen_irq: memory region in which gen_irq command will be written * @cpas_handle: handle for cpas driver * @arbitration: type of arbitration to be used for the CDM - * @rst_done_cnt: CMD reset done count */ struct cam_cdm { uint32_t index; @@ -526,13 +525,13 @@ struct cam_cdm { struct cam_cdm_hw_mem gen_irq[CAM_CDM_BL_FIFO_MAX]; uint32_t cpas_handle; enum cam_cdm_arbitration arbitration; - uint32_t rst_done_cnt; }; /* struct cam_cdm_private_dt_data - CDM hw custom dt data */ struct cam_cdm_private_dt_data { bool dt_cdm_shared; bool config_fifo; + bool is_single_ctx_cdm; uint8_t priority_group; uint32_t fifo_depth[CAM_CDM_BL_FIFO_MAX]; uint32_t dt_num_supported_clients; @@ -550,10 +549,10 @@ struct cam_cdm_intf_devices { /* struct cam_cdm_intf_mgr - CDM mgr interface device struct */ struct cam_cdm_intf_mgr { bool probe_done; - struct cam_cdm_intf_devices nodes[CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM]; uint32_t cdm_count; uint32_t dt_supported_hw_cdm; int32_t refcount; + struct cam_cdm_intf_devices nodes[CAM_CDM_INTF_MGR_MAX_SUPPORTED_CDM]; }; int cam_cdm_intf_register_hw_cdm(struct cam_hw_intf *hw, diff --git a/drivers/cam_cdm/cam_cdm_hw_core.c b/drivers/cam_cdm/cam_cdm_hw_core.c index d3c00193d9..c03e0eec29 100644 --- a/drivers/cam_cdm/cam_cdm_hw_core.c +++ b/drivers/cam_cdm/cam_cdm_hw_core.c @@ -66,14 +66,13 @@ static const struct of_device_id msm_cam_hw_cdm_dt_match[] = { .data = &cam_cdm_2_1_reg_offset, }, { - .compatible = CAM_HW_CDM_OPE_NAME_2_1, + .compatible = CAM_HW_CDM_RT_NAME_2_1, .data = &cam_cdm_2_1_reg_offset, }, { - .compatible = CAM_HW_CDM_IFE_NAME_2_1, + .compatible = CAM_HW_CDM_OPE_NAME_2_1, .data = &cam_cdm_2_1_reg_offset, }, - {} }; static enum cam_cdm_id cam_hw_cdm_get_id_by_name(char *name) @@ -102,12 +101,12 @@ static enum cam_cdm_id cam_hw_cdm_get_id_by_name(char *name) if (strnstr(name, CAM_HW_CDM_CPAS_NAME_2_1, strlen(CAM_HW_CDM_CPAS_NAME_2_1))) return CAM_CDM_CPAS; + if (strnstr(name, CAM_HW_CDM_RT_NAME_2_1, + strlen(CAM_HW_CDM_RT_NAME_2_1))) + return CAM_CDM_RT; if (strnstr(name, CAM_HW_CDM_OPE_NAME_2_1, strlen(CAM_HW_CDM_OPE_NAME_2_1))) return CAM_CDM_OPE; - if (strnstr(name, CAM_HW_CDM_IFE_NAME_2_1, - strlen(CAM_HW_CDM_IFE_NAME_2_1))) - return CAM_CDM_IFE; return CAM_CDM_MAX; } @@ -320,7 +319,7 @@ void cam_hw_cdm_dump_bl_fifo_data(struct cam_hw_info *cdm_hw) void cam_hw_cdm_dump_core_debug_registers( struct cam_hw_info *cdm_hw) { - uint32_t dump_reg, core_dbg; + uint32_t dump_reg, dump_reg1, dump_reg2, core_dbg; int i; struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; @@ -353,6 +352,19 @@ void cam_hw_cdm_dump_core_debug_registers( CAM_INFO(CAM_CDM, "CDM HW AHB dump not enable"); } + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->icl_reg->data_regs->icl_inv_data, + &dump_reg); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->icl_reg->misc_regs->icl_inv_bl_addr, + &dump_reg1); + cam_cdm_read_hw_reg(cdm_hw, + core->offsets->cmn_reg->icl_reg->misc_regs->icl_status, + &dump_reg2); + CAM_INFO(CAM_CDM, + "Last Inv Cmd Log(ICL)Status: 0x%x, Last Inv cmd: 0x%x, Last Inv bl_addr: 0x%x", + dump_reg2, dump_reg, dump_reg1); + cam_hw_cdm_dump_bl_fifo_data(cdm_hw); CAM_INFO(CAM_CDM, "CDM HW default dump"); @@ -360,9 +372,7 @@ void cam_hw_cdm_dump_core_debug_registers( core->offsets->cmn_reg->core_cfg, &dump_reg); CAM_INFO(CAM_CDM, "CDM HW core cfg=%x", dump_reg); - for (i = 0; i < - core->offsets->reg_data->num_bl_fifo_irq; - i++) { + for (i = 0; i < core->offsets->reg_data->num_bl_fifo_irq; i++) { cam_cdm_read_hw_reg(cdm_hw, core->offsets->irq_reg[i]->irq_status, &dump_reg); CAM_INFO(CAM_CDM, "CDM HW irq status%d=%x", i, dump_reg); @@ -412,7 +422,6 @@ enum cam_cdm_arbitration cam_cdm_get_arbitration_type( arbitration = CAM_CDM_ARBITRATION_NONE; goto end; } - switch (id) { case CAM_CDM_CPAS: arbitration = CAM_CDM_ARBITRATION_ROUND_ROBIN; @@ -427,14 +436,13 @@ end: int cam_hw_cdm_set_cdm_blfifo_cfg(struct cam_hw_info *cdm_hw) { - uint32_t blfifo_cfg_mask = 0; int rc = 0, i; struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; - blfifo_cfg_mask = blfifo_cfg_mask | - CAM_CDM_BL_FIFO_REQ_SIZE_MAX; - for (i = 0; i < core->offsets->reg_data->num_bl_fifo_irq; i++) { + if (!core->bl_fifo[i].bl_depth) + continue; + rc = cam_cdm_write_hw_reg(cdm_hw, core->offsets->irq_reg[i]->irq_mask, 0x70003); if (rc) { @@ -447,24 +455,10 @@ int cam_hw_cdm_set_cdm_blfifo_cfg(struct cam_hw_info *cdm_hw) if (core->hw_version >= CAM_CDM_VERSION_2_0) { for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) { - blfifo_cfg_mask = blfifo_cfg_mask | - (core->bl_fifo[i].bl_depth + rc = cam_cdm_write_hw_reg(cdm_hw, + core->offsets->bl_fifo_reg[i]->bl_fifo_cfg, + core->bl_fifo[i].bl_depth << CAM_CDM_BL_FIFO_LENGTH_CFG_SHIFT); - rc = cam_cdm_write_hw_reg(cdm_hw, - core->offsets->bl_fifo_reg[i]->bl_fifo_cfg, - blfifo_cfg_mask); - if (rc) { - CAM_ERR(CAM_CDM, - "Unable to write to cdm irq mask register"); - rc = -EIO; - goto end; - } - } - } else { - for (i = 0; i < core->offsets->reg_data->num_bl_fifo; i++) { - rc = cam_cdm_write_hw_reg(cdm_hw, - core->offsets->bl_fifo_reg[i]->bl_fifo_cfg, - blfifo_cfg_mask); if (rc) { CAM_ERR(CAM_CDM, "Unable to write to cdm irq mask register"); @@ -484,7 +478,7 @@ int cam_hw_cdm_set_cdm_core_cfg(struct cam_hw_info *cdm_hw) int rc; struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info; struct cam_cdm_private_dt_data *pvt_data = - pvt_data = cdm_hw->soc_info.soc_private; + (struct cam_cdm_private_dt_data *)cdm_hw->soc_info.soc_private; cfg_mask = cfg_mask | CAM_CDM_AHB_STOP_ON_ERROR| @@ -501,7 +495,8 @@ int cam_hw_cdm_set_cdm_core_cfg(struct cam_hw_info *cdm_hw) } if (cdm_version >= CAM_CDM_VERSION_2_0) { - if (core->id != CAM_CDM_CPAS) + if (core->id != CAM_CDM_CPAS && + (!pvt_data->is_single_ctx_cdm)) cfg_mask = cfg_mask | CAM_CDM_IMPLICIT_WAIT_EN; if (core->arbitration == CAM_CDM_ARBITRATION_ROUND_ROBIN) @@ -1281,6 +1276,7 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) struct cam_hw_info *cdm_hw = data; struct cam_cdm *cdm_core = cdm_hw->core_info; struct cam_cdm_work_payload *payload[CAM_CDM_BL_FIFO_MAX] = {0}; + uint8_t rst_done_cnt = 0; uint32_t user_data = 0; uint32_t irq_status[CAM_CDM_BL_FIFO_MAX] = {0}; uint32_t irq_context_summary = 0xF; @@ -1332,7 +1328,7 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) continue; if (irq_status[i] & CAM_CDM_IRQ_STATUS_RST_DONE_MASK) { - cdm_core->rst_done_cnt++; + rst_done_cnt++; continue; } @@ -1391,17 +1387,15 @@ irqreturn_t cam_hw_cdm_irq(int irq_num, void *data) kfree(payload[i]); } } - if (cdm_core->rst_done_cnt == - cdm_core->offsets->reg_data->num_bl_fifo_irq) { + if (rst_done_cnt == cdm_core->offsets->reg_data->num_bl_fifo_irq) { CAM_DBG(CAM_CDM, "CDM HW reset done IRQ"); complete(&cdm_core->reset_complete); } - if (cdm_core->rst_done_cnt && - cdm_core->rst_done_cnt != - cdm_core->offsets->reg_data->num_bl_fifo_irq) + if (rst_done_cnt && + (rst_done_cnt != cdm_core->offsets->reg_data->num_bl_fifo_irq)) CAM_INFO(CAM_CDM, "Reset IRQ received for %d fifos instead of %d", - cdm_core->rst_done_cnt, + rst_done_cnt, cdm_core->offsets->reg_data->num_bl_fifo_irq); return IRQ_HANDLED; } @@ -1422,6 +1416,9 @@ int cam_hw_cdm_alloc_genirq_mem(void *hw_priv) genirq_alloc_cmd.smmu_hdl = cdm_core->iommu_hdl.non_secure; genirq_alloc_cmd.flags = CAM_MEM_FLAG_HW_READ_WRITE; for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { + if (!cdm_core->bl_fifo[i].bl_depth) + continue; + genirq_alloc_cmd.size = (8 * cdm_core->bl_fifo[i].bl_depth); rc = cam_mem_mgr_request_mem(&genirq_alloc_cmd, @@ -1478,7 +1475,7 @@ int cam_hw_cdm_reset_hw(struct cam_hw_info *cdm_hw, uint32_t handle) mutex_lock(&cdm_core->bl_fifo[i].fifo_lock); set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); - cdm_core->rst_done_cnt = 0; + reinit_completion(&cdm_core->reset_complete); /* First pause CDM, If it fails still proceed to reset CDM HW */ @@ -1486,6 +1483,9 @@ int cam_hw_cdm_reset_hw(struct cam_hw_info *cdm_hw, uint32_t handle) usleep_range(1000, 1010); for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { + if (!cdm_core->bl_fifo[i].bl_depth) + continue; + reset_val = reset_val | (1 << (i + CAM_CDM_BL_FIFO_FLUSH_SHIFT)); if (cam_cdm_write_hw_reg(cdm_hw, @@ -1549,7 +1549,6 @@ int cam_hw_cdm_handle_error_info( for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) mutex_lock(&cdm_core->bl_fifo[i].fifo_lock); - cdm_core->rst_done_cnt = 0; reinit_completion(&cdm_core->reset_complete); set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); set_bit(CAM_CDM_FLUSH_HW_STATUS, &cdm_core->cdm_status); @@ -1578,6 +1577,9 @@ int cam_hw_cdm_handle_error_info( cam_hw_cdm_dump_core_debug_registers(cdm_hw); for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { + if (!cdm_core->bl_fifo[i].bl_depth) + continue; + reset_val = reset_val | (1 << (i + CAM_CDM_BL_FIFO_FLUSH_SHIFT)); if (cam_cdm_write_hw_reg(cdm_hw, @@ -1811,10 +1813,14 @@ int cam_hw_cdm_init(void *hw_priv, goto disable_return; } else { CAM_DBG(CAM_CDM, "CDM Init success"); - for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) + for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { + if (!cdm_core->bl_fifo[i].bl_depth) + continue; + cam_cdm_write_hw_reg(cdm_hw, cdm_core->offsets->irq_reg[i]->irq_mask, 0x70003); + } rc = 0; goto end; } @@ -1860,7 +1866,6 @@ int cam_hw_cdm_deinit(void *hw_priv, } set_bit(CAM_CDM_RESET_HW_STATUS, &cdm_core->cdm_status); - cdm_core->rst_done_cnt = 0; reinit_completion(&cdm_core->reset_complete); /* First pause CDM, If it fails still proceed to reset CDM HW */ @@ -1868,6 +1873,9 @@ int cam_hw_cdm_deinit(void *hw_priv, usleep_range(1000, 1010); for (i = 0; i < cdm_core->offsets->reg_data->num_bl_fifo; i++) { + if (!cdm_core->bl_fifo[i].bl_depth) + continue; + reset_val = reset_val | (1 << (i + CAM_CDM_BL_FIFO_FLUSH_SHIFT)); if (cam_cdm_write_hw_reg(cdm_hw, @@ -1973,7 +1981,6 @@ static int cam_hw_cdm_component_bind(struct device *dev, goto release_private_mem; } - cdm_core->rst_done_cnt = 0; init_completion(&cdm_core->reset_complete); cdm_hw_intf->hw_priv = cdm_hw; cdm_hw_intf->hw_ops.get_hw_caps = cam_cdm_get_caps; diff --git a/drivers/cam_cdm/cam_cdm_intf_api.h b/drivers/cam_cdm/cam_cdm_intf_api.h index 58ffd4f8a0..adf6930593 100644 --- a/drivers/cam_cdm/cam_cdm_intf_api.h +++ b/drivers/cam_cdm/cam_cdm_intf_api.h @@ -22,6 +22,7 @@ enum cam_cdm_id { CAM_CDM_IPE1, CAM_CDM_BPS, CAM_CDM_VFE, + CAM_CDM_RT, CAM_CDM_MAX }; diff --git a/drivers/cam_cdm/cam_cdm_soc.c b/drivers/cam_cdm/cam_cdm_soc.c index ba4ff1ac6e..f2658448c3 100644 --- a/drivers/cam_cdm/cam_cdm_soc.c +++ b/drivers/cam_cdm/cam_cdm_soc.c @@ -114,6 +114,10 @@ int cam_cdm_soc_load_dt_private(struct platform_device *pdev, } + cdm_pvt_data->is_single_ctx_cdm = + of_property_read_bool(pdev->dev.of_node, + "single-context-cdm"); + rc = of_property_read_u8(pdev->dev.of_node, "cdm-priority-group", &cdm_pvt_data->priority_group); if (rc < 0) { diff --git a/drivers/cam_cdm/cam_cdm_soc.h b/drivers/cam_cdm/cam_cdm_soc.h index 59129c7031..11afd1f676 100644 --- a/drivers/cam_cdm/cam_cdm_soc.h +++ b/drivers/cam_cdm/cam_cdm_soc.h @@ -14,8 +14,8 @@ #define CAM_HW_CDM_CPAS_NAME_2_0 "qcom,cam-cpas-cdm2_0" #define CAM_HW_CDM_OPE_NAME_2_0 "qcom,cam-ope-cdm2_0" #define CAM_HW_CDM_CPAS_NAME_2_1 "qcom,cam-cpas-cdm2_1" +#define CAM_HW_CDM_RT_NAME_2_1 "qcom,cam-rt-cdm2_1" #define CAM_HW_CDM_OPE_NAME_2_1 "qcom,cam-ope-cdm2_1" -#define CAM_HW_CDM_IFE_NAME_2_1 "qcom,cam-ife-cdm2_1" int cam_hw_cdm_soc_get_dt_properties(struct cam_hw_info *cdm_hw, const struct of_device_id *table); diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index 99c25aa7d9..9ef62524bb 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -3001,7 +3001,6 @@ static int cam_ife_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args) uint32_t total_pd_port = 0; struct cam_isp_acquire_hw_info *acquire_hw_info = NULL; uint32_t input_size = 0; - uint32_t hw_version; CAM_DBG(CAM_ISP, "Enter..."); @@ -3110,15 +3109,16 @@ static int cam_ife_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args) goto free_cdm; } - cam_cpas_get_cpas_hw_version(&hw_version); - ife_ctx->hw_version = hw_version; - + cam_cpas_get_cpas_hw_version(&ife_ctx->hw_version); if (ife_ctx->is_dual) memcpy(cdm_acquire.identifier, "dualife", sizeof("dualife")); else memcpy(cdm_acquire.identifier, "ife", sizeof("ife")); - cdm_acquire.cell_index = ife_ctx->base[0].idx; + if (ife_ctx->is_dual) + cdm_acquire.cell_index = ife_ctx->master_hw_idx; + else + cdm_acquire.cell_index = ife_ctx->base[0].idx; cdm_acquire.handle = 0; cdm_acquire.userdata = ife_ctx; cdm_acquire.base_array_cnt = CAM_IFE_HW_NUM_MAX; @@ -3141,6 +3141,7 @@ static int cam_ife_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args) "Successfully acquired CDM Id: %d, CDM HW hdl=%x, is_dual=%d", cdm_acquire.id, cdm_acquire.handle, ife_ctx->is_dual); ife_ctx->cdm_handle = cdm_acquire.handle; + ife_ctx->cdm_id = cdm_acquire.id; if (cdm_acquire.id == CAM_CDM_IFE) ife_ctx->internal_cdm = true; atomic_set(&ife_ctx->cdm_done, 1); @@ -3242,7 +3243,6 @@ static int cam_ife_mgr_acquire_dev(void *hw_mgr_priv, void *acquire_hw_args) uint32_t total_pix_port = 0; uint32_t total_rdi_port = 0; uint32_t in_port_length = 0; - uint32_t hw_version; CAM_DBG(CAM_ISP, "Enter..."); @@ -3375,8 +3375,7 @@ static int cam_ife_mgr_acquire_dev(void *hw_mgr_priv, void *acquire_hw_args) goto free_res; } - cam_cpas_get_cpas_hw_version(&hw_version); - ife_ctx->hw_version = hw_version; + cam_cpas_get_cpas_hw_version(&ife_ctx->hw_version); ife_ctx->internal_cdm = false; if (ife_ctx->is_dual) @@ -3408,6 +3407,7 @@ static int cam_ife_mgr_acquire_dev(void *hw_mgr_priv, void *acquire_hw_args) if (cdm_acquire.id == CAM_CDM_IFE) ife_ctx->internal_cdm = true; ife_ctx->cdm_handle = cdm_acquire.handle; + ife_ctx->cdm_id = cdm_acquire.id; atomic_set(&ife_ctx->cdm_done, 1); acquire_args->ctxt_to_hw_map = ife_ctx; @@ -6219,6 +6219,7 @@ static int cam_ife_mgr_prepare_hw_update(void *hw_mgr_priv, bool frame_header_enable = false; struct cam_isp_prepare_hw_update_data *prepare_hw_data; struct cam_isp_frame_header_info frame_header_info; + struct cam_isp_change_base_args change_base_info = {0}; if (!hw_mgr_priv || !prepare_hw_update_args) { CAM_ERR(CAM_ISP, "Invalid args"); @@ -6289,9 +6290,11 @@ static int cam_ife_mgr_prepare_hw_update(void *hw_mgr_priv, /* Add change base */ if (!ctx->internal_cdm) { + change_base_info.base_idx = ctx->base[i].idx; + change_base_info.cdm_id = ctx->cdm_id; rc = cam_isp_add_change_base(prepare, &ctx->res_list_ife_src, - ctx->base[i].idx, &kmd_buf); + &change_base_info, &kmd_buf); if (rc) { CAM_ERR(CAM_ISP, "Failed in change base i=%d, idx=%d, rc=%d", @@ -6401,11 +6404,13 @@ static int cam_ife_mgr_prepare_hw_update(void *hw_mgr_priv, /* add reg update commands */ for (i = 0; i < ctx->num_base; i++) { + change_base_info.base_idx = ctx->base[i].idx; + change_base_info.cdm_id = ctx->cdm_id; /* Add change base */ if (!ctx->internal_cdm) { rc = cam_isp_add_change_base(prepare, &ctx->res_list_ife_src, - ctx->base[i].idx, &kmd_buf); + &change_base_info, &kmd_buf); if (rc) { CAM_ERR(CAM_ISP, diff --git a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h index 010c7dda16..7a5e658da1 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h +++ b/drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h @@ -74,6 +74,7 @@ struct cam_ife_hw_mgr_debug { * @cdm_ops cdm util operation pointer for building * cdm commands * @cdm_cmd cdm base and length request pointer + * @cdm_id cdm id of the acquired cdm * @sof_cnt sof count value per core, used for dual VFE * @epoch_cnt epoch count value per core, used for dual VFE * @eof_cnt eof count value per core, used for dual VFE @@ -130,7 +131,7 @@ struct cam_ife_hw_mgr_ctx { uint32_t cdm_handle; struct cam_cdm_utils_ops *cdm_ops; struct cam_cdm_bl_request *cdm_cmd; - + enum cam_cdm_id cdm_id; uint32_t sof_cnt[CAM_IFE_HW_NUM_MAX]; uint32_t epoch_cnt[CAM_IFE_HW_NUM_MAX]; uint32_t eof_cnt[CAM_IFE_HW_NUM_MAX]; diff --git a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c index 8a26c06e7c..8aa68af8ca 100644 --- a/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c +++ b/drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c @@ -4008,6 +4008,7 @@ static int cam_tfe_mgr_prepare_hw_update(void *hw_mgr_priv, bool fill_fence = true; struct cam_isp_prepare_hw_update_data *prepare_hw_data; struct cam_isp_frame_header_info frame_header_info; + struct cam_isp_change_base_args change_base_info = {0}; if (!hw_mgr_priv || !prepare_hw_update_args) { CAM_ERR(CAM_ISP, "Invalid args"); @@ -4060,9 +4061,12 @@ static int cam_tfe_mgr_prepare_hw_update(void *hw_mgr_priv, "change base i=%d, idx=%d", i, ctx->base[i].idx); + change_base_info.base_idx = ctx->base[i].idx; + change_base_info.cdm_id = CAM_CDM_MAX; + /* Add change base */ rc = cam_isp_add_change_base(prepare, &ctx->res_list_tfe_in, - ctx->base[i].idx, &kmd_buf); + &change_base_info, &kmd_buf); if (rc) { CAM_ERR(CAM_ISP, "Failed in change base i=%d, idx=%d, rc=%d", @@ -4157,9 +4161,11 @@ static int cam_tfe_mgr_prepare_hw_update(void *hw_mgr_priv, /* add reg update commands */ for (i = 0; i < ctx->num_base; i++) { + change_base_info.base_idx = ctx->base[i].idx; + change_base_info.cdm_id = CAM_CDM_MAX; /* Add change base */ rc = cam_isp_add_change_base(prepare, &ctx->res_list_tfe_in, - ctx->base[i].idx, &kmd_buf); + &change_base_info, &kmd_buf); if (rc) { CAM_ERR(CAM_ISP, "Failed in change base adding reg_update cmd i=%d, idx=%d, rc=%d", diff --git a/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c b/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c index 6cad5f6e73..3849708917 100644 --- a/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c +++ b/drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c @@ -15,7 +15,7 @@ int cam_isp_add_change_base( struct cam_hw_prepare_update_args *prepare, struct list_head *res_list_isp_src, - uint32_t base_idx, + struct cam_isp_change_base_args *change_base_args, struct cam_kmd_buf_info *kmd_buf_info) { int rc = -EINVAL; @@ -44,10 +44,11 @@ int cam_isp_add_change_base( continue; res = hw_mgr_res->hw_res[i]; - if (res->hw_intf->hw_idx != base_idx) + if (res->hw_intf->hw_idx != change_base_args->base_idx) continue; get_base.res = res; + get_base.cdm_id = change_base_args->cdm_id; get_base.cmd_type = CAM_ISP_HW_CMD_GET_CHANGE_BASE; get_base.cmd.cmd_buf_addr = kmd_buf_info->cpu_addr + kmd_buf_info->used_bytes/4; diff --git a/drivers/cam_isp/isp_hw_mgr/hw_utils/include/cam_isp_packet_parser.h b/drivers/cam_isp/isp_hw_mgr/hw_utils/include/cam_isp_packet_parser.h index 1be8507e20..ccd9907996 100644 --- a/drivers/cam_isp/isp_hw_mgr/hw_utils/include/cam_isp_packet_parser.h +++ b/drivers/cam_isp/isp_hw_mgr/hw_utils/include/cam_isp_packet_parser.h @@ -12,6 +12,7 @@ #include "cam_isp_hw_mgr.h" #include "cam_hw_intf.h" #include "cam_packet_util.h" +#include "cam_cdm_intf_api.h" /* enum cam_isp_cdm_bl_type - isp cdm packet type*/ enum cam_isp_cdm_bl_type { @@ -47,6 +48,17 @@ struct cam_isp_frame_header_info { uint32_t frame_header_res_id; }; +/* + * struct cam_isp_change_base_args + * + * @cdm_id: CDM id + * @base_idx: Base index + */ +struct cam_isp_change_base_args { + enum cam_cdm_id cdm_id; + uint32_t base_idx; +}; + /* * cam_isp_add_change_base() * @@ -56,8 +68,7 @@ struct cam_isp_frame_header_info { * * @prepare: Contain the packet and HW update variables * @res_list_isp_src: Resource list for IFE/VFE source - * @base_idx: Base or dev index of the IFE/VFE HW instance for - * which change change base need to be added + * @change_base_args: Arguments for Change base function * @kmd_buf_info: Kmd buffer to store the change base command * @return: 0 for success * -EINVAL for Fail @@ -65,7 +76,7 @@ struct cam_isp_frame_header_info { int cam_isp_add_change_base( struct cam_hw_prepare_update_args *prepare, struct list_head *res_list_isp_src, - uint32_t base_idx, + struct cam_isp_change_base_args *change_base_args, struct cam_kmd_buf_info *kmd_buf_info); /* diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h index de5b049960..b90705766e 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h @@ -12,6 +12,7 @@ #include "cam_soc_util.h" #include "cam_irq_controller.h" #include "cam_hw_intf.h" +#include "cam_cdm_intf_api.h" /* Maximum length of tag while dumping */ #define CAM_ISP_HW_DUMP_TAG_MAX_LEN 32 @@ -273,12 +274,14 @@ struct cam_isp_hw_get_res_for_mid { * * @res: Resource node * @cmd_type: Command type for which to get update + * @cdm_id : CDM id * @cmd: Command buffer information * */ struct cam_isp_hw_get_cmd_update { struct cam_isp_resource_node *res; enum cam_isp_hw_cmd_type cmd_type; + enum cam_cdm_id cdm_id; struct cam_isp_hw_cmd_buf_update cmd; union { void *data; diff --git a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_vfe_hw_intf.h b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_vfe_hw_intf.h index bd2c808bf1..1caf997c8f 100644 --- a/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_vfe_hw_intf.h +++ b/drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_vfe_hw_intf.h @@ -14,6 +14,7 @@ #define CAM_VFE_HW_NUM_MAX 7 #define VFE_CORE_BASE_IDX 0 +#define RT_BASE_IDX 2 /* * VBIF and BUS do not exist on same HW. * Hence both can be 1 below.