Merge "asoc: codecs: bolero: toggle zero gate for first hpf update"
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@@ -463,10 +463,10 @@ tx_hpf_set:
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snd_soc_component_update_bits(component,
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dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK,
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hpf_cut_off_freq << 5);
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snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x02);
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snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x02);
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/* Minimum 1 clk cycle delay is required as per HW spec */
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usleep_range(1000, 1010);
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snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x01);
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snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x00);
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}
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static void tx_macro_mute_update_callback(struct work_struct *work)
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@@ -878,6 +878,10 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
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tx_vol_ctl_reg, 0x20, 0x20);
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snd_soc_component_update_bits(component,
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hpf_gate_reg, 0x01, 0x00);
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/*
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* Minimum 1 clk cycle delay is required as per HW spec
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*/
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usleep_range(1000, 1010);
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hpf_cut_off_freq = (
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snd_soc_component_read32(component, dec_cfg_reg) &
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@@ -900,7 +904,7 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
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&tx_priv->tx_hpf_work[decimator].dwork,
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msecs_to_jiffies(300));
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snd_soc_component_update_bits(component,
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hpf_gate_reg, 0x02, 0x02);
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hpf_gate_reg, 0x03, 0x03);
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/*
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* Minimum 1 clk cycle delay is required as per HW spec
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*/
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