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@@ -666,6 +666,33 @@ static void hal_reo_shared_qaddr_write_be(hal_soc_handle_t hal_soc_hdl,
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reo_qref->rx_reo_queue_desc_addr_39_32);
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}
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+static void hal_reo_shared_qaddr_cache_clear_be(hal_soc_handle_t hal_soc_hdl)
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+{
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+ struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
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+ uint32_t reg_val = 0;
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+
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+ /* Set Qdesc clear bit to erase REO internal storage for Qdesc pointers
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+ * of 37 peer/tids
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+ */
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+ reg_val = HAL_REG_READ(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE));
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+ reg_val |= HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1);
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+ HAL_REG_WRITE(hal,
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+ HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
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+ reg_val);
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+
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+ /* Clear Qdesc clear bit to erase REO internal storage for Qdesc pointers
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+ * of 37 peer/tids
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+ */
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+ reg_val &= ~(HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1));
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+ HAL_REG_WRITE(hal,
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+ HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE),
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+ reg_val);
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+
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+ hal_verbose_debug("hal_soc: %pK :Setting CLEAR_DESC_ARRAY field of"
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+ "WCSS_UMAC_REO_R0_QDESC_ADDR_READ and resetting back"
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+ "to erase stale entries in reo storage: regval:%x", hal, reg_val);
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+}
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+
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/**
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* hal_reo_shared_qaddr_setup() - Allocate MLO and Non MLO reo queue
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* reference table shared between SW and HW and initialize in Qdesc Base0
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