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@@ -205,38 +205,124 @@ void dsi_phy_hw_v4_0_commit_phy_timing(struct dsi_phy_hw *phy,
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}
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/**
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- * enable() - Enable PHY hardware
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+ * cphy_enable() - Enable CPHY hardware
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* @phy: Pointer to DSI PHY hardware object.
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* @cfg: Per lane configurations for timing, strength and lane
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* configurations.
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*/
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-void dsi_phy_hw_v4_0_enable(struct dsi_phy_hw *phy,
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+static void dsi_phy_hw_cphy_enable(struct dsi_phy_hw *phy,
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struct dsi_phy_cfg *cfg)
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{
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- int rc = 0;
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- u32 status;
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- u32 const delay_us = 5;
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- u32 const timeout_us = 1000;
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struct dsi_phy_per_lane_cfgs *timing = &cfg->timing;
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u32 data;
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u32 minor_ver = 0;
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- bool less_than_1500_mhz = false;
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- u32 vreg_ctrl_0 = 0;
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+ /* For C-PHY, no low power settings for lower clk rate */
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+ u32 vreg_ctrl_0 = 0x51;
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u32 glbl_str_swi_cal_sel_ctrl = 0;
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u32 glbl_hstx_str_ctrl_0 = 0;
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u32 glbl_rescode_top_ctrl = 0;
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u32 glbl_rescode_bot_ctrl = 0;
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- if (dsi_phy_hw_v4_0_is_pll_on(phy))
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- DSI_PHY_WARN(phy, "PLL turned on before configuring PHY\n");
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+ if (phy->version == DSI_PHY_VERSION_4_1) {
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+ glbl_rescode_top_ctrl = 0x00;
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+ glbl_rescode_bot_ctrl = 0x3C;
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+ glbl_str_swi_cal_sel_ctrl = 0x00;
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+ glbl_hstx_str_ctrl_0 = 0x88;
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+ } else {
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+ glbl_str_swi_cal_sel_ctrl = 0x03;
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+ glbl_hstx_str_ctrl_0 = 0x66;
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+ glbl_rescode_top_ctrl = 0x03;
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+ glbl_rescode_bot_ctrl = 0x3c;
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+ }
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- /* wait for REFGEN READY */
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- rc = readl_poll_timeout_atomic(phy->base + DSIPHY_CMN_PHY_STATUS,
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- status, (status & BIT(0)), delay_us, timeout_us);
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- if (rc) {
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- DSI_PHY_ERR(phy, "Ref gen not ready. Aborting\n");
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- return;
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+ /* de-assert digital and pll power down */
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+ data = BIT(6) | BIT(5);
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+ DSI_W32(phy, DSIPHY_CMN_CTRL_0, data);
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+
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+ /* Assert PLL core reset */
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+ DSI_W32(phy, DSIPHY_CMN_PLL_CNTRL, 0x00);
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+
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+ /* turn off resync FIFO */
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+ DSI_W32(phy, DSIPHY_CMN_RBUF_CTRL, 0x00);
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+
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+ /* program CMN_CTRL_4 for minor_ver 2 chipsets*/
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+ minor_ver = DSI_R32(phy, DSIPHY_CMN_REVISION_ID0);
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+ minor_ver = minor_ver & (0xf0);
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+ if (minor_ver == 0x20)
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+ DSI_W32(phy, DSIPHY_CMN_CTRL_4, 0x04);
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+
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+ /* Configure PHY lane swap */
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+ dsi_phy_hw_v4_0_lane_swap_config(phy, &cfg->lane_map);
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+
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+ DSI_W32(phy, DSIPHY_CMN_GLBL_CTRL, BIT(6));
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+
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+ /* Enable LDO */
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+ DSI_W32(phy, DSIPHY_CMN_VREG_CTRL_0, vreg_ctrl_0);
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+ DSI_W32(phy, DSIPHY_CMN_VREG_CTRL_1, 0x55);
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+ DSI_W32(phy, DSIPHY_CMN_GLBL_STR_SWI_CAL_SEL_CTRL,
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+ glbl_str_swi_cal_sel_ctrl);
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+ DSI_W32(phy, DSIPHY_CMN_GLBL_HSTX_STR_CTRL_0, glbl_hstx_str_ctrl_0);
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+ DSI_W32(phy, DSIPHY_CMN_GLBL_PEMPH_CTRL_0, 0x11);
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+ DSI_W32(phy, DSIPHY_CMN_GLBL_PEMPH_CTRL_1, 0x01);
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+ DSI_W32(phy, DSIPHY_CMN_GLBL_RESCODE_OFFSET_TOP_CTRL,
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+ glbl_rescode_top_ctrl);
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+ DSI_W32(phy, DSIPHY_CMN_GLBL_RESCODE_OFFSET_BOT_CTRL,
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+ glbl_rescode_bot_ctrl);
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+ DSI_W32(phy, DSIPHY_CMN_GLBL_LPTX_STR_CTRL, 0x55);
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+
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+ /* Remove power down from all blocks */
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+ DSI_W32(phy, DSIPHY_CMN_CTRL_0, 0x7f);
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+
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+ DSI_W32(phy, DSIPHY_CMN_LANE_CTRL0, 0x17);
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+
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+ switch (cfg->pll_source) {
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+ case DSI_PLL_SOURCE_STANDALONE:
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+ case DSI_PLL_SOURCE_NATIVE:
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+ data = 0x0; /* internal PLL */
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+ break;
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+ case DSI_PLL_SOURCE_NON_NATIVE:
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+ data = 0x1; /* external PLL */
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+ break;
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+ default:
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+ break;
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}
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+ DSI_W32(phy, DSIPHY_CMN_CLK_CFG1, (data << 2)); /* set PLL src */
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+
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+ /* DSI PHY timings */
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+ DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_0, timing->lane_v4[0]);
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+ DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_4, timing->lane_v4[4]);
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+ DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_5, timing->lane_v4[5]);
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+ DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_6, timing->lane_v4[6]);
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+ DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_7, timing->lane_v4[7]);
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+ DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_8, timing->lane_v4[8]);
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+ DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_9, timing->lane_v4[9]);
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+ DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_10, timing->lane_v4[10]);
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+ DSI_W32(phy, DSIPHY_CMN_TIMING_CTRL_11, timing->lane_v4[11]);
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+
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+ /* DSI lane settings */
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+ dsi_phy_hw_v4_0_lane_settings(phy, cfg);
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+
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+ DSI_PHY_DBG(phy, "C-Phy enabled\n");
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+}
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+
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+/**
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+ * dphy_enable() - Enable DPHY hardware
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+ * @phy: Pointer to DSI PHY hardware object.
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+ * @cfg: Per lane configurations for timing, strength and lane
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+ * configurations.
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+ */
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+static void dsi_phy_hw_dphy_enable(struct dsi_phy_hw *phy,
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+ struct dsi_phy_cfg *cfg)
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+{
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+ struct dsi_phy_per_lane_cfgs *timing = &cfg->timing;
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+ u32 data;
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+ u32 minor_ver = 0;
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+ bool less_than_1500_mhz = false;
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+ u32 vreg_ctrl_0 = 0;
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+ u32 glbl_str_swi_cal_sel_ctrl = 0;
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+ u32 glbl_hstx_str_ctrl_0 = 0;
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+ u32 glbl_rescode_top_ctrl = 0;
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+ u32 glbl_rescode_bot_ctrl = 0;
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/* Alter PHY configurations if data rate less than 1.5GHZ*/
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if (cfg->bit_clk_rate_hz <= 1500000000)
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@@ -322,7 +408,39 @@ void dsi_phy_hw_v4_0_enable(struct dsi_phy_hw *phy,
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/* DSI lane settings */
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dsi_phy_hw_v4_0_lane_settings(phy, cfg);
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- DSI_PHY_DBG(phy, "Phy enabled\n");
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+ DSI_PHY_DBG(phy, "D-Phy enabled\n");
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+}
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+
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+/**
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+ * enable() - Enable PHY hardware
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+ * @phy: Pointer to DSI PHY hardware object.
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+ * @cfg: Per lane configurations for timing, strength and lane
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+ * configurations.
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+ */
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+void dsi_phy_hw_v4_0_enable(struct dsi_phy_hw *phy,
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+ struct dsi_phy_cfg *cfg)
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+{
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+ int rc = 0;
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+ u32 status;
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+ u32 const delay_us = 5;
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+ u32 const timeout_us = 1000;
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+
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+ if (dsi_phy_hw_v4_0_is_pll_on(phy))
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+ pr_warn("PLL turned on before configuring PHY\n");
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+
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+ /* wait for REFGEN READY */
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+ rc = readl_poll_timeout_atomic(phy->base + DSIPHY_CMN_PHY_STATUS,
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+ status, (status & BIT(0)), delay_us, timeout_us);
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+ if (rc) {
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+ DSI_PHY_ERR(phy, "Ref gen not ready. Aborting\n");
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+ return;
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+ }
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+
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+ if (cfg->phy_type == DSI_PHY_TYPE_CPHY)
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+ dsi_phy_hw_cphy_enable(phy, cfg);
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+ else /* Default PHY type is DPHY */
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+ dsi_phy_hw_dphy_enable(phy, cfg);
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+
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}
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/**
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Yuan Zhao