disp: msm: dsi: update PHY configuration to support cphy

Add support to read cphy boolean flag from panel dtsi
and configure DSI PHY registers accordingly. Update the
bit/byte clock calculation according to cphy specifications.
Update clock parents so that the relevant divider blocks
are configured to support cphy.

Change-Id: Iaca61eec01a488657b086f59910c52f8c79e26a4
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>

msm/dsi/dsi_phy_hw.h

@@ -100,6 +100,7 @@ struct dsi_phy_per_lane_cfgs {
  * @pll_source:       PLL source.
  * @lane_map:         DSI logical to PHY lane mapping.
  * @force_clk_lane_hs:Boolean whether to force clock lane in HS mode.
+ * @phy_type:         Phy-type (Dphy/Cphy).
  * @bit_clk_rate_hz: DSI bit clk rate in HZ.
  */
 struct dsi_phy_cfg {
@@ -111,6 +112,7 @@ struct dsi_phy_cfg {
 	enum dsi_phy_pll_source pll_source;
 	struct dsi_lane_map lane_map;
 	bool force_clk_lane_hs;
+	enum dsi_phy_type phy_type;
 	unsigned long bit_clk_rate_hz;
 };