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disp: msm: dsi: update PHY configuration to support cphy

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Add support to read cphy boolean flag from panel dtsi
and configure DSI PHY registers accordingly. Update the
bit/byte clock calculation according to cphy specifications.
Update clock parents so that the relevant divider blocks
are configured to support cphy.

Change-Id: Iaca61eec01a488657b086f59910c52f8c79e26a4
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
This commit is contained in:
Yuan Zhao
2020-05-07 00:34:24 +08:00
committed by Gerrit - the friendly Code Review server
parent 43069ad44a
commit 5139cad2d4
9 changed files with 240 additions and 35 deletions
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2
msm/dsi/dsi_defs.h
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@@ -469,6 +469,7 @@ struct dsi_split_link_config {
* true.
* @ext_bridge_mode: External bridge is connected.
* @force_hs_clk_lane: Send continuous clock to the panel.
* @phy_type: DPHY/CPHY is enabled for this panel.
* @dsi_split_link_config: Split Link Configuration.
* @byte_intf_clk_div: Determines the factor for calculating byte intf clock.
*/
@@ -493,6 +494,7 @@ struct dsi_host_common_cfg {
bool append_tx_eot;
bool ext_bridge_mode;
bool force_hs_clk_lane;
enum dsi_phy_type phy_type;
struct dsi_split_link_config split_link;
u32 byte_intf_clk_div;
};