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@@ -444,17 +444,29 @@ static int cam_top_tpg_start(void *hw_priv, void *start_args,
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tpg_reg->tpg_num_dts_shift_val) | tpg_data->vc_num;
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tpg_reg->tpg_num_dts_shift_val) | tpg_data->vc_num;
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cam_io_w_mb(val, soc_info->reg_map[0].mem_base + tpg_reg->tpg_vc_cfg0);
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cam_io_w_mb(val, soc_info->reg_map[0].mem_base + tpg_reg->tpg_vc_cfg0);
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- /* HBlank count 500 and V blank count is 600 */
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- cam_io_w_mb(0x2581F4,
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+ /*
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+ * if hblank is notset configureHBlank count 500 and
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+ * V blank count is 600
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+ */
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+
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+ if (tpg_data->h_blank_count)
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+ cam_io_w_mb(tpg_data->h_blank_count,
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+ soc_info->reg_map[0].mem_base + tpg_reg->tpg_vc_cfg1);
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+ else
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+ cam_io_w_mb(0x2581F4,
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soc_info->reg_map[0].mem_base + tpg_reg->tpg_vc_cfg1);
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soc_info->reg_map[0].mem_base + tpg_reg->tpg_vc_cfg1);
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val = (1 << tpg_reg->tpg_split_en_shift);
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val = (1 << tpg_reg->tpg_split_en_shift);
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cam_io_w_mb(tpg_data->pix_pattern, soc_info->reg_map[0].mem_base +
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cam_io_w_mb(tpg_data->pix_pattern, soc_info->reg_map[0].mem_base +
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tpg_reg->tpg_common_gen_cfg);
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tpg_reg->tpg_common_gen_cfg);
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- cam_io_w_mb(0xAFFF,
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- soc_info->reg_map[0].mem_base + tpg_reg->tpg_vbi_cfg);
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- CAM_DBG(CAM_ISP, "TPG:%d set TPG VBI to 0xAFFF",
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- tpg_hw->hw_intf->hw_idx);
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+
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+ /* if VBI is notset configureVBI to 0xAFF */
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+ if (tpg_data->v_blank_count)
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+ cam_io_w_mb(tpg_data->v_blank_count,
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+ soc_info->reg_map[0].mem_base + tpg_reg->tpg_vbi_cfg);
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+ else
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+ cam_io_w_mb(0xAFFF,
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+ soc_info->reg_map[0].mem_base + tpg_reg->tpg_vbi_cfg);
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/* Set the TOP tpg mux sel*/
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/* Set the TOP tpg mux sel*/
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cam_io_w_mb((1 << tpg_hw->hw_intf->hw_idx),
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cam_io_w_mb((1 << tpg_hw->hw_intf->hw_idx),
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