qcacmn: Do not subscribe for MC/BC frames for kiwi/peach
MC/BC frames are routed to FW ring based on routing config for MC/BC data as SRC: FW2RXDMA and DST: RXDMA2DFW. Data offload features in FW will take care of routing the MC/BC frames to FW in both active and low power modes. Make this change only for kiwi/peach using hal ops. Change-Id: Id8665261a512c9db3e808f95082ff82b47f01ade CRs-Fixed: 3464036
This commit is contained in:

committed by
Madan Koyyalamudi

parent
bbd8a57b8e
commit
50c9ab56a1
@@ -1429,8 +1429,10 @@ dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
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htt_tlv_filter.fp_mgmt_filter = 0;
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htt_tlv_filter.fp_mgmt_filter = 0;
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htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
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htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
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htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
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htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
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FILTER_DATA_MCAST |
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FILTER_DATA_DATA);
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FILTER_DATA_DATA);
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htt_tlv_filter.fp_data_filter |=
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hal_rx_en_mcast_fp_data_filter(soc->hal_soc) ?
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FILTER_DATA_MCAST : 0;
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htt_tlv_filter.mo_mgmt_filter = 0;
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htt_tlv_filter.mo_mgmt_filter = 0;
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htt_tlv_filter.mo_ctrl_filter = 0;
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htt_tlv_filter.mo_ctrl_filter = 0;
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htt_tlv_filter.mo_data_filter = 0;
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htt_tlv_filter.mo_data_filter = 0;
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@@ -1533,8 +1535,10 @@ dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
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htt_tlv_filter.fp_mgmt_filter = 0;
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htt_tlv_filter.fp_mgmt_filter = 0;
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htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
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htt_tlv_filter.fp_ctrl_filter = FILTER_CTRL_BA_REQ;
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htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
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htt_tlv_filter.fp_data_filter = (FILTER_DATA_UCAST |
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FILTER_DATA_MCAST |
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FILTER_DATA_DATA);
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FILTER_DATA_DATA);
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htt_tlv_filter.fp_data_filter |=
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hal_rx_en_mcast_fp_data_filter(soc->hal_soc) ?
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FILTER_DATA_MCAST : 0;
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htt_tlv_filter.mo_mgmt_filter = 0;
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htt_tlv_filter.mo_mgmt_filter = 0;
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htt_tlv_filter.mo_ctrl_filter = 0;
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htt_tlv_filter.mo_ctrl_filter = 0;
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htt_tlv_filter.mo_data_filter = 0;
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htt_tlv_filter.mo_data_filter = 0;
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@@ -453,6 +453,17 @@ void hal_rx_buf_cookie_rbm_get_be(uint32_t *buf_addr_info_hdl,
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(hal_ring_desc_t)buf_addr_info);
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(hal_ring_desc_t)buf_addr_info);
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}
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}
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/**
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* hal_rx_en_mcast_fp_data_filter_generic_be() - Is mcast filter pass enabled
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*
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* Return: true default for BE WIN
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*/
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static inline
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bool hal_rx_en_mcast_fp_data_filter_generic_be(void)
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{
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return true;
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}
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/**
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/**
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* hal_rxdma_buff_addr_info_set_be() - set the buffer_addr_info of the
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* hal_rxdma_buff_addr_info_set_be() - set the buffer_addr_info of the
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* rxdma ring entry.
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* rxdma ring entry.
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@@ -973,4 +984,6 @@ void hal_hw_txrx_default_ops_attach_be(struct hal_soc *hal_soc)
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hal_set_reo_ent_desc_reo_dest_ind_be;
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hal_set_reo_ent_desc_reo_dest_ind_be;
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hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr =
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hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr =
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hal_get_reo_ent_desc_qdesc_addr_be;
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hal_get_reo_ent_desc_qdesc_addr_be;
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hal_soc->ops->hal_rx_en_mcast_fp_data_filter =
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hal_rx_en_mcast_fp_data_filter_generic_be;
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}
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}
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@@ -1455,6 +1455,7 @@ struct hal_hw_txrx_ops {
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uint32_t (*hal_tx_get_num_ppe_vp_search_idx_tbl_entries)(
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uint32_t (*hal_tx_get_num_ppe_vp_search_idx_tbl_entries)(
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hal_soc_handle_t hal_soc_hdl);
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hal_soc_handle_t hal_soc_hdl);
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uint32_t (*hal_tx_ring_halt_get)(hal_soc_handle_t hal_soc_hdl);
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uint32_t (*hal_tx_ring_halt_get)(hal_soc_handle_t hal_soc_hdl);
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bool (*hal_rx_en_mcast_fp_data_filter)(void);
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};
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};
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/**
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/**
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@@ -3126,4 +3126,18 @@ hal_get_tsf_time(hal_soc_handle_t hal_soc_hdl, uint32_t tsf_id,
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hal_soc->ops->hal_get_tsf_time(hal_soc_hdl, tsf_id, mac_id,
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hal_soc->ops->hal_get_tsf_time(hal_soc_hdl, tsf_id, mac_id,
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tsf, tsf_sync_soc_time);
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tsf, tsf_sync_soc_time);
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}
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}
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/**
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* hal_rx_en_mcast_fp_data_filter() - Is mcast filter pass enabled
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* @hal_soc_hdl: HAL soc handle
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*
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* Return: false for BE MCC, true for WIN
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*/
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static inline
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bool hal_rx_en_mcast_fp_data_filter(hal_soc_handle_t hal_soc_hdl)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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return hal_soc->ops->hal_rx_en_mcast_fp_data_filter();
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}
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#endif /* _HAL_RX_H */
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#endif /* _HAL_RX_H */
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@@ -2012,6 +2012,17 @@ static QDF_STATUS hal_rx_reo_ent_get_src_link_id_kiwi(hal_rxdma_desc_t rx_desc,
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return QDF_STATUS_SUCCESS;
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return QDF_STATUS_SUCCESS;
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}
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}
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/**
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* hal_rx_en_mcast_fp_data_filter_kiwi() - Is mcast filter pass enabled
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*
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* Return: false for BE MCC
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*/
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static inline
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bool hal_rx_en_mcast_fp_data_filter_kiwi(void)
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{
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return false;
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}
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#ifdef QCA_WIFI_KIWI_V2
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#ifdef QCA_WIFI_KIWI_V2
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/**
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/**
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* hal_srng_dst_hw_init_misc_1_kiwi() - Function to initialize MISC_1 register
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* hal_srng_dst_hw_init_misc_1_kiwi() - Function to initialize MISC_1 register
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@@ -2343,6 +2354,8 @@ static void hal_hw_txrx_ops_attach_kiwi(struct hal_soc *hal_soc)
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#ifdef FEATURE_DIRECT_LINK
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#ifdef FEATURE_DIRECT_LINK
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hal_soc->ops->hal_srng_set_msi_config = hal_srng_set_msi_config;
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hal_soc->ops->hal_srng_set_msi_config = hal_srng_set_msi_config;
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#endif
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#endif
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hal_soc->ops->hal_rx_en_mcast_fp_data_filter =
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hal_rx_en_mcast_fp_data_filter_kiwi;
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};
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};
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struct hal_hw_srng_config hw_srng_table_kiwi[] = {
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struct hal_hw_srng_config hw_srng_table_kiwi[] = {
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