disp: msm: sde: convert system cache boolean to feature bit

Currently a boolean variable is used to track if the system
cache feature is enable for a particular SCID.

This change converts it to use a feature bit instead.

Change-Id: I8461fd9fb837b871c4ac5c67a9ab7613aadea7bb
Signed-off-by: Amine Najahi <[email protected]>

msm/sde/sde_core_perf.c

@@ -383,13 +383,12 @@ static void _sde_core_perf_crtc_set_llcc_cache_type(struct sde_kms *kms,
 {
 	struct drm_crtc *tmp_crtc;
 	struct sde_crtc *sde_crtc;
-	struct sde_sc_cfg *sc_cfg = kms->perf.catalog->sc_cfg;
 	struct sde_core_perf_params *cur_perf;
 	enum sde_crtc_client_type curr_client_type
 					= sde_crtc_get_client_type(crtc);
 	u32 llcc_active = 0;
 
-	if (!sc_cfg[type].has_sys_cache) {
+	if (!test_bit(type, kms->perf.catalog->sde_sys_cache_type_map)) {
 		SDE_DEBUG("System Cache %d is not enabled!. Won't use\n",
 				type);
 		return;

msm/sde/sde_crtc.c

@@ -6248,7 +6248,7 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc,
 			ARRAY_SIZE(e_secure_level), 0,
 			CRTC_PROP_SECURITY_LEVEL);
 
-	if (catalog->sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache)
+	if (test_bit(SDE_SYS_CACHE_DISP, catalog->sde_sys_cache_type_map))
 		msm_property_install_enum(&sde_crtc->property_info, "cache_state",
 			0x0, 0, e_cache_state,
 			ARRAY_SIZE(e_cache_state), 0,
@@ -7387,7 +7387,7 @@ void sde_crtc_static_img_control(struct drm_crtc *crtc,
 		return;
 	}
 
-	if (!sde_kms->catalog->sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache) {
+	if (!test_bit(SDE_SYS_CACHE_DISP, sde_kms->catalog->sde_sys_cache_type_map)) {
 		SDE_DEBUG("DISP syscache not supported\n");
 		return;
 	}

msm/sde/sde_encoder_phys_wb.c

@@ -1093,8 +1093,8 @@ static void _sde_encoder_phys_wb_setup_cache(struct sde_encoder_phys *phys_enc,
 	cache_type = phys_enc->in_clone_mode ? SDE_SYS_CACHE_DISP : SDE_SYS_CACHE_DISP_WB;
 
 	sc_cfg = &hw_wb->catalog->sc_cfg[cache_type];
-	if (!sc_cfg->has_sys_cache) {
-		SDE_DEBUG("sys cache feature not enabled\n");
+	if (!test_bit(cache_type, hw_wb->catalog->sde_sys_cache_type_map)) {
+		SDE_DEBUG("sys cache type %d not enabled\n", cache_type);
 		return;
 	}
 

msm/sde/sde_hw_catalog.c

@@ -1847,7 +1847,7 @@ static void sde_sspp_set_features(struct sde_mdss_cfg *sde_cfg,
 				set_bit(SDE_PERF_SSPP_UIDLE_FILL_LVL_SCALE, &sspp->perf_features);
 		}
 
-		if (sde_cfg->sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache)
+		if (test_bit(SDE_SYS_CACHE_DISP, sde_cfg->sde_sys_cache_type_map))
 			set_bit(SDE_PERF_SSPP_SYS_CACHE, &sspp->perf_features);
 
 		if (test_bit(SDE_FEATURE_MULTIRECT_ERROR, sde_cfg->features))
@@ -3512,12 +3512,12 @@ static int sde_cache_parse_dt(struct device_node *np,
 		struct sde_sc_cfg *sc_cfg = &sde_cfg->sc_cfg[i];
 		u32 usecase_id = 0;
 
-		if (!sc_cfg->has_sys_cache)
+		if (!test_bit(i, sde_cfg->sde_sys_cache_type_map))
 			continue;
 
 		usecase_id = sde_sys_cache_usecase_id[i];
 		if (!usecase_id) {
-			sc_cfg->has_sys_cache = false;
+			clear_bit(i, sde_cfg->sde_sys_cache_type_map);
 			SDE_DEBUG("invalid usecase-id for sys cache:%d\n", i);
 			continue;
 		}
@@ -5010,7 +5010,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
 		set_bit(SDE_FEATURE_DITHER_LUMA_MODE, sde_cfg->features);
 		sde_cfg->mdss_hw_block_size = 0x158;
 		set_bit(SDE_FEATURE_TRUSTED_VM, sde_cfg->features);
-		sde_cfg->sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache = true;
+		set_bit(SDE_SYS_CACHE_DISP, sde_cfg->sde_sys_cache_type_map);
 	} else if (IS_HOLI_TARGET(hw_rev)) {
 		set_bit(SDE_FEATURE_QSYNC, sde_cfg->features);
 		sde_cfg->perf.min_prefill_lines = 24;
@@ -5040,7 +5040,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
 		set_bit(SDE_FEATURE_VBIF_DISABLE_SHAREABLE, sde_cfg->features);
 		sde_cfg->mdss_hw_block_size = 0x158;
 		set_bit(SDE_FEATURE_TRUSTED_VM, sde_cfg->features);
-		sde_cfg->sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache = true;
+		set_bit(SDE_SYS_CACHE_DISP, sde_cfg->sde_sys_cache_type_map);
 	} else if (IS_WAIPIO_TARGET(hw_rev) || IS_CAPE_TARGET(hw_rev)) {
 		sde_cfg->allowed_dsc_reservation_switch = SDE_DP_DSC_RESERVATION_SWITCH;
 		set_bit(SDE_FEATURE_DEDICATED_CWB, sde_cfg->features);
@@ -5062,7 +5062,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
 		set_bit(SDE_FEATURE_VBIF_DISABLE_SHAREABLE, sde_cfg->features);
 		set_bit(SDE_FEATURE_DITHER_LUMA_MODE, sde_cfg->features);
 		sde_cfg->mdss_hw_block_size = 0x158;
-		sde_cfg->sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache = true;
+		set_bit(SDE_SYS_CACHE_DISP, sde_cfg->sde_sys_cache_type_map);
 		set_bit(SDE_FEATURE_MULTIRECT_ERROR, sde_cfg->features);
 		set_bit(SDE_FEATURE_FP16, sde_cfg->features);
 		set_bit(SDE_MDP_PERIPH_TOP_0_REMOVED, &sde_cfg->mdp[0].features);
@@ -5113,7 +5113,7 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
 		set_bit(SDE_FEATURE_VBIF_DISABLE_SHAREABLE, sde_cfg->features);
 		set_bit(SDE_FEATURE_DITHER_LUMA_MODE, sde_cfg->features);
 		sde_cfg->mdss_hw_block_size = 0x158;
-		sde_cfg->sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache = true;
+		set_bit(SDE_SYS_CACHE_DISP, sde_cfg->sde_sys_cache_type_map);
 		set_bit(SDE_FEATURE_MULTIRECT_ERROR, sde_cfg->features);
 		set_bit(SDE_FEATURE_FP16, sde_cfg->features);
 		set_bit(SDE_MDP_PERIPH_TOP_0_REMOVED, &sde_cfg->mdp[0].features);
@@ -5147,8 +5147,8 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
 		set_bit(SDE_FEATURE_VBIF_CLK_SPLIT, sde_cfg->features);
 		set_bit(SDE_FEATURE_CTL_DONE, sde_cfg->features);
 		set_bit(SDE_FEATURE_TRUSTED_VM, sde_cfg->features);
-		sde_cfg->sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache = true;
-		sde_cfg->sc_cfg[SDE_SYS_CACHE_DISP_WB].has_sys_cache = true;
+		set_bit(SDE_SYS_CACHE_DISP, sde_cfg->sde_sys_cache_type_map);
+		set_bit(SDE_SYS_CACHE_DISP_WB, sde_cfg->sde_sys_cache_type_map);
 		sde_cfg->allowed_dsc_reservation_switch = SDE_DP_DSC_RESERVATION_SWITCH;
 		sde_cfg->autorefresh_disable_seq = AUTOREFRESH_DISABLE_SEQ2;
 		sde_cfg->perf.min_prefill_lines = 40;

msm/sde/sde_hw_catalog.h

@@ -710,7 +710,6 @@ enum {
  * @SDE_FEATURE_INLINE_SKIP_THRESHOLD      Skip inline rotation threshold
  * @SDE_FEATURE_DITHER_LUMA_MODE           Dither LUMA mode supported
  * @SDE_FEATURE_RC_LM_FLUSH_OVERRIDE       RC LM flush override supported
- * @SDE_FEATURE_SYSCACHE       System cache supported
  * @SDE_FEATURE_SUI_MISR       SecureUI MISR supported
  * @SDE_FEATURE_SUI_BLENDSTAGE SecureUI Blendstage supported
  * @SDE_FEATURE_SUI_NS_ALLOWED SecureUI allowed to access non-secure context banks
@@ -750,7 +749,6 @@ enum sde_mdss_features {
 	SDE_FEATURE_INLINE_SKIP_THRESHOLD,
 	SDE_FEATURE_DITHER_LUMA_MODE,
 	SDE_FEATURE_RC_LM_FLUSH_OVERRIDE,
-	SDE_FEATURE_SYSCACHE,
 	SDE_FEATURE_SUI_MISR,
 	SDE_FEATURE_SUI_BLENDSTAGE,
 	SDE_FEATURE_SUI_NS_ALLOWED,
@@ -1639,13 +1637,11 @@ struct sde_perf_cdp_cfg {
 
 /**
  * struct sde_sc_cfg - define system cache configuration
- * @has_sys_cache: true if system cache is enabled
  * @llcc_uuid: llcc use case id for the system cache
  * @llcc_scid: scid for the system cache
  * @llcc_slice_size: slice size of the system cache
  */
 struct sde_sc_cfg {
-	bool has_sys_cache;
 	int llcc_uid;
 	int llcc_scid;
 	size_t llcc_slice_size;
@@ -1943,6 +1939,7 @@ struct sde_mdss_cfg {
 	u32 allowed_dsc_reservation_switch;
 	enum autorefresh_disable_sequence autorefresh_disable_seq;
 	struct sde_sc_cfg sc_cfg[SDE_SYS_CACHE_MAX];
+	DECLARE_BITMAP(sde_sys_cache_type_map, SDE_SYS_CACHE_MAX);
 	struct sde_perf_cfg perf;
 	struct sde_uidle_cfg uidle_cfg;
 	struct list_head irq_offset_list;

msm/sde/sde_plane.c

@@ -2861,7 +2861,7 @@ static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde,
 	cfg->flags = SYS_CACHE_EN_FLAG | SYS_CACHE_SCID;
 	cfg->type = SDE_SYS_CACHE_NONE;
 
-	if ((sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache)
+	if ((test_bit(SDE_SYS_CACHE_DISP, psde->catalog->sde_sys_cache_type_map))
 			&& ((pstate->static_cache_state == CACHE_STATE_FRAME_WRITE)
 				|| (pstate->static_cache_state == CACHE_STATE_FRAME_READ))) {
 		cfg->rd_en = true;
@@ -2870,7 +2870,8 @@ static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde,
 		cfg->flags |= SYS_CACHE_NO_ALLOC;
 		cfg->type = SDE_SYS_CACHE_DISP;
 
-	} else if ((sc_cfg[fb_cache_type].has_sys_cache) && fb_cache_flag) {
+	} else if (test_bit(fb_cache_type, psde->catalog->sde_sys_cache_type_map)
+			&& fb_cache_flag) {
 		cfg->rd_en = true;
 		cfg->rd_scid = sc_cfg[fb_cache_type].llcc_scid;
 		cfg->rd_noallocate = true;

msm/sde/sde_wb.c

@@ -625,8 +625,8 @@ int sde_wb_connector_post_init(struct drm_connector *connector, void *display)
 	wb_dev->connector = connector;
 	wb_dev->detect_status = connector_status_connected;
 
-	if (catalog->sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache
-			|| catalog->sc_cfg[SDE_SYS_CACHE_DISP_WB].has_sys_cache)
+	if (test_bit(SDE_SYS_CACHE_DISP, catalog->sde_sys_cache_type_map)
+			|| test_bit(SDE_SYS_CACHE_DISP_WB, catalog->sde_sys_cache_type_map))
 		msm_property_install_enum(&c_conn->property_info, "cache_state",
 			0x0, 0, e_cache_state, ARRAY_SIZE(e_cache_state),
 			0, CONNECTOR_PROP_CACHE_STATE);