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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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- * Copyright (c) 2019, The Linux Foundation. All rights reserved.
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+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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*/
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#include <linux/slab.h>
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@@ -52,6 +52,8 @@ struct cam_vfe_mux_camif_ver3_data {
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uint32_t camif_debug;
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uint32_t horizontal_bin;
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uint32_t qcfa_bin;
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+ uint32_t dual_hw_idx;
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+ uint32_t is_dual;
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};
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static int cam_vfe_camif_ver3_get_evt_payload(
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@@ -258,6 +260,10 @@ int cam_vfe_camif_ver3_acquire_resource(
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camif_data->qcfa_bin = acquire_data->vfe_in.in_port->qcfa_bin;
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camif_data->event_cb = acquire_data->event_cb;
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camif_data->priv = acquire_data->priv;
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+ camif_data->is_dual = acquire_data->vfe_in.is_dual;
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+
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+ if (acquire_data->vfe_in.is_dual)
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+ camif_data->dual_hw_idx = acquire_data->vfe_in.dual_hw_idx;
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CAM_DBG(CAM_ISP, "VFE:%d CAMIF pix_pattern:%d dsp_mode=%d",
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camif_res->hw_intf->hw_idx,
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@@ -387,10 +393,16 @@ static int cam_vfe_camif_ver3_resource_start(
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if ((rsrc_data->dsp_mode >= CAM_ISP_DSP_MODE_ONE_WAY) &&
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(rsrc_data->dsp_mode <= CAM_ISP_DSP_MODE_ROUND)) {
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/* DSP mode reg val is CAM_ISP_DSP_MODE - 1 */
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- val |= (((rsrc_data->dsp_mode - 1) &
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- rsrc_data->reg_data->dsp_mode_mask) <<
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- rsrc_data->reg_data->dsp_mode_shift);
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- val |= (0x1 << rsrc_data->reg_data->dsp_en_shift);
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+ if (camif_res->hw_intf->hw_idx != CAM_ISP_HW_VFE_CORE_2) {
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+ val |= (((rsrc_data->dsp_mode - 1) &
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+ rsrc_data->reg_data->dsp_mode_mask) <<
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+ rsrc_data->reg_data->dsp_mode_shift);
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+ val |= (0x1 << rsrc_data->reg_data->dsp_en_shift);
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+ } else {
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+ CAM_ERR(CAM_ISP, "Error, HVX not available for IFE_%d",
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+ camif_res->hw_intf->hw_idx);
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+ return -EINVAL;
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+ }
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}
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if (rsrc_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE)
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@@ -419,6 +431,12 @@ static int cam_vfe_camif_ver3_resource_start(
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val |= (rsrc_data->cam_common_cfg.input_mux_sel_pp & 0x3) <<
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CAM_SHIFT_TOP_CORE_CFG_INPUTMUX_PP;
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+ if (rsrc_data->is_dual && rsrc_data->reg_data->dual_vfe_sync_mask) {
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+ val |= (((rsrc_data->dual_hw_idx &
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+ rsrc_data->reg_data->dual_vfe_sync_mask) + 1) <<
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+ rsrc_data->reg_data->dual_ife_sync_sel_shift);
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+ }
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+
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cam_io_w_mb(val, rsrc_data->mem_base +
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rsrc_data->common_reg->core_cfg_0);
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