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msm: camera: isp: Improvements to logging in VFE and CSID

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This commit fixes minor issues in logging in VFE and CSID drivers along
with major fixes and improvements -- issue CSID global reset after
fatal error, extending debug register parsing for IFE Lite, fix clipping
of text due to limited buffer size in RX error log printing.

CRs-Fixed: 2977145
Change-Id: I4eacfc60264911b0597ece7693877fc1fb6976eb
Signed-off-by: Anand Ravi <ananravi@codeaurora.org>
This commit is contained in:
Anand Ravi
2021-07-19 12:28:23 -07:00
parent 13670c580a
commit 4f0c968cf1
12 changed files with 601 additions and 735 deletions
Download Patch File Download Diff File Expand all files Collapse all files

41
drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c
View File

@@ -3059,6 +3059,7 @@ static int cam_ife_hw_mgr_acquire_csid_hw(
struct cam_isp_out_port_generic_info *out_port = NULL; struct cam_isp_out_port_generic_info *out_port = NULL;
struct cam_ife_csid_hw_caps *csid_caps = NULL; struct cam_ife_csid_hw_caps *csid_caps = NULL;
bool can_use_lite = false; bool can_use_lite = false;
int busy_count = 0, compat_count = 0;
if (!ife_ctx || !csid_acquire) { if (!ife_ctx || !csid_acquire) {
CAM_ERR(CAM_ISP, CAM_ERR(CAM_ISP,
@@ -3124,10 +3125,9 @@ static int cam_ife_hw_mgr_acquire_csid_hw(
} }
} }
if (is_start_lower_idx) for (i = (is_start_lower_idx) ? 0 : (CAM_IFE_CSID_HW_NUM_MAX - 1);
goto start_acquire_lower_idx; (is_start_lower_idx) ? (i < CAM_IFE_CSID_HW_NUM_MAX) : (i >= 0);
(is_start_lower_idx) ? i++ : i--) {
for (i = CAM_IFE_CSID_HW_NUM_MAX - 1; i >= 0; i--) {
if (!ife_hw_mgr->csid_devices[i]) if (!ife_hw_mgr->csid_devices[i])
continue; continue;
hw_intf = ife_hw_mgr->csid_devices[i]; hw_intf = ife_hw_mgr->csid_devices[i];
@@ -3139,30 +3139,7 @@ static int cam_ife_hw_mgr_acquire_csid_hw(
continue; continue;
} }
rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, compat_count++;
csid_acquire,
sizeof(struct
cam_csid_hw_reserve_resource_args));
if (!rc)
return rc;
}
return rc;
start_acquire_lower_idx:
for (i = 0; i < CAM_IFE_CSID_HW_NUM_MAX; i++) {
if (!ife_hw_mgr->csid_devices[i])
continue;
hw_intf = ife_hw_mgr->csid_devices[i];
if (ife_hw_mgr->csid_hw_caps[hw_intf->hw_idx].is_lite &&
!can_use_lite) {
CAM_DBG(CAM_ISP, "CSID[%u] cannot use lite",
hw_intf->hw_idx);
continue;
}
rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv, rc = hw_intf->hw_ops.reserve(hw_intf->hw_priv,
csid_acquire, csid_acquire,
@@ -3170,8 +3147,16 @@ start_acquire_lower_idx:
cam_csid_hw_reserve_resource_args)); cam_csid_hw_reserve_resource_args));
if (!rc) if (!rc)
return rc; return rc;
if (rc == -EBUSY)
busy_count++;
else
CAM_ERR(CAM_ISP, "CSID[%d] acquire failed (rc=%d)", i, rc);
} }
if (compat_count == busy_count)
CAM_ERR(CAM_ISP, "all compatible CSIDs are busy");
acquire_successful: acquire_successful:
return rc; return rc;
} }

9
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.c
View File

@@ -591,6 +591,15 @@ int cam_ife_csid_convert_res_to_irq_reg(uint32_t res_id)
} }
} }
const char *cam_ife_csid_reset_type_to_string(enum cam_ife_csid_reset_type reset_type)
{
switch (reset_type) {
case CAM_IFE_CSID_RESET_GLOBAL: return "global";
case CAM_IFE_CSID_RESET_PATH: return "path";
default: return "invalid";
}
}
int cam_ife_csid_get_base(struct cam_hw_soc_info *soc_info, int cam_ife_csid_get_base(struct cam_hw_soc_info *soc_info,
uint32_t base_id, void *cmd_args, size_t arg_size) uint32_t base_id, void *cmd_args, size_t arg_size)
{ {

2
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.h
View File

@@ -383,5 +383,7 @@ int cam_ife_csid_convert_res_to_irq_reg(uint32_t res_id);
int cam_ife_csid_get_base(struct cam_hw_soc_info *soc_info, int cam_ife_csid_get_base(struct cam_hw_soc_info *soc_info,
uint32_t base_id, void *cmd_args, size_t arg_size); uint32_t base_id, void *cmd_args, size_t arg_size);
const char *cam_ife_csid_reset_type_to_string(enum cam_ife_csid_reset_type reset_type);
const uint8_t **cam_ife_csid_get_irq_reg_tag_ptr(void); const uint8_t **cam_ife_csid_get_irq_reg_tag_ptr(void);
#endif /*_CAM_IFE_CSID_COMMON_H_ */ #endif /*_CAM_IFE_CSID_COMMON_H_ */

99
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c
View File

@@ -656,6 +656,7 @@ static int cam_ife_csid_ver2_rx_err_top_half(
struct cam_ife_csid_ver2_reg_info *csid_reg; struct cam_ife_csid_ver2_reg_info *csid_reg;
struct cam_ife_csid_ver2_evt_payload *evt_payload; struct cam_ife_csid_ver2_evt_payload *evt_payload;
const struct cam_ife_csid_csi2_rx_reg_info *csi2_reg; const struct cam_ife_csid_csi2_rx_reg_info *csi2_reg;
int discard_frame_count;
csid_hw = th_payload->handler_priv; csid_hw = th_payload->handler_priv;
if (!csid_hw) { if (!csid_hw) {
@@ -667,8 +668,12 @@ static int cam_ife_csid_ver2_rx_err_top_half(
csid_hw->core_info->csid_reg; csid_hw->core_info->csid_reg;
csi2_reg = csid_reg->csi2_reg; csi2_reg = csid_reg->csi2_reg;
if (atomic_read(&csid_hw->discard_frame_per_path)) discard_frame_count = atomic_read(&csid_hw->discard_frame_per_path);
if (discard_frame_count) {
CAM_DBG(CAM_ISP, "ignoring rx error (error:0x%x, remaining frames:%d)",
th_payload->evt_status_arr[CAM_IFE_CSID_IRQ_REG_RX], discard_frame_count);
return -ENODEV; return -ENODEV;
}
if (csid_hw->flags.fatal_err_detected) { if (csid_hw->flags.fatal_err_detected) {
CAM_INFO_RATE_LIMIT(CAM_ISP, CAM_INFO_RATE_LIMIT(CAM_ISP,
@@ -935,7 +940,7 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
uint8_t *log_buf = NULL; uint8_t *log_buf = NULL;
uint32_t irq_status; uint32_t irq_status;
uint32_t rx_irq_status = 0; uint32_t rx_irq_status = 0;
size_t len = 0; size_t len = 0, i;
uint32_t val = 0; uint32_t val = 0;
uint32_t event_type = 0; uint32_t event_type = 0;
uint32_t long_pkt_ftr_val; uint32_t long_pkt_ftr_val;
@@ -961,28 +966,22 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
csi2_reg->fatal_err_mask; csi2_reg->fatal_err_mask;
if (irq_status) { if (irq_status) {
CAM_ERR_BUF(CAM_ISP, log_buf, CAM_IFE_CSID_LOG_BUF_LEN, &len, bool lane_overflow = false;
"Fatal Errors:"); char tmp_buf[10];
int tmp_len = 0;
if (irq_status & IFE_CSID_VER2_RX_LANE0_FIFO_OVERFLOW) for (i = 0; i < 4; i++) {
CAM_ERR_BUF(CAM_ISP, log_buf, CAM_IFE_CSID_LOG_BUF_LEN, &len, /* NOTE: Hardware specific bits */
"RX_ERROR_LANE0_FIFO_OVERFLOW: Skew/Less Data on lanes/ Slow csid clock:%luHz", if (irq_status & (IFE_CSID_VER2_RX_LANE0_FIFO_OVERFLOW << i)) {
soc_info->applied_src_clk_rate); tmp_len += scnprintf(tmp_buf + tmp_len, 10 - tmp_len, " %d", i);
lane_overflow = true;
}
}
if (irq_status & IFE_CSID_VER2_RX_LANE1_FIFO_OVERFLOW) if (lane_overflow)
CAM_ERR_BUF(CAM_ISP, log_buf, CAM_IFE_CSID_LOG_BUF_LEN, &len, CAM_ERR_BUF(CAM_ISP, log_buf, CAM_IFE_CSID_LOG_BUF_LEN, &len,
"RX_ERROR_LANE1_FIFO_OVERFLOW: Skew/Less Data on lanes/ Slow csid clock:%luHz", "INPUT_FIFO_OVERFLOW [Lanes:%s]: Skew/Less Data on lanes/ Slow csid clock:%luHz",
soc_info->applied_src_clk_rate); tmp_buf, soc_info->applied_src_clk_rate);
if (irq_status & IFE_CSID_VER2_RX_LANE2_FIFO_OVERFLOW)
CAM_ERR_BUF(CAM_ISP, log_buf, CAM_IFE_CSID_LOG_BUF_LEN, &len,
"RX_ERROR_LANE2_FIFO_OVERFLOW: Skew/Less Data on lanes/ Slow csid clock:%luHz",
soc_info->applied_src_clk_rate);
if (irq_status & IFE_CSID_VER2_RX_LANE3_FIFO_OVERFLOW)
CAM_ERR_BUF(CAM_ISP, log_buf, CAM_IFE_CSID_LOG_BUF_LEN, &len,
"RX_ERROR_LANE3_FIFO_OVERFLOW: Skew/Less Data on lanes/ Slow csid clock:%luHz",
soc_info->applied_src_clk_rate);
if (irq_status & IFE_CSID_VER2_RX_ERROR_CPHY_PH_CRC) if (irq_status & IFE_CSID_VER2_RX_ERROR_CPHY_PH_CRC)
CAM_ERR_BUF(CAM_ISP, log_buf, CAM_IFE_CSID_LOG_BUF_LEN, &len, CAM_ERR_BUF(CAM_ISP, log_buf, CAM_IFE_CSID_LOG_BUF_LEN, &len,
@@ -993,7 +992,7 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
csi2_reg->captured_long_pkt_0_addr); csi2_reg->captured_long_pkt_0_addr);
CAM_ERR_BUF(CAM_ISP, log_buf, CAM_IFE_CSID_LOG_BUF_LEN, &len, CAM_ERR_BUF(CAM_ISP, log_buf, CAM_IFE_CSID_LOG_BUF_LEN, &len,
"ERROR_STREAM_UNDERFLOW: Fewer bytes rcvd than WC:%d in pkt hdr", "STREAM_UNDERFLOW: Fewer bytes rcvd than WC:%d in pkt hdr",
val & 0xFFFF); val & 0xFFFF);
} }
@@ -1004,6 +1003,8 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
cam_io_r_mb(soc_info->reg_map[0].mem_base + cam_io_r_mb(soc_info->reg_map[0].mem_base +
csi2_reg->captured_long_pkt_1_addr)); csi2_reg->captured_long_pkt_1_addr));
CAM_ERR(CAM_ISP, "Fatal Errors: %s", log_buf);
rx_irq_status |= irq_status; rx_irq_status |= irq_status;
csid_hw->flags.fatal_err_detected = true; csid_hw->flags.fatal_err_detected = true;
} }
@@ -1012,8 +1013,7 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
csi2_reg->part_fatal_err_mask; csi2_reg->part_fatal_err_mask;
if (irq_status) { if (irq_status) {
CAM_ERR_BUF(CAM_ISP, log_buf, CAM_IFE_CSID_LOG_BUF_LEN, &len, len = 0;
"Recoverable-errors:");
if (irq_status & IFE_CSID_VER2_RX_CPHY_EOT_RECEPTION) if (irq_status & IFE_CSID_VER2_RX_CPHY_EOT_RECEPTION)
CAM_ERR_BUF(CAM_ISP, log_buf, CAM_IFE_CSID_LOG_BUF_LEN, &len, CAM_ERR_BUF(CAM_ISP, log_buf, CAM_IFE_CSID_LOG_BUF_LEN, &len,
@@ -1058,6 +1058,7 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
CAM_ERR_BUF(CAM_ISP, log_buf, CAM_IFE_CSID_LOG_BUF_LEN, &len, CAM_ERR_BUF(CAM_ISP, log_buf, CAM_IFE_CSID_LOG_BUF_LEN, &len,
"UNBOUNDED_FRAME: Frame started with EOF or No EOF"); "UNBOUNDED_FRAME: Frame started with EOF or No EOF");
CAM_ERR(CAM_ISP, "Recoverable-errors: %s", log_buf);
rx_irq_status |= irq_status; rx_irq_status |= irq_status;
} }
@@ -1065,8 +1066,7 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
csi2_reg->non_fatal_err_mask; csi2_reg->non_fatal_err_mask;
if (irq_status) { if (irq_status) {
CAM_ERR_BUF(CAM_ISP, log_buf, CAM_IFE_CSID_LOG_BUF_LEN, &len, len = 0;
"Non-fatal-errors:");
if (irq_status & IFE_CSID_VER2_RX_MMAPPED_VC_DT) { if (irq_status & IFE_CSID_VER2_RX_MMAPPED_VC_DT) {
val = cam_io_r_mb(soc_info->reg_map[0].mem_base + val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
@@ -1076,13 +1076,13 @@ static int cam_ife_csid_ver2_rx_err_bottom_half(
"MMAPPED_VC_DT: VC:%d DT:%d mapped to more than 1 csid paths", "MMAPPED_VC_DT: VC:%d DT:%d mapped to more than 1 csid paths",
(val >> 22), ((val >> 16) & 0x3F)); (val >> 22), ((val >> 16) & 0x3F));
} }
CAM_ERR(CAM_ISP, "Non-fatal-errors: %s", log_buf);
} }
if (len) CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID[%u] Rx Status 0x%x",
CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID[%u] Rx Status 0x%x %s", csid_hw->hw_intf->hw_idx,
csid_hw->hw_intf->hw_idx, payload->irq_reg_val[CAM_IFE_CSID_IRQ_REG_RX]);
payload->irq_reg_val[CAM_IFE_CSID_IRQ_REG_RX],
log_buf);
if (csid_hw->flags.fatal_err_detected) { if (csid_hw->flags.fatal_err_detected) {
event_type |= CAM_ISP_HW_ERROR_CSID_FATAL; event_type |= CAM_ISP_HW_ERROR_CSID_FATAL;
@@ -1658,7 +1658,7 @@ int cam_ife_csid_ver2_get_hw_caps(void *hw_priv,
hw_caps->is_lite = soc_private->is_ife_csid_lite; hw_caps->is_lite = soc_private->is_ife_csid_lite;
CAM_DBG(CAM_ISP, CAM_DBG(CAM_ISP,
"CSID:%d No rdis:%d, no pix:%d, major:%d minor:%d ver :%d", "CSID:%d num-rdis:%d, num-pix:%d, major:%d minor:%d ver:%d",
csid_hw->hw_intf->hw_idx, hw_caps->num_rdis, csid_hw->hw_intf->hw_idx, hw_caps->num_rdis,
hw_caps->num_pix, hw_caps->major_version, hw_caps->num_pix, hw_caps->major_version,
hw_caps->minor_version, hw_caps->version_incr); hw_caps->minor_version, hw_caps->version_incr);
@@ -1679,12 +1679,12 @@ static int cam_ife_csid_ver2_wait_for_reset(
if (rem_jiffies == 0) { if (rem_jiffies == 0) {
rc = -ETIMEDOUT; rc = -ETIMEDOUT;
CAM_ERR(CAM_ISP, CAM_ERR(CAM_ISP,
"CSID[%d], mode[%d] reset time out", "CSID[%d], sync-mode[%d] reset time out",
csid_hw->hw_intf->hw_idx, csid_hw->hw_intf->hw_idx,
csid_hw->sync_mode); csid_hw->sync_mode);
} else { } else {
CAM_DBG(CAM_ISP, CAM_DBG(CAM_ISP,
"CSID[%d], mode[%d] reset success", "CSID[%d], sync-mode[%d] reset success",
csid_hw->hw_intf->hw_idx, csid_hw->hw_intf->hw_idx,
csid_hw->sync_mode); csid_hw->sync_mode);
} }
@@ -1807,20 +1807,18 @@ int cam_ife_csid_ver2_reset(void *hw_priv,
break; break;
default: default:
CAM_ERR(CAM_ISP, "CSID:Invalid reset type :%d",
reset->reset_type);
rc = -EINVAL; rc = -EINVAL;
break; break;
} }
if (rc) if (rc)
CAM_ERR(CAM_ISP, "CSID[%d] reset type :%d fail", CAM_ERR(CAM_ISP, "CSID[%d] reset type: %s failed",
csid_hw->hw_intf->hw_idx, csid_hw->hw_intf->hw_idx,
reset->reset_type); cam_ife_csid_reset_type_to_string(reset->reset_type));
else
CAM_DBG(CAM_ISP, "CSID[%d] reset type :%d", CAM_DBG(CAM_ISP, "CSID[%d] reset type: %s",
csid_hw->hw_intf->hw_idx, csid_hw->hw_intf->hw_idx,
reset->reset_type); cam_ife_csid_reset_type_to_string(reset->reset_type));
mutex_unlock(&csid_hw->hw_info->hw_mutex); mutex_unlock(&csid_hw->hw_info->hw_mutex);
return rc; return rc;
@@ -1836,7 +1834,7 @@ static int cam_ife_csid_ver2_disable_path(
if (res->res_state != CAM_ISP_RESOURCE_STATE_STREAMING) { if (res->res_state != CAM_ISP_RESOURCE_STATE_STREAMING) {
CAM_ERR(CAM_ISP, CAM_ERR(CAM_ISP,
"CSID:%d %s path res type:%d res_id:%d Invalid state%d", "CSID:%d path res type:%d res_id:%d Invalid state:%d",
csid_hw->hw_intf->hw_idx, csid_hw->hw_intf->hw_idx,
res->res_type, res->res_id, res->res_state); res->res_type, res->res_id, res->res_state);
return -EINVAL; return -EINVAL;
@@ -2171,10 +2169,14 @@ int cam_ife_csid_ver2_reserve(void *hw_priv,
res = &csid_hw->path_res[reserve->res_id]; res = &csid_hw->path_res[reserve->res_id];
if (res->res_state != CAM_ISP_RESOURCE_STATE_AVAILABLE) { if (res->res_state != CAM_ISP_RESOURCE_STATE_AVAILABLE) {
CAM_ERR(CAM_ISP, "CSID %d Res_id %d state %d", /**
* intentionally set as DBG log to since this log gets printed when hw manager
* checks if resource is available
*/
CAM_DBG(CAM_ISP, "CSID %d Res_id %d state %d",
csid_hw->hw_intf->hw_idx, reserve->res_id, csid_hw->hw_intf->hw_idx, reserve->res_id,
res->res_state); res->res_state);
return -EINVAL; return -EBUSY;
} }
rc = cam_ife_csid_ver2_in_port_validate(reserve, csid_hw); rc = cam_ife_csid_ver2_in_port_validate(reserve, csid_hw);
@@ -3072,7 +3074,7 @@ static int cam_ife_csid_ver2_enable_path(
cam_io_w_mb(val, mem_base + ctrl_addr); cam_io_w_mb(val, mem_base + ctrl_addr);
CAM_DBG(CAM_ISP, "CSID[%u] start cmd programmed for res: %s", CAM_DBG(CAM_ISP, "CSID[%u] start cmd programmed for res: %s",
csid_hw->hw_intf->hw_idx, res->res_id); csid_hw->hw_intf->hw_idx, res->res_name);
end: end:
/* Change state even if we don't configure start cmd */ /* Change state even if we don't configure start cmd */
res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING;
@@ -3966,11 +3968,12 @@ int cam_ife_csid_ver2_stop(void *hw_priv,
cam_ife_csid_ver2_disable_csi2(csid_hw); cam_ife_csid_ver2_disable_csi2(csid_hw);
mutex_unlock(&csid_hw->hw_info->hw_mutex); mutex_unlock(&csid_hw->hw_info->hw_mutex);
reset.reset_type = CAM_IFE_CSID_RESET_PATH; reset.reset_type = (csid_hw->flags.fatal_err_detected) ? CAM_IFE_CSID_RESET_GLOBAL :
CAM_IFE_CSID_RESET_PATH;
cam_ife_csid_ver2_reset(hw_priv, &reset, cam_ife_csid_ver2_reset(hw_priv, &reset,
sizeof(struct cam_csid_reset_cfg_args)); sizeof(struct cam_csid_reset_cfg_args));
csid_hw->flags.device_enabled = false;
csid_hw->flags.device_enabled = false;
return rc; return rc;
} }

2
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe480.h
View File

@@ -25,7 +25,7 @@ static struct cam_irq_register_set vfe480_top_irq_reg_set[3] = {
.clear_reg_offset = 0x0000004C, .clear_reg_offset = 0x0000004C,
.status_reg_offset = 0x00000058, .status_reg_offset = 0x00000058,
}, },
{ {
.mask_reg_offset = 0x00000044, .mask_reg_offset = 0x00000044,
.clear_reg_offset = 0x00000050, .clear_reg_offset = 0x00000050,
.status_reg_offset = 0x0000005C, .status_reg_offset = 0x0000005C,

178
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe680.h
View File

@@ -11,6 +11,7 @@
#include "cam_irq_controller.h" #include "cam_irq_controller.h"
#define CAM_VFE_BUS_VER3_680_MAX_CLIENTS 28 #define CAM_VFE_BUS_VER3_680_MAX_CLIENTS 28
#define CAM_VFE_680_NUM_DBG_REG 17
static struct cam_vfe_top_ver4_module_desc vfe680_ipp_mod_desc[] = { static struct cam_vfe_top_ver4_module_desc vfe680_ipp_mod_desc[] = {
{ {
@@ -445,7 +446,7 @@ static struct cam_vfe_top_ver4_pdaf_violation_desc vfe680_pdaf_violation_desc[]
}, },
}; };
static struct cam_irq_register_set vfe680_top_irq_reg_set[3] = { static struct cam_irq_register_set vfe680_top_irq_reg_set[2] = {
{ {
.mask_reg_offset = 0x00000034, .mask_reg_offset = 0x00000034,
.clear_reg_offset = 0x0000003c, .clear_reg_offset = 0x0000003c,
@@ -502,7 +503,7 @@ static struct cam_vfe_top_ver4_reg_offset_common vfe680_top_common_reg = {
.bus_violation_status = 0x00000C64, .bus_violation_status = 0x00000C64,
.bus_overflow_status = 0x00000C68, .bus_overflow_status = 0x00000C68,
.top_debug_cfg = 0x000000FC, .top_debug_cfg = 0x000000FC,
.num_top_debug_reg = 17, .num_top_debug_reg = CAM_VFE_680_NUM_DBG_REG,
.top_debug = { .top_debug = {
0x000000A0, 0x000000A0,
0x000000A4, 0x000000A4,
@@ -584,6 +585,178 @@ struct cam_vfe_ver4_path_hw_info
}, },
}; };
static struct cam_vfe_top_ver4_debug_reg_info vfe680_dbg_reg_info[CAM_VFE_680_NUM_DBG_REG][8] = {
VFE_DBG_INFO_ARRAY_4bit("test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved"
),
VFE_DBG_INFO_ARRAY_4bit(
"STATS_IHIST",
"STATS_RS",
"STATS_BAF",
"GTM_BHIST",
"TINTLESS_BG",
"STATS_BFW",
"STATS_BG",
"STATS_BHIST"
),
VFE_DBG_INFO_ARRAY_4bit(
"STATS_BE",
"R2PD_DS16_C_VID",
"R2PD_DS16_Y_VID",
"crop_rnd_clamp_post_downscale_C_DS16_VID",
"4to1_C_DS16_VID",
"crop_rnd_clamp_post_downscale_Y_DS16_VID",
"4to1_Y_DS16_VID",
"crop_rnd_clamp_post_dsx_C_VID"
),
VFE_DBG_INFO_ARRAY_4bit(
"R2PD_DS4_VID_C",
"R2PD_DS4_VID_Y",
"DSX_C",
"crop_rnd_clamp_post_dsx_Y_VID",
"DSX_Y",
"crop_rnd_clamp_post_downscale_mn_C_VID",
"downscale_mn_C_VID",
"crop_rnd_clamp_post_downscale_mn_Y_VID"
),
VFE_DBG_INFO_ARRAY_4bit(
"MNDS_Y_VID",
"R2PD_DS16_C_DISP",
"R2PD_DS16_Y_DISP",
"crop_rnd_clamp_post_downscale_C_DS16_DISP",
"4to1_C_DS16_DISP",
"crop_rnd_clamp_post_downscale_Y_DS16_DISP",
"4to1_Y_DS16_DISP",
"R2PD_DS4_C_DISP"
),
VFE_DBG_INFO_ARRAY_4bit(
"R2PD_DS4_Y_DISP",
"crop_rnd_clamp_post_downscale_C_DS4_DISP",
"4to1_C_DS4_DISP",
"crop_rnd_clamp_post_downscale_Y_DS4_DISP",
"4to1_Y_DS4_DISP",
"crop_rnd_clamp_post_downscale_mn_C_DISP",
"downscale_mn_C_DISP",
"crop_rnd_clamp_post_downscale_mn_Y_DISP"
),
VFE_DBG_INFO_ARRAY_4bit(
"downscale_mn_Y_DISP",
"crop_rnd_clamp_post_downscale_mn_C_FD",
"downscale_mn_C_FD",
"crop_rnd_clamp_post_downscale_mn_Y_FD",
"downscale_mn_Y_FD",
"gtm_fd_out",
"uvg",
"color_xform"
),
VFE_DBG_INFO_ARRAY_4bit(
"glut",
"gtm",
"color_correct",
"demosaic",
"hvx_tap2",
"lcac",
"bayer_ltm",
"bayer_gtm"
),
VFE_DBG_INFO_ARRAY_4bit(
"bls",
"bpc_abf",
"gic",
"wb_gain",
"lsc",
"compdecomp_hxv_rx",
"compdecomp_hxv_tx",
"hvx_tap1"
),
VFE_DBG_INFO_ARRAY_4bit(
"decompand",
"reserved",
"bincorrect",
"bpc_pdpc",
"channel_gain",
"bayer_argb_ccif_converter",
"crop_rnd_clamp_pre_argb_packer",
"chroma_up_uv"
),
VFE_DBG_INFO_ARRAY_4bit(
"chroma_up_y",
"demux",
"hxv_tap0",
"preprocess",
"sparse_pd_ext",
"lcr",
"bayer_ltm_bus_wr",
"RDI2"
),
VFE_DBG_INFO_ARRAY_4bit(
"RDI1",
"RDI0",
"lcr_bus_wr",
"pdaf_sad_bus_wr",
"pd_data_bus_wr",
"sparse_pd_bus_wr",
"ihist_bus_wr",
"flicker_rs_bus_wr"
),
VFE_DBG_INFO_ARRAY_4bit(
"gtm_bhist_bus_wr",
"baf_bus_wr",
"bfw_bus_wr",
"bg_bus_wr",
"tintless_bg_bus_wr",
"bhist_bus_wr",
"be_bus_wr",
"pixel_raw_bus_wr"
),
VFE_DBG_INFO_ARRAY_4bit(
"fd_c_bus_wr",
"fd_y_bus_wr",
"disp_ds16_bus_wr",
"disp_ds4_bus_wr",
"disp_c_bus_wr",
"disp_y_bus_wr",
"vid_ds16_bus_Wr",
"vid_ds4_bus_Wr"
),
VFE_DBG_INFO_ARRAY_4bit(
"vid_c_bus_wr",
"vid_y_bus_wr",
"CLC_PDAF",
"PIX_PP",
"reserved",
"reserved",
"reserved",
"reserved"
),
VFE_DBG_INFO_ARRAY_4bit(
"r2pd_reserved",
"r2pd_reserved",
"r2pd_reserved",
"r2pd_reserved",
"r2pd_reserved",
"r2pd_reserved",
"r2pd_reserved",
"r2pd_reserved"
),
VFE_DBG_INFO_ARRAY_4bit(
"r2pd_reserved",
"r2pd_reserved",
"r2pd_reserved",
"r2pd_reserved",
"r2pd_reserved",
"r2pd_reserved",
"r2pd_reserved",
"r2pd_reserved"
),
};
static struct cam_vfe_top_ver4_hw_info vfe680_top_hw_info = { static struct cam_vfe_top_ver4_hw_info vfe680_top_hw_info = {
.common_reg = &vfe680_top_common_reg, .common_reg = &vfe680_top_common_reg,
.vfe_full_hw_info = { .vfe_full_hw_info = {
@@ -616,6 +789,7 @@ static struct cam_vfe_top_ver4_hw_info vfe680_top_hw_info = {
.top_err_desc = vfe680_top_irq_err_desc, .top_err_desc = vfe680_top_irq_err_desc,
.num_pdaf_violation_errors = ARRAY_SIZE(vfe680_pdaf_violation_desc), .num_pdaf_violation_errors = ARRAY_SIZE(vfe680_pdaf_violation_desc),
.pdaf_violation_desc = vfe680_pdaf_violation_desc, .pdaf_violation_desc = vfe680_pdaf_violation_desc,
.debug_reg_info = &vfe680_dbg_reg_info,
}; };
static struct cam_irq_register_set vfe680_bus_irq_reg[2] = { static struct cam_irq_register_set vfe680_bus_irq_reg[2] = {

177
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe780.h
View File

@@ -11,6 +11,7 @@
#include "cam_irq_controller.h" #include "cam_irq_controller.h"
#define CAM_VFE_BUS_VER3_780_MAX_CLIENTS 27 #define CAM_VFE_BUS_VER3_780_MAX_CLIENTS 27
#define CAM_VFE_780_NUM_DBG_REG 17
static struct cam_vfe_top_ver4_module_desc vfe780_ipp_mod_desc[] = { static struct cam_vfe_top_ver4_module_desc vfe780_ipp_mod_desc[] = {
{ {
@@ -527,7 +528,7 @@ static struct cam_vfe_top_ver4_reg_offset_common vfe780_top_common_reg = {
.bus_violation_status = 0x00000C64, .bus_violation_status = 0x00000C64,
.bus_overflow_status = 0x00000C68, .bus_overflow_status = 0x00000C68,
.top_debug_cfg = 0x000000FC, .top_debug_cfg = 0x000000FC,
.num_top_debug_reg = 17, .num_top_debug_reg = CAM_VFE_780_NUM_DBG_REG,
.top_debug = { .top_debug = {
0x000000A0, 0x000000A0,
0x000000A4, 0x000000A4,
@@ -609,6 +610,179 @@ struct cam_vfe_ver4_path_hw_info
}, },
}; };
static struct cam_vfe_top_ver4_debug_reg_info vfe780_dbg_reg_info[CAM_VFE_780_NUM_DBG_REG][8] = {
VFE_DBG_INFO_ARRAY_4bit("test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved"
),
VFE_DBG_INFO_ARRAY_4bit(
"STATS_IHIST",
"STATS_RS",
"STATS_CAF",
"GTM_BHIST",
"TINTLESS_BG",
"STATS_BFW",
"STATS_BG",
"STATS_BHIST"
),
VFE_DBG_INFO_ARRAY_4bit(
"STATS_BE",
"R2PD_DS16_C_VID",
"R2PD_DS16_Y_VID",
"crop_rnd_clamp_post_downscale_C_DS16_VID",
"4to1_C_DS16_VID",
"crop_rnd_clamp_post_downscale_Y_DS16_VID",
"4to1_Y_DS16_VID",
"crop_rnd_clamp_post_dsx_C_VID"
),
VFE_DBG_INFO_ARRAY_4bit(
"R2PD_DS4_VID_C",
"R2PD_DS4_VID_Y",
"DSX_C",
"crop_rnd_clamp_post_dsx_Y_VID",
"DSX_Y",
"crop_rnd_clamp_post_downscale_mn_C_VID",
"downscale_mn_C_VID",
"crop_rnd_clamp_post_downscale_mn_Y_VID"
),
VFE_DBG_INFO_ARRAY_4bit(
"MNDS_Y_VID",
"R2PD_DS16_C_DISP",
"R2PD_DS16_Y_DISP",
"crop_rnd_clamp_post_downscale_C_DS16_DISP",
"4to1_C_DS16_DISP",
"crop_rnd_clamp_post_downscale_Y_DS16_DISP",
"4to1_Y_DS16_DISP",
"R2PD_DS4_C_DISP"
),
VFE_DBG_INFO_ARRAY_4bit(
"R2PD_DS4_Y_DISP",
"crop_rnd_clamp_post_downscale_C_DS4_DISP",
"4to1_C_DS4_DISP",
"crop_rnd_clamp_post_downscale_Y_DS4_DISP",
"4to1_Y_DS4_DISP",
"crop_rnd_clamp_post_downscale_mn_C_DISP",
"downscale_mn_C_DISP",
"crop_rnd_clamp_post_downscale_mn_Y_DISP"
),
VFE_DBG_INFO_ARRAY_4bit(
"downscale_mn_Y_DISP",
"crop_rnd_clamp_post_downscale_mn_C_FD",
"downscale_mn_C_FD",
"crop_rnd_clamp_post_downscale_mn_Y_FD",
"downscale_mn_Y_FD",
"gtm_fd_out",
"uvg",
"color_xform"
),
VFE_DBG_INFO_ARRAY_4bit(
"glut",
"gtm",
"color_correct",
"demosaic",
"hvx_tap2",
"lcac",
"bayer_ltm",
"bayer_gtm"
),
VFE_DBG_INFO_ARRAY_4bit(
"bls",
"bpc_abf",
"gic",
"wb_gain",
"lsc",
"compdecomp_hxv_rx",
"compdecomp_hxv_tx",
"hvx_tap1"
),
VFE_DBG_INFO_ARRAY_4bit(
"decompand",
"reserved",
"bincorrect",
"bpc_pdpc",
"channel_gain",
"bayer_argb_ccif_converter",
"crop_rnd_clamp_pre_argb_packer",
"chroma_up_uv"
),
VFE_DBG_INFO_ARRAY_4bit(
"chroma_up_y",
"demux",
"hxv_tap0",
"preprocess",
"reserved",
"reserved",
"bayer_ltm_bus_wr",
"RDI2"
),
VFE_DBG_INFO_ARRAY_4bit(
"RDI1",
"RDI0",
"reserved",
"pdaf_2_bus_wr",
"pdaf_1_bus_wr",
"pdaf_1_bus_wr",
"ihist_bus_wr",
"flicker_rs_bus_wr"
),
VFE_DBG_INFO_ARRAY_4bit(
"gtm_bhist_bus_wr",
"caf_bus_wr",
"bfw_bus_wr",
"bg_bus_wr",
"tintless_bg_bus_wr",
"bhist_bus_wr",
"be_bus_wr",
"pixel_raw_bus_wr"
),
VFE_DBG_INFO_ARRAY_4bit(
"fd_c_bus_wr",
"fd_y_bus_wr",
"disp_ds16_bus_wr",
"disp_ds4_bus_wr",
"disp_c_bus_wr",
"disp_y_bus_wr",
"vid_ds16_bus_Wr",
"vid_ds4_bus_Wr"
),
VFE_DBG_INFO_ARRAY_4bit(
"vid_c_bus_wr",
"vid_y_bus_wr",
"CLC_PDAF",
"PIX_PP",
"reserved",
"reserved",
"reserved",
"reserved"
),
{
/* needs to be parsed separately, doesn't conform to I, V, R */
VFE_DBG_INFO(32, "lcr_pd_timing_debug"),
VFE_DBG_INFO(32, "lcr_pd_timing_debug"),
VFE_DBG_INFO(32, "lcr_pd_timing_debug"),
VFE_DBG_INFO(32, "lcr_pd_timing_debug"),
VFE_DBG_INFO(32, "lcr_pd_timing_debug"),
VFE_DBG_INFO(32, "lcr_pd_timing_debug"),
VFE_DBG_INFO(32, "lcr_pd_timing_debug"),
VFE_DBG_INFO(32, "lcr_pd_timing_debug"),
},
VFE_DBG_INFO_ARRAY_4bit(
"r2pd_reserved",
"r2pd_reserved",
"r2pd_reserved",
"r2pd_reserved",
"r2pd_reserved",
"r2pd_reserved",
"r2pd_reserved",
"r2pd_reserved"
),
};
static struct cam_vfe_top_ver4_hw_info vfe780_top_hw_info = { static struct cam_vfe_top_ver4_hw_info vfe780_top_hw_info = {
.common_reg = &vfe780_top_common_reg, .common_reg = &vfe780_top_common_reg,
.vfe_full_hw_info = { .vfe_full_hw_info = {
@@ -642,6 +816,7 @@ static struct cam_vfe_top_ver4_hw_info vfe780_top_hw_info = {
.top_err_desc = vfe780_top_irq_err_desc, .top_err_desc = vfe780_top_irq_err_desc,
.num_pdaf_violation_errors = ARRAY_SIZE(vfe780_pdaf_violation_desc), .num_pdaf_violation_errors = ARRAY_SIZE(vfe780_pdaf_violation_desc),
.pdaf_violation_desc = vfe780_pdaf_violation_desc, .pdaf_violation_desc = vfe780_pdaf_violation_desc,
.debug_reg_info = &vfe780_dbg_reg_info,
}; };
static struct cam_irq_register_set vfe780_bus_irq_reg[2] = { static struct cam_irq_register_set vfe780_bus_irq_reg[2] = {

58
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite68x.h
View File

@@ -12,6 +12,8 @@
#include "cam_vfe_bus_ver3.h" #include "cam_vfe_bus_ver3.h"
#include "cam_irq_controller.h" #include "cam_irq_controller.h"
#define CAM_VFE_68X_NUM_DBG_REG 5
static struct cam_vfe_top_ver4_module_desc vfe68x_ipp_mod_desc[] = { static struct cam_vfe_top_ver4_module_desc vfe68x_ipp_mod_desc[] = {
{ {
.id = 0, .id = 0,
@@ -87,7 +89,7 @@ static struct cam_vfe_top_ver4_reg_offset_common vfe68x_top_common_reg = {
.bus_violation_status = 0x00001264, .bus_violation_status = 0x00001264,
.bus_overflow_status = 0x00001268, .bus_overflow_status = 0x00001268,
.top_debug_cfg = 0x00001074, .top_debug_cfg = 0x00001074,
.num_top_debug_reg = 5, .num_top_debug_reg = CAM_VFE_68X_NUM_DBG_REG,
.top_debug = { .top_debug = {
0x0000105C, 0x0000105C,
0x00001060, 0x00001060,
@@ -159,6 +161,58 @@ static struct cam_vfe_ver4_path_hw_info
}, },
}; };
static struct cam_vfe_top_ver4_debug_reg_info vfe68x_dbg_reg_info[CAM_VFE_68X_NUM_DBG_REG][8] = {
VFE_DBG_INFO_ARRAY_4bit(
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved"
),
{
VFE_DBG_INFO(32, "non-CLC info"),
VFE_DBG_INFO(32, "non-CLC info"),
VFE_DBG_INFO(32, "non-CLC info"),
VFE_DBG_INFO(32, "non-CLC info"),
VFE_DBG_INFO(32, "non-CLC info"),
VFE_DBG_INFO(32, "non-CLC info"),
VFE_DBG_INFO(32, "non-CLC info"),
VFE_DBG_INFO(32, "non-CLC info"),
},
VFE_DBG_INFO_ARRAY_4bit(
"PP_THROTTLE",
"STATS_BG_THROTTLE",
"STATS_BG",
"BLS",
"GLUT",
"unused",
"unused",
"unused"
),
VFE_DBG_INFO_ARRAY_4bit(
"RDI_0",
"RDI_1",
"RDI_2",
"RDI_3",
"PP_STATS_BG",
"PP_GLUT",
"PP_STATS_BG",
"PP_GLUT"
),
VFE_DBG_INFO_ARRAY_4bit(
"unused",
"unused",
"unused",
"unused",
"unused",
"unused",
"unused",
"unused"
),
};
static struct cam_vfe_top_ver4_hw_info vfe68x_top_hw_info = { static struct cam_vfe_top_ver4_hw_info vfe68x_top_hw_info = {
.common_reg = &vfe68x_top_common_reg, .common_reg = &vfe68x_top_common_reg,
@@ -180,7 +234,7 @@ static struct cam_vfe_top_ver4_hw_info vfe68x_top_hw_info = {
CAM_VFE_RDI_VER_1_0, CAM_VFE_RDI_VER_1_0,
CAM_VFE_RDI_VER_1_0, CAM_VFE_RDI_VER_1_0,
}, },
.debug_reg_info = &vfe68x_dbg_reg_info,
}; };
static struct cam_irq_register_set vfe680x_bus_irq_reg[2] = { static struct cam_irq_register_set vfe680x_bus_irq_reg[2] = {

58
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite78x.h
View File

@@ -12,6 +12,8 @@
#include "cam_vfe_bus_ver3.h" #include "cam_vfe_bus_ver3.h"
#include "cam_irq_controller.h" #include "cam_irq_controller.h"
#define CAM_VFE_78X_NUM_DBG_REG 5
static struct cam_vfe_top_ver4_module_desc vfe_lite78x_ipp_mod_desc[] = { static struct cam_vfe_top_ver4_module_desc vfe_lite78x_ipp_mod_desc[] = {
{ {
.id = 0, .id = 0,
@@ -87,7 +89,7 @@ static struct cam_vfe_top_ver4_reg_offset_common vfe_lite78x_top_common_reg = {
.bus_violation_status = 0x00001264, .bus_violation_status = 0x00001264,
.bus_overflow_status = 0x00001268, .bus_overflow_status = 0x00001268,
.top_debug_cfg = 0x00001074, .top_debug_cfg = 0x00001074,
.num_top_debug_reg = 5, .num_top_debug_reg = CAM_VFE_78X_NUM_DBG_REG,
.top_debug = { .top_debug = {
0x0000105C, 0x0000105C,
0x00001060, 0x00001060,
@@ -159,6 +161,58 @@ static struct cam_vfe_ver4_path_hw_info
}, },
}; };
static struct cam_vfe_top_ver4_debug_reg_info vfe78x_dbg_reg_info[CAM_VFE_78X_NUM_DBG_REG][8] = {
VFE_DBG_INFO_ARRAY_4bit(
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved",
"test_bus_reserved"
),
{
VFE_DBG_INFO(32, "non-CLC info"),
VFE_DBG_INFO(32, "non-CLC info"),
VFE_DBG_INFO(32, "non-CLC info"),
VFE_DBG_INFO(32, "non-CLC info"),
VFE_DBG_INFO(32, "non-CLC info"),
VFE_DBG_INFO(32, "non-CLC info"),
VFE_DBG_INFO(32, "non-CLC info"),
VFE_DBG_INFO(32, "non-CLC info"),
},
VFE_DBG_INFO_ARRAY_4bit(
"PP_THROTTLE",
"STATS_BG_THROTTLE",
"STATS_BG",
"BLS",
"GLUT",
"unused",
"unused",
"unused"
),
VFE_DBG_INFO_ARRAY_4bit(
"RDI_0",
"RDI_1",
"RDI_2",
"RDI_3",
"PP_STATS_BG",
"PP_GLUT",
"PP_STATS_BG",
"PP_GLUT"
),
VFE_DBG_INFO_ARRAY_4bit(
"unused",
"unused",
"unused",
"unused",
"unused",
"unused",
"unused",
"unused"
),
};
static struct cam_vfe_top_ver4_hw_info vfe_lite78x_top_hw_info = { static struct cam_vfe_top_ver4_hw_info vfe_lite78x_top_hw_info = {
.common_reg = &vfe_lite78x_top_common_reg, .common_reg = &vfe_lite78x_top_common_reg,
@@ -180,7 +234,7 @@ static struct cam_vfe_top_ver4_hw_info vfe_lite78x_top_hw_info = {
CAM_VFE_RDI_VER_1_0, CAM_VFE_RDI_VER_1_0,
CAM_VFE_RDI_VER_1_0, CAM_VFE_RDI_VER_1_0,
}, },
.debug_reg_info = &vfe78x_dbg_reg_info,
}; };
static struct cam_irq_register_set vfe_lite78x_bus_irq_reg[1] = { static struct cam_irq_register_set vfe_lite78x_bus_irq_reg[1] = {

686
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.c
View File

@@ -32,6 +32,7 @@ struct cam_vfe_top_ver4_priv {
struct cam_vfe_top_priv_common top_common; struct cam_vfe_top_priv_common top_common;
atomic_t overflow_pending; atomic_t overflow_pending;
uint8_t log_buf[CAM_VFE_LEN_LOG_BUF]; uint8_t log_buf[CAM_VFE_LEN_LOG_BUF];
uint32_t sof_cnt;
}; };
struct cam_vfe_mux_ver4_data { struct cam_vfe_mux_ver4_data {
@@ -82,592 +83,6 @@ struct cam_vfe_mux_ver4_data {
struct timespec64 error_ts; struct timespec64 error_ts;
}; };
struct cam_vfe_top_debug_info {
uint32_t shift;
char *clc_name;
};
static const struct cam_vfe_top_debug_info vfe_dbg_list[][8] = {
{
{
.shift = 0,
.clc_name = "test_bus_reserved"
},
{
.shift = 4,
.clc_name = "test_bus_reserved"
},
{
.shift = 8,
.clc_name = "test_bus_reserved"
},
{
.shift = 12,
.clc_name = "test_bus_reserved"
},
{
.shift = 16,
.clc_name = "test_bus_reserved"
},
{
.shift = 20,
.clc_name = "test_bus_reserved"
},
{
.shift = 24,
.clc_name = "test_bus_reserved"
},
{
.shift = 28,
.clc_name = "test_bus_reserved"
},
},
{
{
.shift = 0,
.clc_name = "STATS_IHIST"
},
{
.shift = 4,
.clc_name = "STATS_RS"
},
{
.shift = 8,
.clc_name = "STATS_BAF"
},
{
.shift = 12,
.clc_name = "GTM_BHIST"
},
{
.shift = 16,
.clc_name = "TINTLESS_BG"
},
{
.shift = 20,
.clc_name = "STATS_BFW"
},
{
.shift = 24,
.clc_name = "STATS_BG"
},
{
.shift = 28,
.clc_name = "STATS_BHIST"
},
},
{
{
.shift = 0,
.clc_name = "STATS_BE"
},
{
.shift = 4,
.clc_name = "R2PD_DS16_C_VID"
},
{
.shift = 8,
.clc_name = "R2PD_DS16_Y_VID"
},
{
.shift = 12,
.clc_name = "crop_rnd_clamp_post_downscale_C_DS16_VID"
},
{
.shift = 16,
.clc_name = "4to1_C_DS16_VID"
},
{
.shift = 20,
.clc_name = "crop_rnd_clamp_post_downscale_Y_DS16_VID"
},
{
.shift = 24,
.clc_name = "4to1_Y_DS16_VID"
},
{
.shift = 28,
.clc_name = "crop_rnd_clamp_post_dsx_C_VID"
},
},
{
{
.shift = 0,
.clc_name = "R2PD_DS4_VID_C"
},
{
.shift = 4,
.clc_name = "R2PD_DS4_VID_Y"
},
{
.shift = 8,
.clc_name = "DSX_C"
},
{
.shift = 12,
.clc_name = "crop_rnd_clamp_post_dsx_Y_VID"
},
{
.shift = 16,
.clc_name = "DSX_Y"
},
{
.shift = 20,
.clc_name = "crop_rnd_clamp_post_downscale_mn_C_VID"
},
{
.shift = 24,
.clc_name = "downscale_mn_C_VID"
},
{
.shift = 28,
.clc_name = "crop_rnd_clamp_post_downscale_mn_Y_VID"
},
},
{
{
.shift = 0,
.clc_name = "MNDS_Y_VID"
},
{
.shift = 4,
.clc_name = "R2PD_DS16_C_DISP"
},
{
.shift = 8,
.clc_name = "R2PD_DS16_Y_DISP"
},
{
.shift = 12,
.clc_name = "crop_rnd_clamp_post_downscale_C_DS16_DISP"
},
{
.shift = 16,
.clc_name = "4to1_C_DS16_DISP"
},
{
.shift = 20,
.clc_name = "crop_rnd_clamp_post_downscale_Y_DS16_DISP"
},
{
.shift = 24,
.clc_name = "4to1_Y_DS16_DISP"
},
{
.shift = 28,
.clc_name = "R2PD_DS4_C_DISP"
},
},
{
{
.shift = 0,
.clc_name = "R2PD_DS4_Y_DISP"
},
{
.shift = 4,
.clc_name = "crop_rnd_clamp_post_downscale_C_DS4_DISP"
},
{
.shift = 8,
.clc_name = "4to1_C_DS4_DISP"
},
{
.shift = 12,
.clc_name = "crop_rnd_clamp_post_downscale_Y_DS4_DISP"
},
{
.shift = 16,
.clc_name = "4to1_Y_DS4_DISP"
},
{
.shift = 20,
.clc_name = "crop_rnd_clamp_post_downscale_mn_C_DISP"
},
{
.shift = 24,
.clc_name = "downscale_mn_C_DISP"
},
{
.shift = 28,
.clc_name = "crop_rnd_clamp_post_downscale_mn_Y_DISP"
},
},
{
{
.shift = 0,
.clc_name = "downscale_mn_Y_DISP"
},
{
.shift = 4,
.clc_name = "crop_rnd_clamp_post_downscale_mn_C_FD"
},
{
.shift = 8,
.clc_name = "downscale_mn_C_FD"
},
{
.shift = 12,
.clc_name = "crop_rnd_clamp_post_downscale_mn_Y_FD"
},
{
.shift = 16,
.clc_name = "downscale_mn_Y_FD"
},
{
.shift = 20,
.clc_name = "gtm_fd_out"
},
{
.shift = 24,
.clc_name = "uvg"
},
{
.shift = 28,
.clc_name = "color_xform"
},
},
{
{
.shift = 0,
.clc_name = "glut"
},
{
.shift = 4,
.clc_name = "gtm"
},
{
.shift = 8,
.clc_name = "color_correct"
},
{
.shift = 12,
.clc_name = "demosaic"
},
{
.shift = 16,
.clc_name = "hvx_tap2"
},
{
.shift = 20,
.clc_name = "lcac"
},
{
.shift = 24,
.clc_name = "bayer_ltm"
},
{
.shift = 28,
.clc_name = "bayer_gtm"
},
},
{
{
.shift = 0,
.clc_name = "bls"
},
{
.shift = 4,
.clc_name = "bpc_abf"
},
{
.shift = 8,
.clc_name = "gic"
},
{
.shift = 12,
.clc_name = "wb_gain"
},
{
.shift = 16,
.clc_name = "lsc"
},
{
.shift = 20,
.clc_name = "compdecomp_hxv_rx"
},
{
.shift = 24,
.clc_name = "compdecomp_hxv_tx"
},
{
.shift = 28,
.clc_name = "hvx_tap1"
},
},
{
{
.shift = 0,
.clc_name = "decompand"
},
{
.shift = 4,
.clc_name = "reserved"
},
{
.shift = 8,
.clc_name = "bincorrect"
},
{
.shift = 12,
.clc_name = "bpc_pdpc"
},
{
.shift = 16,
.clc_name = "channel_gain"
},
{
.shift = 20,
.clc_name = "bayer_argb_ccif_converter"
},
{
.shift = 24,
.clc_name = "crop_rnd_clamp_pre_argb_packer"
},
{
.shift = 28,
.clc_name = "chroma_up_uv"
},
},
{
{
.shift = 0,
.clc_name = "chroma_up_y"
},
{
.shift = 4,
.clc_name = "demux"
},
{
.shift = 8,
.clc_name = "hxv_tap0"
},
{
.shift = 12,
.clc_name = "preprocess"
},
{
.shift = 16,
.clc_name = "sparse_pd_ext"
},
{
.shift = 20,
.clc_name = "lcr"
},
{
.shift = 24,
.clc_name = "bayer_ltm_bus_wr"
},
{
.shift = 28,
.clc_name = "RDI2"
},
},
{
{
.shift = 0,
.clc_name = "RDI1"
},
{
.shift = 4,
.clc_name = "RDI0"
},
{
.shift = 8,
.clc_name = "lcr_bus_wr"
},
{
.shift = 12,
.clc_name = "pdaf_sad_bus_wr"
},
{
.shift = 16,
.clc_name = "pd_data_bus_wr"
},
{
.shift = 20,
.clc_name = "sparse_pd_bus_wr"
},
{
.shift = 24,
.clc_name = "ihist_bus_wr"
},
{
.shift = 28,
.clc_name = "flicker_rs_bus_wr"
},
},
{
{
.shift = 0,
.clc_name = "gtm_bhist_bus_wr"
},
{
.shift = 4,
.clc_name = "baf_bus_wr"
},
{
.shift = 8,
.clc_name = "bfw_bus_wr"
},
{
.shift = 12,
.clc_name = "bg_bus_wr"
},
{
.shift = 16,
.clc_name = "tintless_bg_bus_wr"
},
{
.shift = 20,
.clc_name = "bhist_bus_wr"
},
{
.shift = 24,
.clc_name = "be_bus_wr"
},
{
.shift = 28,
.clc_name = "pixel_raw_bus_wr"
},
},
{
{
.shift = 0,
.clc_name = "fd_c_bus_wr"
},
{
.shift = 4,
.clc_name = "fd_y_bus_wr"
},
{
.shift = 8,
.clc_name = "disp_ds16_bus_wr"
},
{
.shift = 12,
.clc_name = "disp_ds4_bus_wr"
},
{
.shift = 16,
.clc_name = "disp_c_bus_wr"
},
{
.shift = 20,
.clc_name = "disp_y_bus_wr"
},
{
.shift = 24,
.clc_name = "vid_ds16_bus_Wr"
},
{
.shift = 28,
.clc_name = "vid_ds4_bus_Wr"
},
},
{
{
.shift = 0,
.clc_name = "vid_c_bus_wr"
},
{
.shift = 4,
.clc_name = "vid_y_bus_wr"
},
{
.shift = 8,
.clc_name = "CLC_PDAF"
},
{
.shift = 12,
.clc_name = "PIX_PP"
},
{
.shift = 16,
.clc_name = "reserved"
},
{
.shift = 20,
.clc_name = "reserved"
},
{
.shift = 24,
.clc_name = "reserved"
},
{
.shift = 28,
.clc_name = "reserved"
},
},
{
{
.shift = 0,
.clc_name = "r2pd_reserved"
},
{
.shift = 4,
.clc_name = "r2pd_reserved"
},
{
.shift = 8,
.clc_name = "r2pd_reserved"
},
{
.shift = 12,
.clc_name = "r2pd_reserved"
},
{
.shift = 16,
.clc_name = "r2pd_reserved"
},
{
.shift = 20,
.clc_name = "r2pd_reserved"
},
{
.shift = 24,
.clc_name = "r2pd_reserved"
},
{
.shift = 28,
.clc_name = "r2pd_reserved"
},
},
{
{
.shift = 0,
.clc_name = "r2pd_reserved"
},
{
.shift = 4,
.clc_name = "r2pd_reserved"
},
{
.shift = 8,
.clc_name = "r2pd_reserved"
},
{
.shift = 12,
.clc_name = "r2pd_reserved"
},
{
.shift = 16,
.clc_name = "r2pd_reserved"
},
{
.shift = 20,
.clc_name = "r2pd_reserved"
},
{
.shift = 24,
.clc_name = "r2pd_reserved"
},
{
.shift = 28,
.clc_name = "r2pd_reserved"
},
},
};
static int cam_vfe_top_ver4_get_path_port_map(struct cam_vfe_top_ver4_priv *top_priv, static int cam_vfe_top_ver4_get_path_port_map(struct cam_vfe_top_ver4_priv *top_priv,
void *cmd_args, uint32_t arg_size) void *cmd_args, uint32_t arg_size)
{ {
@@ -751,7 +166,7 @@ static int cam_vfe_top_fs_update(
static void cam_vfe_top_ver4_check_module_status( static void cam_vfe_top_ver4_check_module_status(
uint32_t num_reg, uint32_t *reg_val, uint32_t num_reg, uint32_t *reg_val,
const struct cam_vfe_top_debug_info status_list[][8]) struct cam_vfe_top_ver4_debug_reg_info (*status_list)[][8])
{ {
bool found = false; bool found = false;
uint32_t i, j, val = 0; uint32_t i, j, val = 0;
@@ -767,13 +182,13 @@ static void cam_vfe_top_ver4_check_module_status(
continue; continue;
for (j = 0; j < 8; j++) { for (j = 0; j < 8; j++) {
val = reg_val[i] >> status_list[i][j].shift; val = reg_val[i] >> (*status_list)[i][j].shift;
val &= 0xF; val &= 0xF;
if (val == 0 || val == 5) if (val == 0 || val == 5)
continue; continue;
CAM_INFO_BUF(CAM_ISP, log_buf, 1024, &len, "%s [I:%u V:%u R:%u]", CAM_INFO_BUF(CAM_ISP, log_buf, 1024, &len, "%s [I:%u V:%u R:%u]",
status_list[i][j].clc_name, (*status_list)[i][j].clc_name,
((val >> 2) & 1), ((val >> 1) & 1), (val & 1)); ((val >> 2) & 1), ((val >> 1) & 1), (val & 1));
found = true; found = true;
} }
@@ -877,21 +292,15 @@ static void cam_vfe_top_ver4_print_debug_reg_status(
uint32_t i = 0, j; uint32_t i = 0, j;
size_t len = 0; size_t len = 0;
uint8_t *log_buf; uint8_t *log_buf;
uint32_t *reg_val = NULL; uint32_t reg_val[CAM_VFE_TOP_DBG_REG_MAX] = {0};
struct cam_hw_soc_info *soc_info; struct cam_hw_soc_info *soc_info;
struct cam_vfe_soc_private *soc_priv;
void __iomem *base; void __iomem *base;
soc_info = top_priv->top_common.soc_info; soc_info = top_priv->top_common.soc_info;
soc_priv = soc_info->soc_private;
common_reg = top_priv->common_data.common_reg; common_reg = top_priv->common_data.common_reg;
num_reg = common_reg->num_top_debug_reg; num_reg = common_reg->num_top_debug_reg;
base = soc_info->reg_map[VFE_CORE_BASE_IDX].mem_base; base = soc_info->reg_map[VFE_CORE_BASE_IDX].mem_base;
log_buf = top_priv->log_buf; log_buf = top_priv->log_buf;
reg_val = kcalloc(num_reg, sizeof(uint32_t), GFP_KERNEL);
if (!reg_val)
return;
while (i < num_reg) { while (i < num_reg) {
for(j = 0; j < 4 && i < num_reg; j++, i++) { for(j = 0; j < 4 && i < num_reg; j++, i++) {
@@ -907,16 +316,7 @@ static void cam_vfe_top_ver4_print_debug_reg_status(
} }
cam_vfe_top_ver4_check_module_status(num_reg, reg_val, cam_vfe_top_ver4_check_module_status(num_reg, reg_val,
((soc_priv->is_ife_lite) ? NULL : vfe_dbg_list)); top_priv->common_data.hw_info->debug_reg_info);
CAM_ERR(CAM_ISP, "VFE[%u] Bus overflow status 0x%x",
soc_info->index,
cam_io_r(base + common_reg->bus_overflow_status));
CAM_ERR(CAM_ISP, "VFE[%u] Bus Violation status 0x%x",
soc_info->index,
cam_io_r(base + common_reg->bus_violation_status));
kfree(reg_val);
} }
int cam_vfe_top_ver4_dump_timestamps( int cam_vfe_top_ver4_dump_timestamps(
@@ -986,27 +386,31 @@ static int cam_vfe_top_ver4_print_overflow_debug_info(
struct cam_vfe_top_ver4_common_data *common_data; struct cam_vfe_top_ver4_common_data *common_data;
struct cam_hw_soc_info *soc_info; struct cam_hw_soc_info *soc_info;
struct cam_vfe_soc_private *soc_private = NULL; struct cam_vfe_soc_private *soc_private = NULL;
uint32_t status = 0, bus_overflow_status = 0; uint32_t violation_status = 0, bus_overflow_status = 0, tmp;
uint32_t i = 0; uint32_t i = 0;
int res_id; int res_id = *((int *)(cmd_args));
common_data = &top_priv->common_data; common_data = &top_priv->common_data;
soc_info = top_priv->top_common.soc_info; soc_info = top_priv->top_common.soc_info;
soc_private = soc_info->soc_private; soc_private = soc_info->soc_private;
status = cam_io_r(soc_info->reg_map[VFE_CORE_BASE_IDX].mem_base + bus_overflow_status = cam_io_r(soc_info->reg_map[VFE_CORE_BASE_IDX].mem_base +
common_data->common_reg->bus_overflow_status); common_data->common_reg->bus_overflow_status);
bus_overflow_status = status; violation_status = cam_io_r(soc_info->reg_map[VFE_CORE_BASE_IDX].mem_base +
res_id = *((int *)(cmd_args)); common_data->common_reg->bus_violation_status);
CAM_ERR_RATE_LIMIT(CAM_ISP, "VFE[%d] src_clk_rate:%luHz res: %u overflow_status 0x%x",
soc_info->index, soc_info->applied_src_clk_rate,
res_id, status);
while (status) { CAM_ERR_RATE_LIMIT(CAM_ISP, "VFE[%d] sof_cnt:%d src_clk:%luMHz overflow:%s violation:%s",
if (status & 0x1) top_priv->sof_cnt, soc_info->index, soc_info->applied_src_clk_rate / 1000000,
CAM_ERR_RATE_LIMIT(CAM_ISP, "VFE Bus Overflow %s", CAM_BOOL_TO_YESNO(bus_overflow_status), CAM_BOOL_TO_YESNO(violation_status));
common_data->hw_info->wr_client_desc[i].desc);
status = status >> 1; if (bus_overflow_status)
CAM_INFO_RATE_LIMIT(CAM_ISP, "VFE[%d] Bus overflow status: 0x%x",
soc_info->index, bus_overflow_status);
while (bus_overflow_status) {
if (bus_overflow_status & 0x1)
CAM_ERR_RATE_LIMIT(CAM_ISP, "VFE[%d] Bus Overflow %s",
soc_info->index, common_data->hw_info->wr_client_desc[i].desc);
bus_overflow_status = bus_overflow_status >> 1;
i++; i++;
} }
@@ -1015,17 +419,17 @@ static int cam_vfe_top_ver4_print_overflow_debug_info(
if (bus_overflow_status) if (bus_overflow_status)
cam_cpas_log_votes(); cam_cpas_log_votes();
status = cam_io_r(soc_info->reg_map[VFE_CORE_BASE_IDX].mem_base + if (violation_status)
common_data->common_reg->bus_violation_status); CAM_INFO_RATE_LIMIT(CAM_ISP, "VFE[%d] Bus violation status: 0x%x",
CAM_ERR_RATE_LIMIT(CAM_ISP, "VFE[%d] Bus violation_status 0x%x", soc_info->index, violation_status);
soc_info->index, status);
i = 0; i = 0;
while (status) { tmp = violation_status;
if (status & 0x1) while (violation_status) {
CAM_INFO_RATE_LIMIT(CAM_ISP, "VFE Bus Violation %s", if (tmp & 0x1)
common_data->hw_info->wr_client_desc[i].desc); CAM_ERR_RATE_LIMIT(CAM_ISP, "VFE[%d] Bus Violation %s",
status = status >> 1; soc_info->index, common_data->hw_info->wr_client_desc[i].desc);
tmp = tmp >> 1;
i++; i++;
} }
@@ -1146,24 +550,6 @@ int cam_vfe_top_ver4_init_hw(void *device_priv,
top_priv->top_common.applied_clk_rate = 0; top_priv->top_common.applied_clk_rate = 0;
/**
* Auto clock gating is enabled by default, but no harm
* in setting the value we expect.
*/
CAM_DBG(CAM_ISP, "Enabling clock gating at IFE top");
cam_soc_util_w_mb(top_priv->top_common.soc_info, VFE_CORE_BASE_IDX,
common_data.common_reg->core_cgc_ovd_0, 0x0);
cam_soc_util_w_mb(top_priv->top_common.soc_info, VFE_CORE_BASE_IDX,
common_data.common_reg->core_cgc_ovd_1, 0x0);
cam_soc_util_w_mb(top_priv->top_common.soc_info, VFE_CORE_BASE_IDX,
common_data.common_reg->ahb_cgc_ovd, 0x0);
cam_soc_util_w_mb(top_priv->top_common.soc_info, VFE_CORE_BASE_IDX,
common_data.common_reg->noc_cgc_ovd, 0x0);
top_priv->top_common.hw_version = cam_io_r_mb( top_priv->top_common.hw_version = cam_io_r_mb(
top_priv->top_common.soc_info->reg_map[0].mem_base + top_priv->top_common.soc_info->reg_map[0].mem_base +
common_data.common_reg->hw_version); common_data.common_reg->hw_version);
@@ -1218,11 +604,11 @@ int cam_vfe_top_acquire_resource(
config_done: config_done:
CAM_DBG(CAM_ISP, CAM_DBG(CAM_ISP,
"VFE:%d Res:[id:%d name:%s] pix_pattern:%d dsp_mode=%d is_dual:%d dual_hw_idx:%d", "VFE:%d Res:[id:%d name:%s] dsp_mode:%d is_dual:%d dual_hw_idx:%d",
vfe_full_res->hw_intf->hw_idx, vfe_full_res->hw_intf->hw_idx,
vfe_full_res->res_id, vfe_full_res->res_id,
vfe_full_res->res_name, vfe_full_res->res_name,
res_data->pix_pattern, res_data->dsp_mode, res_data->dsp_mode,
res_data->is_dual, res_data->dual_hw_idx); res_data->is_dual, res_data->dual_hw_idx);
return rc; return rc;
@@ -1677,6 +1063,7 @@ static int cam_vfe_handle_irq_bottom_half(void *handler_priv,
vfe_priv->sof_ts.tv_nsec = vfe_priv->sof_ts.tv_nsec =
payload->ts.mono_time.tv_nsec; payload->ts.mono_time.tv_nsec;
} }
vfe_priv->top_priv->sof_cnt++;
cam_cpas_notify_event("IFE SOF", evt_info.hw_idx); cam_cpas_notify_event("IFE SOF", evt_info.hw_idx);
@@ -1870,6 +1257,9 @@ static int cam_vfe_resource_start(
skip_core_cfg: skip_core_cfg:
vfe_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING; vfe_res->res_state = CAM_ISP_RESOURCE_STATE_STREAMING;
/* reset sof count */
rsrc_data->top_priv->sof_cnt = 0;
/* disable sof irq debug flag */ /* disable sof irq debug flag */
rsrc_data->enable_sof_irq_debug = false; rsrc_data->enable_sof_irq_debug = false;
rsrc_data->irq_debug_cnt = 0; rsrc_data->irq_debug_cnt = 0;

24
drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.h
View File

@@ -98,17 +98,21 @@ struct cam_vfe_ver4_path_hw_info {
struct cam_vfe_ver4_path_reg_data *reg_data; struct cam_vfe_ver4_path_reg_data *reg_data;
}; };
struct cam_vfe_top_ver4_debug_reg_info {
uint32_t shift;
char *clc_name;
};
struct cam_vfe_top_ver4_hw_info { struct cam_vfe_top_ver4_hw_info {
struct cam_vfe_top_ver4_reg_offset_common *common_reg; struct cam_vfe_top_ver4_reg_offset_common *common_reg;
struct cam_vfe_ver4_path_hw_info vfe_full_hw_info; struct cam_vfe_ver4_path_hw_info vfe_full_hw_info;
struct cam_vfe_ver4_path_hw_info pdlib_hw_info; struct cam_vfe_ver4_path_hw_info pdlib_hw_info;
struct cam_vfe_ver4_path_hw_info *rdi_hw_info[ struct cam_vfe_ver4_path_hw_info *rdi_hw_info[CAM_VFE_RDI_VER2_MAX];
CAM_VFE_RDI_VER2_MAX];
struct cam_vfe_ver4_path_reg_data *reg_data; struct cam_vfe_ver4_path_reg_data *reg_data;
struct cam_vfe_top_ver4_wr_client_desc *wr_client_desc; struct cam_vfe_top_ver4_wr_client_desc *wr_client_desc;
struct cam_vfe_top_ver4_module_desc *ipp_module_desc; struct cam_vfe_top_ver4_module_desc *ipp_module_desc;
uint32_t num_reg; uint32_t num_reg;
struct cam_vfe_top_ver4_debug_reg_info (*debug_reg_info)[][8];
uint32_t num_mux; uint32_t num_mux;
uint32_t num_path_port_map; uint32_t num_path_port_map;
uint32_t mux_type[CAM_VFE_TOP_MUX_MAX]; uint32_t mux_type[CAM_VFE_TOP_MUX_MAX];
@@ -141,4 +145,18 @@ int cam_vfe_top_ver4_init(struct cam_hw_soc_info *soc_info,
int cam_vfe_top_ver4_deinit(struct cam_vfe_top **vfe_top); int cam_vfe_top_ver4_deinit(struct cam_vfe_top **vfe_top);
#define VFE_DBG_INFO(shift_val, name) {.shift = shift_val, .clc_name = name}
#define VFE_DBG_INFO_ARRAY_4bit(name1, name2, name3, name4, name5, name6, name7, name8) \
{ \
VFE_DBG_INFO(0, name1), \
VFE_DBG_INFO(4, name2), \
VFE_DBG_INFO(8, name3), \
VFE_DBG_INFO(12, name4), \
VFE_DBG_INFO(16, name5), \
VFE_DBG_INFO(20, name6), \
VFE_DBG_INFO(24, name7), \
VFE_DBG_INFO(28, name8), \
}
#endif /* _CAM_VFE_TOP_VER4_H_ */ #endif /* _CAM_VFE_TOP_VER4_H_ */

2
drivers/cam_utils/cam_debug_util.h
View File

@@ -317,6 +317,8 @@ void cam_print_to_buffer(char *buf, const size_t buf_size, size_t *len, unsigned
#define CAM_INFO_BUF(module_id, buf, buf_size, len, fmt, args...) \ #define CAM_INFO_BUF(module_id, buf, buf_size, len, fmt, args...) \
cam_print_to_buffer(buf, buf_size, len, CAM_TYPE_INFO, module_id, fmt, ##args) cam_print_to_buffer(buf, buf_size, len, CAM_TYPE_INFO, module_id, fmt, ##args)
#define CAM_BOOL_TO_YESNO(val) ((val) ? "Y" : "N")
/** /**
* struct cam_cpas_debug_settings - Sysfs debug settings for cpas driver * struct cam_cpas_debug_settings - Sysfs debug settings for cpas driver
*/ */