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qcacmn: Use function to attach HAL TX/RX ops

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Assign th HAL TX/RX ops in a function instead of assining a structure
directly. This can be later extended to have default ops for a family of
chips and then override that with chip specific ops.

This also helps the case where a new hal_soc->ops needs to be added.
The new 'op' will need to be added to only a default ops initializer
(with assumption that it applies to all chips).

Change-Id: Iefa23d14110fa5252444fad89737a3b2b2fbab6f
CRs-Fixed: 2891049
This commit is contained in:
Mohit Khanna
2021-02-04 05:25:37 -08:00
committed by Manjunathappa Prakash
parent 606c708af6
commit 4e6a7cf1bf
10 changed files with 1020 additions and 999 deletions
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14
hal/wifi3.0/hal_srng.c
View File

@@ -1399,6 +1399,12 @@ void *hal_attach(struct hif_opaque_softc *hif_handle, qdf_device_t qdf_dev)
qdf_spinlock_create(&hal->register_access_lock);
hal->register_window = 0;
hal->target_type = hal_get_target_type(hal_soc_to_hal_soc_handle(hal));
hal->ops = qdf_mem_malloc(sizeof(*hal->ops));
if (!hal->ops) {
hal_err("unable to allocable memory for HAL ops");
goto fail3;
}
hal_target_based_configure(hal);
@@ -1411,7 +1417,12 @@ void *hal_attach(struct hif_opaque_softc *hif_handle, qdf_device_t qdf_dev)
hal_delayed_tcl_reg_write_init(hal);
return (void *)hal;
fail3:
qdf_mem_free_consistent(qdf_dev, qdf_dev->dev,
sizeof(*hal->shadow_wrptr_mem_vaddr) *
HAL_MAX_LMAC_RINGS,
hal->shadow_wrptr_mem_vaddr,
hal->shadow_wrptr_mem_paddr, 0);
fail2:
qdf_mem_free_consistent(qdf_dev, qdf_dev->dev,
sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX,
@@ -1460,6 +1471,7 @@ extern void hal_detach(void *hal_soc)
hal_delayed_reg_write_deinit(hal);
hal_delayed_tcl_reg_write_deinit(hal);
qdf_mem_free(hal->ops);
qdf_mem_free_consistent(hal->qdf_dev, hal->qdf_dev->dev,
sizeof(*(hal->shadow_rdptr_mem_vaddr)) * HAL_SRNG_ID_MAX,

220
hal/wifi3.0/qca5018/hal_5018.c
View File

@@ -1650,128 +1650,128 @@ hal_rx_flow_setup_fse_5018(uint8_t *rx_fst, uint32_t table_offset,
return fse;
}
struct hal_hw_txrx_ops qca5018_hal_hw_txrx_ops = {
static void hal_hw_txrx_ops_attach_qca5018(struct hal_soc *hal_soc)
{
/* init and setup */
.hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic,
.hal_srng_src_hw_init = hal_srng_src_hw_init_generic,
.hal_get_hw_hptp = hal_get_hw_hptp_generic,
.hal_reo_setup = hal_reo_setup_generic,
.hal_setup_link_idle_list = hal_setup_link_idle_list_generic,
.hal_get_window_address = hal_get_window_address_5018,
hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic;
hal_soc->ops->hal_setup_link_idle_list = hal_setup_link_idle_list_generic;
hal_soc->ops->hal_get_window_address = hal_get_window_address_5018;
/* tx */
.hal_tx_desc_set_dscp_tid_table_id =
hal_tx_desc_set_dscp_tid_table_id_5018,
.hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_5018,
.hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_5018,
.hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_5018,
.hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic,
.hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic,
.hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic,
.hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic,
.hal_tx_comp_get_status = hal_tx_comp_get_status_generic,
.hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic,
.hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic,
.hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_5018,
.hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_5018,
hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
hal_tx_desc_set_dscp_tid_table_id_5018;
hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_5018;
hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_5018;
hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_5018;
hal_soc->ops->hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic;
hal_soc->ops->hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic;
hal_soc->ops->hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic;
hal_soc->ops->hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic;
hal_soc->ops->hal_tx_comp_get_status = hal_tx_comp_get_status_generic;
hal_soc->ops->hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic;
hal_soc->ops->hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic;
hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_5018;
hal_soc->ops->hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_5018;
/* rx */
.hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_5018,
.hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_5018,
.hal_rx_get_tlv = hal_rx_get_tlv_5018,
.hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_5018,
.hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_5018,
.hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_5018,
.hal_get_link_desc_size = hal_get_link_desc_size_5018,
.hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_5018,
.hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_5018,
.hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_5018,
.hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_5018,
.hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_5018,
.hal_reo_status_get_header = hal_reo_status_get_header_5018,
.hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic,
.hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic,
.hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic,
hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_5018;
hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_5018;
hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_5018;
hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_5018;
hal_soc->ops->hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_5018;
hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_5018;
hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_5018;
hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_5018;
hal_soc->ops->hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_5018;
hal_soc->ops->hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_5018;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_5018;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_5018;
hal_soc->ops->hal_reo_status_get_header = hal_reo_status_get_header_5018;
hal_soc->ops->hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic;
hal_soc->ops->hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic;
.hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic,
.hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic,
.hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic,
.hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_5018,
.hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_5018,
.hal_rx_msdu_end_sa_is_valid_get = hal_rx_msdu_end_sa_is_valid_get_5018,
.hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_5018,
.hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_5018,
.hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_5018,
.hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_5018,
.hal_rx_print_pn = hal_rx_print_pn_5018,
.hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_5018,
.hal_rx_msdu_end_da_is_valid_get = hal_rx_msdu_end_da_is_valid_get_5018,
.hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_5018,
.hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_5018,
.hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_5018,
.hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_5018,
.hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_5018,
.hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_5018,
.hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_5018,
.hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_5018,
.hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_5018,
.hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_5018,
.hal_rx_get_mpdu_sequence_control_valid =
hal_rx_get_mpdu_sequence_control_valid_5018,
.hal_rx_is_unicast = hal_rx_is_unicast_5018,
.hal_rx_tid_get = hal_rx_tid_get_5018,
.hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_5018,
.hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018,
.hal_rx_msdu_end_sa_sw_peer_id_get =
hal_rx_msdu_end_sa_sw_peer_id_get_5018,
.hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_5018,
.hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_5018,
.hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_5018,
.hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_5018,
.hal_rx_get_fc_valid = hal_rx_get_fc_valid_5018,
.hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_5018,
.hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_5018,
.hal_rx_get_filter_category = hal_rx_get_filter_category_5018,
.hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_5018,
.hal_reo_config = hal_reo_config_5018,
.hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_5018,
.hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_5018,
.hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_5018,
.hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_5018,
.hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_5018,
.hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_5018,
.hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_5018,
.hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_5018,
hal_soc->ops->hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic;
hal_soc->ops->hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic;
hal_soc->ops->hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic;
hal_soc->ops->hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_5018;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_5018;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = hal_rx_msdu_end_sa_is_valid_get_5018;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_5018;
hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_5018;
hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_5018;
hal_soc->ops->hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_5018;
hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_5018;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_5018;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = hal_rx_msdu_end_da_is_valid_get_5018;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_5018;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_5018;
hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_5018;
hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_5018;
hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_5018;
hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_5018;
hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_5018;
hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_5018;
hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_5018;
hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_5018;
hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
hal_rx_get_mpdu_sequence_control_valid_5018;
hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_5018;
hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_5018;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_5018;
hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018;
hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
hal_rx_msdu_end_sa_sw_peer_id_get_5018;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_5018;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_5018;
hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_5018;
hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_5018;
hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_5018;
hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_5018;
hal_soc->ops->hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_5018;
hal_soc->ops->hal_rx_get_filter_category = hal_rx_get_filter_category_5018;
hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_5018;
hal_soc->ops->hal_reo_config = hal_reo_config_5018;
hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_5018;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_5018;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_5018;
hal_soc->ops->hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_5018;
hal_soc->ops->hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_5018;
hal_soc->ops->hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_5018;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_5018;
hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_5018;
#if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
.hal_rx_get_bb_info = hal_rx_get_bb_info_5018,
.hal_rx_get_rtt_info = hal_rx_get_rtt_info_5018,
hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_5018;
hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_5018;
#endif
/* rx - msdu fast path info fields */
.hal_rx_msdu_packet_metadata_get = hal_rx_msdu_packet_metadata_get_5018,
.hal_rx_mpdu_start_tlv_tag_valid = hal_rx_mpdu_start_tlv_tag_valid_5018,
.hal_rx_wbm_err_msdu_continuation_get =
hal_rx_wbm_err_msdu_continuation_get_5018,
hal_soc->ops->hal_rx_msdu_packet_metadata_get = hal_rx_msdu_packet_metadata_get_5018;
hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = hal_rx_mpdu_start_tlv_tag_valid_5018;
hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get =
hal_rx_wbm_err_msdu_continuation_get_5018;
/* rx - TLV struct offsets */
.hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic,
.hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic,
.hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic,
.hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic,
.hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic,
hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic;
#ifndef NO_RX_PKT_HDR_TLV
.hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic,
hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic;
#endif
.hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_5018,
.hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_5018,
hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_5018;
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_5018;
};
struct hal_hw_srng_config hw_srng_table_5018[] = {
@@ -2226,5 +2226,5 @@ void hal_qca5018_attach(struct hal_soc *hal_soc)
{
hal_soc->hw_srng_table = hw_srng_table_5018;
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca5018;
hal_soc->ops = &qca5018_hal_hw_txrx_ops;
hal_hw_txrx_ops_attach_qca5018(hal_soc);
}

209
hal/wifi3.0/qca6290/hal_6290.c
View File

@@ -1038,119 +1038,120 @@ void hal_compute_reo_remap_ix2_ix3_6290(uint32_t *ring, uint32_t num_rings,
}
}
struct hal_hw_txrx_ops qca6290_hal_hw_txrx_ops = {
static void hal_hw_txrx_ops_attach_6290(struct hal_soc *hal_soc)
{
/* init and setup */
.hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic,
.hal_srng_src_hw_init = hal_srng_src_hw_init_generic,
.hal_get_hw_hptp = hal_get_hw_hptp_generic,
.hal_reo_setup = hal_reo_setup_generic,
.hal_setup_link_idle_list = hal_setup_link_idle_list_generic,
.hal_get_window_address = hal_get_window_address_6290,
hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic;
hal_soc->ops->hal_setup_link_idle_list = hal_setup_link_idle_list_generic;
hal_soc->ops->hal_get_window_address = hal_get_window_address_6290;
/* tx */
.hal_tx_desc_set_dscp_tid_table_id =
hal_tx_desc_set_dscp_tid_table_id_6290,
.hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6290,
.hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6290,
.hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6290,
.hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic,
.hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic,
.hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic,
.hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic,
.hal_tx_comp_get_status = hal_tx_comp_get_status_generic,
.hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic,
.hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic,
.hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6290,
.hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_6290,
hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
hal_tx_desc_set_dscp_tid_table_id_6290;
hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6290;
hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6290;
hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6290;
hal_soc->ops->hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic;
hal_soc->ops->hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic;
hal_soc->ops->hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic;
hal_soc->ops->hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic;
hal_soc->ops->hal_tx_comp_get_status = hal_tx_comp_get_status_generic;
hal_soc->ops->hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic;
hal_soc->ops->hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic;
hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6290;
hal_soc->ops->hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_6290;
/* rx */
.hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_6290,
.hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_6290,
.hal_rx_get_tlv = hal_rx_get_tlv_6290,
.hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_6290,
.hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_6290,
.hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6290,
.hal_get_link_desc_size = hal_get_link_desc_size_6290,
.hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_6290,
.hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_6290,
.hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_6290,
.hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_6290,
.hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_6290,
.hal_reo_status_get_header = hal_reo_status_get_header_6290,
.hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic,
.hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic,
.hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic,
hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_6290;
hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_6290;
hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6290;
hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_6290;
hal_soc->ops->hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_6290;
hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6290;
hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6290;
hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_6290;
hal_soc->ops->hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_6290;
hal_soc->ops->hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_6290;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_6290;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_6290;
hal_soc->ops->hal_reo_status_get_header = hal_reo_status_get_header_6290;
hal_soc->ops->hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic;
hal_soc->ops->hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic;
.hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic,
.hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic,
.hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic,
.hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_6290,
.hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_6290,
.hal_rx_msdu_end_sa_is_valid_get = hal_rx_msdu_end_sa_is_valid_get_6290,
.hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_6290,
.hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_6290,
.hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_6290,
.hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_6290,
.hal_rx_print_pn = hal_rx_print_pn_6290,
.hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_6290,
.hal_rx_msdu_end_da_is_valid_get = hal_rx_msdu_end_da_is_valid_get_6290,
.hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_6290,
.hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_6290,
.hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_6290,
.hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6290,
.hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6290,
.hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_6290,
.hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6290,
.hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6290,
.hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6290,
.hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6290,
.hal_rx_get_mpdu_sequence_control_valid =
hal_rx_get_mpdu_sequence_control_valid_6290,
.hal_rx_is_unicast = hal_rx_is_unicast_6290,
.hal_rx_tid_get = hal_rx_tid_get_6290,
.hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_6290,
.hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290,
.hal_rx_msdu_end_sa_sw_peer_id_get =
hal_rx_msdu_end_sa_sw_peer_id_get_6290,
.hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_6290,
.hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_6290,
.hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6290,
.hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6290,
.hal_rx_get_fc_valid = hal_rx_get_fc_valid_6290,
.hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6290,
.hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_6290,
.hal_rx_get_filter_category = hal_rx_get_filter_category_6290,
.hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6290,
.hal_reo_config = hal_reo_config_6290,
.hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6290,
.hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_6290,
.hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_6290,
.hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_6290,
.hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_6290,
.hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_6290,
.hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_6290,
.hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6290,
hal_soc->ops->hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic;
hal_soc->ops->hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic;
hal_soc->ops->hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic;
hal_soc->ops->hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_6290;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_6290;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = hal_rx_msdu_end_sa_is_valid_get_6290;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_6290;
hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_6290;
hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_6290;
hal_soc->ops->hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_6290;
hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6290;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_6290;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = hal_rx_msdu_end_da_is_valid_get_6290;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_6290;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_6290;
hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_6290;
hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6290;
hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6290;
hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_6290;
hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6290;
hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6290;
hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6290;
hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6290;
hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
hal_rx_get_mpdu_sequence_control_valid_6290;
hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6290;
hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6290;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_6290;
hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_6290;
hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
hal_rx_msdu_end_sa_sw_peer_id_get_6290;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_6290;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_6290;
hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6290;
hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6290;
hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6290;
hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6290;
hal_soc->ops->hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_6290;
hal_soc->ops->hal_rx_get_filter_category = hal_rx_get_filter_category_6290;
hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6290;
hal_soc->ops->hal_reo_config = hal_reo_config_6290;
hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6290;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_6290;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_6290;
hal_soc->ops->hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_6290;
hal_soc->ops->hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_6290;
hal_soc->ops->hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_6290;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_6290;
hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6290;
/* rx - msdu end fast path info fields */
.hal_rx_msdu_packet_metadata_get =
hal_rx_msdu_packet_metadata_get_generic,
hal_soc->ops->hal_rx_msdu_packet_metadata_get =
hal_rx_msdu_packet_metadata_get_generic;
/* rx - TLV struct offsets */
.hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic,
.hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic,
.hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic,
.hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic,
.hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic,
hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic;
#ifndef NO_RX_PKT_HDR_TLV
.hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic,
hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic;
#endif
.hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_6290,
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_6290;
};
struct hal_hw_srng_config hw_srng_table_6290[] = {
@@ -1600,5 +1601,5 @@ void hal_qca6290_attach(struct hal_soc *hal_soc)
{
hal_soc->hw_srng_table = hw_srng_table_6290;
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6290;
hal_soc->ops = &qca6290_hal_hw_txrx_ops;
hal_hw_txrx_ops_attach_6290(hal_soc);
}

213
hal/wifi3.0/qca6390/hal_6390.c
View File

@@ -1090,122 +1090,123 @@ void hal_compute_reo_remap_ix2_ix3_6390(uint32_t *ring, uint32_t num_rings,
}
}
struct hal_hw_txrx_ops qca6390_hal_hw_txrx_ops = {
static void hal_hw_txrx_ops_attach_qca6390(struct hal_soc *hal_soc)
{
/* init and setup */
.hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic,
.hal_srng_src_hw_init = hal_srng_src_hw_init_generic,
.hal_get_hw_hptp = hal_get_hw_hptp_generic,
.hal_reo_setup = hal_reo_setup_generic,
.hal_setup_link_idle_list = hal_setup_link_idle_list_generic,
.hal_get_window_address = hal_get_window_address_6390,
.hal_reo_set_err_dst_remap = hal_reo_set_err_dst_remap_6390,
hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic;
hal_soc->ops->hal_setup_link_idle_list = hal_setup_link_idle_list_generic;
hal_soc->ops->hal_get_window_address = hal_get_window_address_6390;
hal_soc->ops->hal_reo_set_err_dst_remap = hal_reo_set_err_dst_remap_6390;
/* tx */
.hal_tx_desc_set_dscp_tid_table_id =
hal_tx_desc_set_dscp_tid_table_id_6390,
.hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6390,
.hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6390,
.hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6390,
.hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic,
.hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic,
.hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic,
.hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic,
.hal_tx_comp_get_status = hal_tx_comp_get_status_generic,
.hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic,
.hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic,
.hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6390,
.hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_6390,
hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
hal_tx_desc_set_dscp_tid_table_id_6390;
hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6390;
hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6390;
hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6390;
hal_soc->ops->hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic;
hal_soc->ops->hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic;
hal_soc->ops->hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic;
hal_soc->ops->hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic;
hal_soc->ops->hal_tx_comp_get_status = hal_tx_comp_get_status_generic;
hal_soc->ops->hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic;
hal_soc->ops->hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic;
hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6390;
hal_soc->ops->hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_6390;
/* rx */
.hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_6390,
.hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_6390,
.hal_rx_get_tlv = hal_rx_get_tlv_6390,
.hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_6390,
.hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_6390,
.hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6390,
.hal_get_link_desc_size = hal_get_link_desc_size_6390,
.hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_6390,
.hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_6390,
.hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_6390,
.hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_6390,
.hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_6390,
.hal_reo_status_get_header = hal_reo_status_get_header_6390,
.hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic,
.hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic,
.hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic,
hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_6390;
hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_6390;
hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6390;
hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_6390;
hal_soc->ops->hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_6390;
hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6390;
hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6390;
hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_6390;
hal_soc->ops->hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_6390;
hal_soc->ops->hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_6390;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_6390;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_6390;
hal_soc->ops->hal_reo_status_get_header = hal_reo_status_get_header_6390;
hal_soc->ops->hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic;
hal_soc->ops->hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic;
.hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic,
.hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic,
.hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic,
.hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_6390,
.hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_6390,
.hal_rx_msdu_end_sa_is_valid_get = hal_rx_msdu_end_sa_is_valid_get_6390,
.hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_6390,
.hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_6390,
.hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_6390,
.hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_6390,
.hal_rx_print_pn = hal_rx_print_pn_6390,
.hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_6390,
.hal_rx_msdu_end_da_is_valid_get = hal_rx_msdu_end_da_is_valid_get_6390,
.hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_6390,
.hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_6390,
.hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_6390,
.hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6390,
.hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6390,
.hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_6390,
.hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6390,
.hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6390,
.hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6390,
.hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6390,
.hal_rx_get_mpdu_sequence_control_valid =
hal_rx_get_mpdu_sequence_control_valid_6390,
.hal_rx_is_unicast = hal_rx_is_unicast_6390,
.hal_rx_tid_get = hal_rx_tid_get_6390,
.hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_6390,
.hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390,
.hal_rx_msdu_end_sa_sw_peer_id_get =
hal_rx_msdu_end_sa_sw_peer_id_get_6390,
.hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_6390,
.hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_6390,
.hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6390,
.hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6390,
.hal_rx_get_fc_valid = hal_rx_get_fc_valid_6390,
.hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6390,
.hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_6390,
.hal_rx_get_filter_category = hal_rx_get_filter_category_6390,
.hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6390,
.hal_reo_config = hal_reo_config_6390,
.hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6390,
.hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_6390,
.hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_6390,
.hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_6390,
.hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_6390,
.hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_6390,
.hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_6390,
.hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6390,
hal_soc->ops->hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic;
hal_soc->ops->hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic;
hal_soc->ops->hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic;
hal_soc->ops->hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_6390;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_6390;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = hal_rx_msdu_end_sa_is_valid_get_6390;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_6390;
hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_6390;
hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_6390;
hal_soc->ops->hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_6390;
hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6390;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_6390;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = hal_rx_msdu_end_da_is_valid_get_6390;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_6390;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_6390;
hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_6390;
hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6390;
hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6390;
hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_6390;
hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6390;
hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6390;
hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6390;
hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6390;
hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
hal_rx_get_mpdu_sequence_control_valid_6390;
hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6390;
hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6390;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_6390;
hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_6390;
hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
hal_rx_msdu_end_sa_sw_peer_id_get_6390;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_6390;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_6390;
hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6390;
hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6390;
hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6390;
hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6390;
hal_soc->ops->hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_6390;
hal_soc->ops->hal_rx_get_filter_category = hal_rx_get_filter_category_6390;
hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6390;
hal_soc->ops->hal_reo_config = hal_reo_config_6390;
hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6390;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_6390;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_6390;
hal_soc->ops->hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_6390;
hal_soc->ops->hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_6390;
hal_soc->ops->hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_6390;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_6390;
hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6390;
/* rx - msdu end fast path info fields */
.hal_rx_msdu_packet_metadata_get =
hal_rx_msdu_packet_metadata_get_generic,
.hal_rx_mpdu_start_tlv_tag_valid = hal_rx_mpdu_start_tlv_tag_valid_6390,
hal_soc->ops->hal_rx_msdu_packet_metadata_get =
hal_rx_msdu_packet_metadata_get_generic;
hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = hal_rx_mpdu_start_tlv_tag_valid_6390;
/* rx - TLV struct offsets */
.hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic,
.hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic,
.hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic,
.hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic,
.hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic,
hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic;
#ifndef NO_RX_PKT_HDR_TLV
.hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic,
hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic;
#endif
.hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_6390,
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_6390;
};
struct hal_hw_srng_config hw_srng_table_6390[] = {
@@ -1667,5 +1668,5 @@ void hal_qca6390_attach(struct hal_soc *hal_soc)
{
hal_soc->hw_srng_table = hw_srng_table_6390;
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6390;
hal_soc->ops = &qca6390_hal_hw_txrx_ops;
hal_hw_txrx_ops_attach_qca6390(hal_soc);
}

239
hal/wifi3.0/qca6490/hal_6490.c
View File

@@ -1666,138 +1666,139 @@ void hal_compute_reo_remap_ix2_ix3_6490(uint32_t *ring, uint32_t num_rings,
}
}
struct hal_hw_txrx_ops qca6490_hal_hw_txrx_ops = {
static void hal_hw_txrx_ops_attach_qca6490(struct hal_soc *hal_soc)
{
/* init and setup */
.hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic,
.hal_srng_src_hw_init = hal_srng_src_hw_init_generic,
.hal_get_hw_hptp = hal_get_hw_hptp_generic,
.hal_reo_setup = hal_reo_setup_generic,
.hal_setup_link_idle_list = hal_setup_link_idle_list_generic,
.hal_get_window_address = hal_get_window_address_6490,
.hal_reo_set_err_dst_remap = hal_reo_set_err_dst_remap_6490,
hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic;
hal_soc->ops->hal_setup_link_idle_list = hal_setup_link_idle_list_generic;
hal_soc->ops->hal_get_window_address = hal_get_window_address_6490;
hal_soc->ops->hal_reo_set_err_dst_remap = hal_reo_set_err_dst_remap_6490;
/* tx */
.hal_tx_desc_set_dscp_tid_table_id =
hal_tx_desc_set_dscp_tid_table_id_6490,
.hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6490,
.hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6490,
.hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6490,
.hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic,
.hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic,
.hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic,
.hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic,
.hal_tx_comp_get_status = hal_tx_comp_get_status_generic,
.hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic,
.hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic,
.hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6490,
.hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_6490,
hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
hal_tx_desc_set_dscp_tid_table_id_6490;
hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6490;
hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6490;
hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6490;
hal_soc->ops->hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic;
hal_soc->ops->hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic;
hal_soc->ops->hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic;
hal_soc->ops->hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic;
hal_soc->ops->hal_tx_comp_get_status = hal_tx_comp_get_status_generic;
hal_soc->ops->hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic;
hal_soc->ops->hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic;
hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6490;
hal_soc->ops->hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_6490;
/* rx */
.hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_6490,
.hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_6490,
.hal_rx_get_tlv = hal_rx_get_tlv_6490,
.hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_6490,
.hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_6490,
.hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6490,
.hal_get_link_desc_size = hal_get_link_desc_size_6490,
.hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_6490,
.hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_6490,
.hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_6490,
.hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_6490,
.hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_6490,
.hal_reo_status_get_header = hal_reo_status_get_header_6490,
.hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic,
.hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic,
.hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic,
hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_6490;
hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_6490;
hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6490;
hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_6490;
hal_soc->ops->hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_6490;
hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6490;
hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6490;
hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_6490;
hal_soc->ops->hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_6490;
hal_soc->ops->hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_6490;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_6490;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_6490;
hal_soc->ops->hal_reo_status_get_header = hal_reo_status_get_header_6490;
hal_soc->ops->hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic;
hal_soc->ops->hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic;
.hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic,
.hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic,
.hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic,
.hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_6490,
.hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_6490,
.hal_rx_msdu_end_sa_is_valid_get =
hal_rx_msdu_end_sa_is_valid_get_6490,
.hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_6490,
.hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_6490,
.hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_6490,
.hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_6490,
.hal_rx_print_pn = hal_rx_print_pn_6490,
.hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_6490,
.hal_rx_msdu_end_da_is_valid_get =
hal_rx_msdu_end_da_is_valid_get_6490,
.hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_6490,
.hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_6490,
.hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_6490,
.hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6490,
.hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6490,
.hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_6490,
.hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6490,
.hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6490,
.hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6490,
.hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6490,
.hal_rx_get_mpdu_sequence_control_valid =
hal_rx_get_mpdu_sequence_control_valid_6490,
.hal_rx_is_unicast = hal_rx_is_unicast_6490,
.hal_rx_tid_get = hal_rx_tid_get_6490,
.hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_6490,
.hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_6490,
.hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_6490,
.hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6490,
.hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6490,
.hal_rx_get_fc_valid = hal_rx_get_fc_valid_6490,
.hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6490,
.hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_6490,
.hal_rx_get_filter_category = hal_rx_get_filter_category_6490,
.hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6490,
.hal_reo_config = hal_reo_config_6490,
.hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6490,
.hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_6490,
.hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_6490,
.hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_6490,
.hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_6490,
.hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_6490,
.hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_6490,
.hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6490,
hal_soc->ops->hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic;
hal_soc->ops->hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic;
hal_soc->ops->hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic;
hal_soc->ops->hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_6490;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_6490;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
hal_rx_msdu_end_sa_is_valid_get_6490;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_6490;
hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_6490;
hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_6490;
hal_soc->ops->hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_6490;
hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6490;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_6490;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
hal_rx_msdu_end_da_is_valid_get_6490;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_6490;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_6490;
hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_6490;
hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6490;
hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6490;
hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_6490;
hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6490;
hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6490;
hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6490;
hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6490;
hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
hal_rx_get_mpdu_sequence_control_valid_6490;
hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6490;
hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6490;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_6490;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_6490;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_6490;
hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6490;
hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6490;
hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6490;
hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6490;
hal_soc->ops->hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_6490;
hal_soc->ops->hal_rx_get_filter_category = hal_rx_get_filter_category_6490;
hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6490;
hal_soc->ops->hal_reo_config = hal_reo_config_6490;
hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6490;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_6490;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_6490;
hal_soc->ops->hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_6490;
hal_soc->ops->hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_6490;
hal_soc->ops->hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_6490;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_6490;
hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6490;
#if defined(QCA_WIFI_QCA6490) && defined(WLAN_CFR_ENABLE) && \
defined(WLAN_ENH_CFR_ENABLE)
.hal_rx_get_bb_info = hal_rx_get_bb_info_6490,
.hal_rx_get_rtt_info = hal_rx_get_rtt_info_6490,
hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_6490;
hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_6490;
#endif
/* rx - msdu end fast path info fields */
.hal_rx_msdu_packet_metadata_get =
hal_rx_msdu_packet_metadata_get_generic,
.hal_rx_get_fisa_cumulative_l4_checksum =
hal_rx_get_fisa_cumulative_l4_checksum_6490,
.hal_rx_get_fisa_cumulative_ip_length =
hal_rx_get_fisa_cumulative_ip_length_6490,
.hal_rx_get_udp_proto = hal_rx_get_udp_proto_6490,
.hal_rx_get_fisa_flow_agg_continuation =
hal_rx_get_flow_agg_continuation_6490,
.hal_rx_get_fisa_flow_agg_count = hal_rx_get_flow_agg_count_6490,
.hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_6490,
.hal_rx_mpdu_start_tlv_tag_valid =
hal_rx_mpdu_start_tlv_tag_valid_6490,
hal_soc->ops->hal_rx_msdu_packet_metadata_get =
hal_rx_msdu_packet_metadata_get_generic;
hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum =
hal_rx_get_fisa_cumulative_l4_checksum_6490;
hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length =
hal_rx_get_fisa_cumulative_ip_length_6490;
hal_soc->ops->hal_rx_get_udp_proto = hal_rx_get_udp_proto_6490;
hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation =
hal_rx_get_flow_agg_continuation_6490;
hal_soc->ops->hal_rx_get_fisa_flow_agg_count = hal_rx_get_flow_agg_count_6490;
hal_soc->ops->hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_6490;
hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
hal_rx_mpdu_start_tlv_tag_valid_6490;
/* rx - TLV struct offsets */
.hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic,
.hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic,
.hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic,
.hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic,
.hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic,
hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic;
#ifndef NO_RX_PKT_HDR_TLV
.hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic,
hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic;
#endif
.hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6490,
.hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_6490,
.hal_rx_msdu_get_reo_destination_indication =
hal_rx_msdu_get_reo_destination_indication_6490,
hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6490;
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_6490;
hal_soc->ops->hal_rx_msdu_get_reo_destination_indication =
hal_rx_msdu_get_reo_destination_indication_6490;
};
struct hal_hw_srng_config hw_srng_table_6490[] = {
@@ -2259,5 +2260,5 @@ void hal_qca6490_attach(struct hal_soc *hal_soc)
{
hal_soc->hw_srng_table = hw_srng_table_6490;
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6490;
hal_soc->ops = &qca6490_hal_hw_txrx_ops;
hal_hw_txrx_ops_attach_qca6490(hal_soc);
}

239
hal/wifi3.0/qca6750/hal_6750.c
View File

@@ -1824,140 +1824,141 @@ void hal_compute_reo_remap_ix2_ix3_6750(uint32_t *ring, uint32_t num_rings,
}
}
struct hal_hw_txrx_ops qca6750_hal_hw_txrx_ops = {
static void hal_hw_txrx_ops_attach_qca6750(struct hal_soc *hal_soc)
{
/* init and setup */
.hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic,
.hal_srng_src_hw_init = hal_srng_src_hw_init_generic,
.hal_get_hw_hptp = hal_get_hw_hptp_generic,
.hal_reo_setup = hal_reo_setup_generic,
.hal_setup_link_idle_list = hal_setup_link_idle_list_generic,
.hal_get_window_address = hal_get_window_address_6750,
.hal_reo_set_err_dst_remap = hal_reo_set_err_dst_remap_6750,
hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic;
hal_soc->ops->hal_setup_link_idle_list = hal_setup_link_idle_list_generic;
hal_soc->ops->hal_get_window_address = hal_get_window_address_6750;
hal_soc->ops->hal_reo_set_err_dst_remap = hal_reo_set_err_dst_remap_6750;
/* tx */
.hal_tx_desc_set_dscp_tid_table_id =
hal_tx_desc_set_dscp_tid_table_id_6750,
.hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6750,
.hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6750,
.hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6750,
.hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic,
.hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic,
.hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic,
.hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic,
.hal_tx_comp_get_status = hal_tx_comp_get_status_generic,
.hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic,
.hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic,
.hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6750,
.hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_6750,
hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
hal_tx_desc_set_dscp_tid_table_id_6750;
hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6750;
hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6750;
hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6750;
hal_soc->ops->hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic;
hal_soc->ops->hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic;
hal_soc->ops->hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic;
hal_soc->ops->hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic;
hal_soc->ops->hal_tx_comp_get_status = hal_tx_comp_get_status_generic;
hal_soc->ops->hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic;
hal_soc->ops->hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic;
hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6750;
hal_soc->ops->hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_6750;
/* rx */
.hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_6750,
.hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_6750,
.hal_rx_get_tlv = hal_rx_get_tlv_6750,
.hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_6750,
.hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_6750,
.hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6750,
.hal_get_link_desc_size = hal_get_link_desc_size_6750,
.hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_6750,
.hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_6750,
.hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_6750,
.hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_6750,
.hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_6750,
.hal_reo_status_get_header = hal_reo_status_get_header_6750,
.hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic,
.hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic,
.hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic,
hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_6750;
hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_6750;
hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6750;
hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_6750;
hal_soc->ops->hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_6750;
hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6750;
hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6750;
hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_6750;
hal_soc->ops->hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_6750;
hal_soc->ops->hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_6750;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_6750;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_6750;
hal_soc->ops->hal_reo_status_get_header = hal_reo_status_get_header_6750;
hal_soc->ops->hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic;
hal_soc->ops->hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic;
.hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic,
.hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic,
.hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic,
.hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_6750,
.hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_6750,
.hal_rx_msdu_end_sa_is_valid_get = hal_rx_msdu_end_sa_is_valid_get_6750,
.hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_6750,
.hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_6750,
.hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_6750,
.hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_6750,
.hal_rx_print_pn = hal_rx_print_pn_6750,
.hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_6750,
.hal_rx_msdu_end_da_is_valid_get = hal_rx_msdu_end_da_is_valid_get_6750,
.hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_6750,
.hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_6750,
.hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_6750,
.hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6750,
.hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6750,
.hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_6750,
.hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6750,
.hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6750,
.hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6750,
.hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6750,
.hal_rx_get_mpdu_sequence_control_valid =
hal_rx_get_mpdu_sequence_control_valid_6750,
.hal_rx_is_unicast = hal_rx_is_unicast_6750,
.hal_rx_tid_get = hal_rx_tid_get_6750,
.hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_6750,
.hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_6750,
.hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_6750,
.hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6750,
.hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6750,
.hal_rx_get_fc_valid = hal_rx_get_fc_valid_6750,
.hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6750,
.hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_6750,
.hal_rx_get_filter_category = hal_rx_get_filter_category_6750,
.hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6750,
.hal_reo_config = hal_reo_config_6750,
.hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6750,
.hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_6750,
.hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_6750,
.hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_6750,
.hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_6750,
.hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_6750,
.hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_6750,
.hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6750,
hal_soc->ops->hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic;
hal_soc->ops->hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic;
hal_soc->ops->hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic;
hal_soc->ops->hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_6750;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_6750;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = hal_rx_msdu_end_sa_is_valid_get_6750;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_6750;
hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_6750;
hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_6750;
hal_soc->ops->hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_6750;
hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6750;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_6750;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = hal_rx_msdu_end_da_is_valid_get_6750;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_6750;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_6750;
hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_6750;
hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6750;
hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6750;
hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_6750;
hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6750;
hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6750;
hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6750;
hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6750;
hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
hal_rx_get_mpdu_sequence_control_valid_6750;
hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6750;
hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6750;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_6750;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_6750;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_6750;
hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6750;
hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6750;
hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6750;
hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6750;
hal_soc->ops->hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_6750;
hal_soc->ops->hal_rx_get_filter_category = hal_rx_get_filter_category_6750;
hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6750;
hal_soc->ops->hal_reo_config = hal_reo_config_6750;
hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6750;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_6750;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_6750;
hal_soc->ops->hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_6750;
hal_soc->ops->hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_6750;
hal_soc->ops->hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_6750;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_6750;
hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6750;
#if defined(QCA_WIFI_QCA6750) && defined(WLAN_CFR_ENABLE) && \
defined(WLAN_ENH_CFR_ENABLE)
.hal_rx_get_bb_info = hal_rx_get_bb_info_6750,
.hal_rx_get_rtt_info = hal_rx_get_rtt_info_6750,
hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_6750;
hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_6750;
#endif
/* rx - msdu end fast path info fields */
.hal_rx_msdu_packet_metadata_get =
hal_rx_msdu_packet_metadata_get_generic,
.hal_rx_get_fisa_cumulative_l4_checksum =
hal_rx_get_fisa_cumulative_l4_checksum_6750,
.hal_rx_get_fisa_cumulative_ip_length =
hal_rx_get_fisa_cumulative_ip_length_6750,
.hal_rx_get_udp_proto = hal_rx_get_udp_proto_6750,
.hal_rx_get_fisa_flow_agg_continuation =
hal_rx_get_flow_agg_continuation_6750,
.hal_rx_get_fisa_flow_agg_count = hal_rx_get_flow_agg_count_6750,
.hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_6750,
.hal_rx_mpdu_start_tlv_tag_valid = hal_rx_mpdu_start_tlv_tag_valid_6750,
hal_soc->ops->hal_rx_msdu_packet_metadata_get =
hal_rx_msdu_packet_metadata_get_generic;
hal_soc->ops->hal_rx_get_fisa_cumulative_l4_checksum =
hal_rx_get_fisa_cumulative_l4_checksum_6750;
hal_soc->ops->hal_rx_get_fisa_cumulative_ip_length =
hal_rx_get_fisa_cumulative_ip_length_6750;
hal_soc->ops->hal_rx_get_udp_proto = hal_rx_get_udp_proto_6750;
hal_soc->ops->hal_rx_get_fisa_flow_agg_continuation =
hal_rx_get_flow_agg_continuation_6750;
hal_soc->ops->hal_rx_get_fisa_flow_agg_count = hal_rx_get_flow_agg_count_6750;
hal_soc->ops->hal_rx_get_fisa_timeout = hal_rx_get_fisa_timeout_6750;
hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = hal_rx_mpdu_start_tlv_tag_valid_6750;
/* rx - TLV struct offsets */
.hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic,
.hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic,
.hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic,
.hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic,
.hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic,
hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic;
#ifndef NO_RX_PKT_HDR_TLV
.hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic,
hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic;
#endif
.hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6750,
.hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_6750,
hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6750;
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_6750;
/* CMEM FSE */
.hal_rx_flow_setup_cmem_fse = hal_rx_flow_setup_cmem_fse_6750,
.hal_rx_flow_get_cmem_fse_ts = hal_rx_flow_get_cmem_fse_ts_6750,
.hal_rx_flow_get_cmem_fse = hal_rx_flow_get_cmem_fse_6750,
.hal_rx_msdu_get_reo_destination_indication =
hal_rx_msdu_get_reo_destination_indication_6750,
hal_soc->ops->hal_rx_flow_setup_cmem_fse = hal_rx_flow_setup_cmem_fse_6750;
hal_soc->ops->hal_rx_flow_get_cmem_fse_ts = hal_rx_flow_get_cmem_fse_ts_6750;
hal_soc->ops->hal_rx_flow_get_cmem_fse = hal_rx_flow_get_cmem_fse_6750;
hal_soc->ops->hal_rx_msdu_get_reo_destination_indication =
hal_rx_msdu_get_reo_destination_indication_6750;
};
struct hal_hw_srng_config hw_srng_table_6750[] = {
@@ -2409,5 +2410,5 @@ void hal_qca6750_attach(struct hal_soc *hal_soc)
{
hal_soc->hw_srng_table = hw_srng_table_6750;
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca6750;
hal_soc->ops = &qca6750_hal_hw_txrx_ops;
hal_hw_txrx_ops_attach_qca6750(hal_soc);
}

219
hal/wifi3.0/qca8074v1/hal_8074v1.c
View File

@@ -1212,126 +1212,127 @@ void hal_compute_reo_remap_ix2_ix3_8074v1(uint32_t *ring, uint32_t num_rings,
}
}
struct hal_hw_txrx_ops qca8074_hal_hw_txrx_ops = {
static void hal_hw_txrx_ops_attach_qca8074(struct hal_soc *hal_soc)
{
/* init and setup */
.hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic,
.hal_srng_src_hw_init = hal_srng_src_hw_init_generic,
.hal_get_hw_hptp = hal_get_hw_hptp_generic,
.hal_reo_setup = hal_reo_setup_generic,
.hal_setup_link_idle_list = hal_setup_link_idle_list_generic,
.hal_get_window_address = hal_get_window_address_8074,
hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic;
hal_soc->ops->hal_setup_link_idle_list = hal_setup_link_idle_list_generic;
hal_soc->ops->hal_get_window_address = hal_get_window_address_8074;
/* tx */
.hal_tx_desc_set_dscp_tid_table_id =
hal_tx_desc_set_dscp_tid_table_id_8074,
.hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_8074,
.hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_8074,
.hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_8074,
.hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic,
.hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic,
.hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic,
.hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic,
.hal_tx_comp_get_status = hal_tx_comp_get_status_generic,
.hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic,
.hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic,
.hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_8074v1,
.hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_8074v1,
hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
hal_tx_desc_set_dscp_tid_table_id_8074;
hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_8074;
hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_8074;
hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_8074;
hal_soc->ops->hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic;
hal_soc->ops->hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic;
hal_soc->ops->hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic;
hal_soc->ops->hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic;
hal_soc->ops->hal_tx_comp_get_status = hal_tx_comp_get_status_generic;
hal_soc->ops->hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic;
hal_soc->ops->hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic;
hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_8074v1;
hal_soc->ops->hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_8074v1;
/* rx */
.hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_8074,
.hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_8074,
.hal_rx_get_tlv = hal_rx_get_tlv_8074,
.hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_8074,
.hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_8074,
.hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_8074,
.hal_get_link_desc_size = hal_get_link_desc_size_8074,
.hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_8074,
.hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_8074,
.hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_8074,
.hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_8074v1,
.hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_8074v1,
.hal_reo_status_get_header = hal_reo_status_get_header_8074v1,
.hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic,
.hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic,
.hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic,
hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_8074;
hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_8074;
hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_8074;
hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_8074;
hal_soc->ops->hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_8074;
hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_8074;
hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_8074;
hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_8074;
hal_soc->ops->hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_8074;
hal_soc->ops->hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_8074;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_8074v1;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_8074v1;
hal_soc->ops->hal_reo_status_get_header = hal_reo_status_get_header_8074v1;
hal_soc->ops->hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic;
hal_soc->ops->hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic;
.hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic,
.hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic,
.hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic,
.hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_8074v1,
.hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_8074v1,
.hal_rx_msdu_end_sa_is_valid_get =
hal_rx_msdu_end_sa_is_valid_get_8074v1,
.hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_8074v1,
.hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_8074v1,
.hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_8074v1,
.hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_8074v1,
.hal_rx_print_pn = hal_rx_print_pn_8074v1,
.hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_8074v1,
.hal_rx_msdu_end_da_is_valid_get =
hal_rx_msdu_end_da_is_valid_get_8074v1,
.hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_8074v1,
.hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_8074v1,
.hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_8074v1,
.hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_8074v1,
.hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_8074v1,
.hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_8074v1,
.hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_8074v1,
.hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_8074v1,
.hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_8074v1,
.hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_8074v1,
.hal_rx_get_mpdu_sequence_control_valid =
hal_rx_get_mpdu_sequence_control_valid_8074v1,
.hal_rx_is_unicast = hal_rx_is_unicast_8074v1,
.hal_rx_tid_get = hal_rx_tid_get_8074v1,
.hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_8074v1,
.hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1,
.hal_rx_msdu_end_sa_sw_peer_id_get =
hal_rx_msdu_end_sa_sw_peer_id_get_8074v1,
.hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_8074v1,
.hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_8074v1,
.hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_8074v1,
.hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_8074v1,
.hal_rx_get_fc_valid = hal_rx_get_fc_valid_8074v1,
.hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_8074v1,
.hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_8074v1,
.hal_rx_get_filter_category = hal_rx_get_filter_category_8074v1,
.hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_8074v1,
.hal_reo_config = hal_reo_config_8074v1,
.hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_8074v1,
.hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_8074v1,
.hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_8074v1,
.hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_8074v1,
.hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_8074v1,
.hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_8074v1,
.hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_8074v1,
.hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_8074v1,
hal_soc->ops->hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic;
hal_soc->ops->hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic;
hal_soc->ops->hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic;
hal_soc->ops->hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_8074v1;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_8074v1;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
hal_rx_msdu_end_sa_is_valid_get_8074v1;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_8074v1;
hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_8074v1;
hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_8074v1;
hal_soc->ops->hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_8074v1;
hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_8074v1;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_8074v1;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
hal_rx_msdu_end_da_is_valid_get_8074v1;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_8074v1;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_8074v1;
hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_8074v1;
hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_8074v1;
hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_8074v1;
hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_8074v1;
hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_8074v1;
hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_8074v1;
hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_8074v1;
hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_8074v1;
hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
hal_rx_get_mpdu_sequence_control_valid_8074v1;
hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_8074v1;
hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_8074v1;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_8074v1;
hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1;
hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
hal_rx_msdu_end_sa_sw_peer_id_get_8074v1;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_8074v1;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_8074v1;
hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_8074v1;
hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_8074v1;
hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_8074v1;
hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_8074v1;
hal_soc->ops->hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_8074v1;
hal_soc->ops->hal_rx_get_filter_category = hal_rx_get_filter_category_8074v1;
hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_8074v1;
hal_soc->ops->hal_reo_config = hal_reo_config_8074v1;
hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_8074v1;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_8074v1;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_8074v1;
hal_soc->ops->hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_8074v1;
hal_soc->ops->hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_8074v1;
hal_soc->ops->hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_8074v1;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_8074v1;
hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_8074v1;
/* rx - msdu fast path info fields */
.hal_rx_msdu_packet_metadata_get =
hal_rx_msdu_packet_metadata_get_generic,
.hal_rx_mpdu_start_tlv_tag_valid =
hal_rx_mpdu_start_tlv_tag_valid_8074v1,
hal_soc->ops->hal_rx_msdu_packet_metadata_get =
hal_rx_msdu_packet_metadata_get_generic;
hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
hal_rx_mpdu_start_tlv_tag_valid_8074v1;
/* rx - TLV struct offsets */
.hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic,
.hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic,
.hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic,
.hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic,
.hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic,
hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic;
#ifndef NO_RX_PKT_HDR_TLV
.hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic,
hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic;
#endif
.hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_8074v1,
.hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_8074v1,
hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_8074v1;
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_8074v1;
};
struct hal_hw_srng_config hw_srng_table_8074[] = {
@@ -1784,5 +1785,5 @@ void hal_qca8074_attach(struct hal_soc *hal_soc)
{
hal_soc->hw_srng_table = hw_srng_table_8074;
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074;
hal_soc->ops = &qca8074_hal_hw_txrx_ops;
hal_hw_txrx_ops_attach_qca8074(hal_soc);
}

223
hal/wifi3.0/qca8074v2/hal_8074v2.c
View File

@@ -1209,131 +1209,132 @@ void hal_compute_reo_remap_ix2_ix3_8074v2(uint32_t *ring, uint32_t num_rings,
}
}
struct hal_hw_txrx_ops qca8074v2_hal_hw_txrx_ops = {
static void hal_hw_txrx_ops_attach_qca8074v2(struct hal_soc *hal_soc)
{
/* init and setup */
.hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic,
.hal_srng_src_hw_init = hal_srng_src_hw_init_generic,
.hal_get_hw_hptp = hal_get_hw_hptp_generic,
.hal_reo_setup = hal_reo_setup_generic,
.hal_setup_link_idle_list = hal_setup_link_idle_list_generic,
.hal_get_window_address = hal_get_window_address_8074v2,
hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic;
hal_soc->ops->hal_setup_link_idle_list = hal_setup_link_idle_list_generic;
hal_soc->ops->hal_get_window_address = hal_get_window_address_8074v2;
/* tx */
.hal_tx_desc_set_dscp_tid_table_id =
hal_tx_desc_set_dscp_tid_table_id_8074v2,
.hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_8074v2,
.hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_8074v2,
.hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_8074v2,
.hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic,
.hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic,
.hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic,
.hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic,
.hal_tx_comp_get_status = hal_tx_comp_get_status_generic,
.hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic,
.hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic,
.hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_8074v2,
.hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_8074v2,
hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
hal_tx_desc_set_dscp_tid_table_id_8074v2;
hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_8074v2;
hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_8074v2;
hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_8074v2;
hal_soc->ops->hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic;
hal_soc->ops->hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic;
hal_soc->ops->hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic;
hal_soc->ops->hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic;
hal_soc->ops->hal_tx_comp_get_status = hal_tx_comp_get_status_generic;
hal_soc->ops->hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic;
hal_soc->ops->hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic;
hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_8074v2;
hal_soc->ops->hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_8074v2;
/* rx */
.hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_8074v2,
.hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_8074v2,
.hal_rx_get_tlv = hal_rx_get_tlv_8074v2,
.hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_8074v2,
.hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_8074v2,
.hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_8074v2,
.hal_get_link_desc_size = hal_get_link_desc_size_8074v2,
.hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_8074v2,
.hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_8074v2,
.hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_8074v2,
.hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_8074v2,
.hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_8074v2,
.hal_reo_status_get_header = hal_reo_status_get_header_8074v2,
.hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic,
.hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic,
.hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic,
hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_8074v2;
hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_8074v2;
hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_8074v2;
hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_8074v2;
hal_soc->ops->hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_8074v2;
hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_8074v2;
hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_8074v2;
hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_8074v2;
hal_soc->ops->hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_8074v2;
hal_soc->ops->hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_8074v2;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_8074v2;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_8074v2;
hal_soc->ops->hal_reo_status_get_header = hal_reo_status_get_header_8074v2;
hal_soc->ops->hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic;
hal_soc->ops->hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic;
.hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic,
.hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic,
.hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic,
.hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_8074v2,
.hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_8074v2,
.hal_rx_msdu_end_sa_is_valid_get =
hal_rx_msdu_end_sa_is_valid_get_8074v2,
.hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_8074v2,
.hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_8074v2,
.hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_8074v2,
.hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_8074v2,
.hal_rx_print_pn = hal_rx_print_pn_8074v2,
.hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_8074v2,
.hal_rx_msdu_end_da_is_valid_get =
hal_rx_msdu_end_da_is_valid_get_8074v2,
.hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_8074v2,
.hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_8074v2,
.hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_8074v2,
.hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_8074v2,
.hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_8074v2,
.hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_8074v2,
.hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_8074v2,
.hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_8074v2,
.hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_8074v2,
.hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_8074v2,
.hal_rx_get_mpdu_sequence_control_valid =
hal_rx_get_mpdu_sequence_control_valid_8074v2,
.hal_rx_is_unicast = hal_rx_is_unicast_8074v2,
.hal_rx_tid_get = hal_rx_tid_get_8074v2,
.hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_8074v2,
.hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2,
.hal_rx_msdu_end_sa_sw_peer_id_get =
hal_rx_msdu_end_sa_sw_peer_id_get_8074v2,
.hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_8074v2,
.hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_8074v2,
.hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_8074v2,
.hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_8074v2,
.hal_rx_get_fc_valid = hal_rx_get_fc_valid_8074v2,
.hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_8074v2,
.hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_8074v2,
.hal_rx_get_filter_category = hal_rx_get_filter_category_8074v2,
.hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_8074v2,
.hal_reo_config = hal_reo_config_8074v2,
.hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_8074v2,
.hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_8074v2,
.hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_8074v2,
.hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_8074v2,
.hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_8074v2,
.hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_8074v2,
.hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_8074v2,
.hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_8074v2,
hal_soc->ops->hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic;
hal_soc->ops->hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic;
hal_soc->ops->hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic;
hal_soc->ops->hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_8074v2;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_8074v2;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
hal_rx_msdu_end_sa_is_valid_get_8074v2;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_8074v2;
hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_8074v2;
hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_8074v2;
hal_soc->ops->hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_8074v2;
hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_8074v2;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_8074v2;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
hal_rx_msdu_end_da_is_valid_get_8074v2;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_8074v2;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_8074v2;
hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_8074v2;
hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_8074v2;
hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_8074v2;
hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_8074v2;
hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_8074v2;
hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_8074v2;
hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_8074v2;
hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_8074v2;
hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
hal_rx_get_mpdu_sequence_control_valid_8074v2;
hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_8074v2;
hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_8074v2;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_8074v2;
hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2;
hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
hal_rx_msdu_end_sa_sw_peer_id_get_8074v2;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_8074v2;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_8074v2;
hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_8074v2;
hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_8074v2;
hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_8074v2;
hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_8074v2;
hal_soc->ops->hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_8074v2;
hal_soc->ops->hal_rx_get_filter_category = hal_rx_get_filter_category_8074v2;
hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_8074v2;
hal_soc->ops->hal_reo_config = hal_reo_config_8074v2;
hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_8074v2;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_8074v2;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_8074v2;
hal_soc->ops->hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_8074v2;
hal_soc->ops->hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_8074v2;
hal_soc->ops->hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_8074v2;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_8074v2;
hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_8074v2;
#if defined(QCA_WIFI_QCA6018) && defined(WLAN_CFR_ENABLE) && \
defined(WLAN_ENH_CFR_ENABLE)
.hal_rx_get_bb_info = hal_rx_get_bb_info_8074v2,
.hal_rx_get_rtt_info = hal_rx_get_rtt_info_8074v2,
hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_8074v2;
hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_8074v2;
#endif
/* rx - msdu fast path info fields */
.hal_rx_msdu_packet_metadata_get =
hal_rx_msdu_packet_metadata_get_generic,
.hal_rx_mpdu_start_tlv_tag_valid =
hal_rx_mpdu_start_tlv_tag_valid_8074v2,
hal_soc->ops->hal_rx_msdu_packet_metadata_get =
hal_rx_msdu_packet_metadata_get_generic;
hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
hal_rx_mpdu_start_tlv_tag_valid_8074v2;
/* rx - TLV struct offsets */
.hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic,
.hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic,
.hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic,
.hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic,
.hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic,
hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic;
#ifndef NO_RX_PKT_HDR_TLV
.hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic,
hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic;
#endif
.hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_8074v2,
.hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_8074v2,
hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_8074v2;
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_8074v2;
};
struct hal_hw_srng_config hw_srng_table_8074v2[] = {
@@ -1789,5 +1790,5 @@ void hal_qca8074v2_attach(struct hal_soc *hal_soc)
{
hal_soc->hw_srng_table = hw_srng_table_8074v2;
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qca8074v2;
hal_soc->ops = &qca8074v2_hal_hw_txrx_ops;
hal_hw_txrx_ops_attach_qca8074v2(hal_soc);
}

221
hal/wifi3.0/qcn6122/hal_qcn6122.c
View File

@@ -1706,129 +1706,130 @@ void hal_compute_reo_remap_ix2_ix3_6122(uint32_t *ring, uint32_t num_rings,
}
}
struct hal_hw_txrx_ops qcn6122_hal_hw_txrx_ops = {
static void hal_hw_txrx_ops_attach_qcn6122(struct hal_soc *hal_soc)
{
/* init and setup */
.hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic,
.hal_srng_src_hw_init = hal_srng_src_hw_init_generic,
.hal_get_hw_hptp = hal_get_hw_hptp_generic,
.hal_reo_setup = hal_reo_setup_generic,
.hal_setup_link_idle_list = hal_setup_link_idle_list_generic,
.hal_get_window_address = hal_get_window_address_6122,
hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic;
hal_soc->ops->hal_setup_link_idle_list = hal_setup_link_idle_list_generic;
hal_soc->ops->hal_get_window_address = hal_get_window_address_6122;
/* tx */
.hal_tx_desc_set_dscp_tid_table_id =
hal_tx_desc_set_dscp_tid_table_id_6122,
.hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6122,
.hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6122,
.hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6122,
.hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic,
.hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic,
.hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic,
.hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic,
.hal_tx_comp_get_status = hal_tx_comp_get_status_generic,
.hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic,
.hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic,
.hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6122,
.hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_6122,
hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
hal_tx_desc_set_dscp_tid_table_id_6122;
hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_6122;
hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_6122;
hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_6122;
hal_soc->ops->hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic;
hal_soc->ops->hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic;
hal_soc->ops->hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic;
hal_soc->ops->hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic;
hal_soc->ops->hal_tx_comp_get_status = hal_tx_comp_get_status_generic;
hal_soc->ops->hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic;
hal_soc->ops->hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic;
hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_6122;
hal_soc->ops->hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_6122;
/* rx */
.hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_6122,
.hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_6122,
.hal_rx_get_tlv = hal_rx_get_tlv_6122,
.hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_6122,
.hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_6122,
.hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6122,
.hal_get_link_desc_size = hal_get_link_desc_size_6122,
.hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_6122,
.hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_6122,
.hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_6122,
.hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_6122,
.hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_6122,
.hal_reo_status_get_header = hal_reo_status_get_header_6122,
.hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic,
.hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic,
.hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic,
hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_6122;
hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_6122;
hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_6122;
hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_6122;
hal_soc->ops->hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_6122;
hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_6122;
hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_6122;
hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_6122;
hal_soc->ops->hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_6122;
hal_soc->ops->hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_6122;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_6122;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_6122;
hal_soc->ops->hal_reo_status_get_header = hal_reo_status_get_header_6122;
hal_soc->ops->hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic;
hal_soc->ops->hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic;
.hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic,
.hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic,
.hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic,
.hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_6122,
.hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_6122,
.hal_rx_msdu_end_sa_is_valid_get = hal_rx_msdu_end_sa_is_valid_get_6122,
.hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_6122,
.hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_6122,
.hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_6122,
.hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_6122,
.hal_rx_print_pn = hal_rx_print_pn_6122,
.hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_6122,
.hal_rx_msdu_end_da_is_valid_get = hal_rx_msdu_end_da_is_valid_get_6122,
.hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_6122,
.hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_6122,
.hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_6122,
.hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6122,
.hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6122,
.hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_6122,
.hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6122,
.hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6122,
.hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6122,
.hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6122,
.hal_rx_get_mpdu_sequence_control_valid =
hal_rx_get_mpdu_sequence_control_valid_6122,
.hal_rx_is_unicast = hal_rx_is_unicast_6122,
.hal_rx_tid_get = hal_rx_tid_get_6122,
.hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_6122,
.hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_6122,
.hal_rx_msdu_end_sa_sw_peer_id_get =
hal_rx_msdu_end_sa_sw_peer_id_get_6122,
.hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_6122,
.hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_6122,
.hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6122,
.hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6122,
.hal_rx_get_fc_valid = hal_rx_get_fc_valid_6122,
.hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6122,
.hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_6122,
.hal_rx_get_filter_category = hal_rx_get_filter_category_6122,
.hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6122,
.hal_reo_config = hal_reo_config_6122,
.hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6122,
.hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_6122,
.hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_6122,
.hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_6122,
.hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_6122,
.hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_6122,
.hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_6122,
.hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6122,
hal_soc->ops->hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic;
hal_soc->ops->hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic;
hal_soc->ops->hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic;
hal_soc->ops->hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_6122;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_6122;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = hal_rx_msdu_end_sa_is_valid_get_6122;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_6122;
hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_6122;
hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_6122;
hal_soc->ops->hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_6122;
hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_6122;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_6122;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = hal_rx_msdu_end_da_is_valid_get_6122;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_6122;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_6122;
hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_6122;
hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_6122;
hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_6122;
hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_6122;
hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_6122;
hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_6122;
hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_6122;
hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_6122;
hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
hal_rx_get_mpdu_sequence_control_valid_6122;
hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_6122;
hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_6122;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_6122;
hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_6122;
hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
hal_rx_msdu_end_sa_sw_peer_id_get_6122;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_6122;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_6122;
hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_6122;
hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_6122;
hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_6122;
hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_6122;
hal_soc->ops->hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_6122;
hal_soc->ops->hal_rx_get_filter_category = hal_rx_get_filter_category_6122;
hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_6122;
hal_soc->ops->hal_reo_config = hal_reo_config_6122;
hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_6122;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_6122;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_6122;
hal_soc->ops->hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_6122;
hal_soc->ops->hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_6122;
hal_soc->ops->hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_6122;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_6122;
hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_6122;
#if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
.hal_rx_get_bb_info = hal_rx_get_bb_info_6122,
.hal_rx_get_rtt_info = hal_rx_get_rtt_info_6122,
hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_6122;
hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_6122;
#endif
/* rx - msdu fast path info fields */
.hal_rx_msdu_packet_metadata_get = hal_rx_msdu_packet_metadata_get_6122,
.hal_rx_mpdu_start_tlv_tag_valid = hal_rx_mpdu_start_tlv_tag_valid_6122,
.hal_rx_sw_mon_desc_info_get = hal_rx_sw_mon_desc_info_get_6122,
.hal_rx_wbm_err_msdu_continuation_get =
hal_rx_wbm_err_msdu_continuation_get_6122,
hal_soc->ops->hal_rx_msdu_packet_metadata_get = hal_rx_msdu_packet_metadata_get_6122;
hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = hal_rx_mpdu_start_tlv_tag_valid_6122;
hal_soc->ops->hal_rx_sw_mon_desc_info_get = hal_rx_sw_mon_desc_info_get_6122;
hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get =
hal_rx_wbm_err_msdu_continuation_get_6122;
/* rx - TLV struct offsets */
.hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic,
.hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic,
.hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic,
.hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic,
.hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic,
hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic;
#ifndef NO_RX_PKT_HDR_TLV
.hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic,
hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic;
#endif
.hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6122,
.hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_6122,
hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_6122;
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_6122;
};
struct hal_hw_srng_config hw_srng_table_6122[] = {
@@ -2284,7 +2285,7 @@ void hal_qcn6122_attach(struct hal_soc *hal_soc)
{
hal_soc->hw_srng_table = hw_srng_table_6122;
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qcn6122;
hal_soc->ops = &qcn6122_hal_hw_txrx_ops;
hal_hw_txrx_ops_attach_qcn6122(hal_soc);
if (hal_soc->static_window_map)
hal_write_window_register(hal_soc);
}

222
hal/wifi3.0/qcn9000/hal_9000.c
View File

@@ -1731,129 +1731,131 @@ void hal_compute_reo_remap_ix2_ix3_9000(uint32_t *ring, uint32_t num_rings,
break;
}
}
struct hal_hw_txrx_ops qcn9000_hal_hw_txrx_ops = {
static void hal_hw_txrx_ops_attach_qcn9000(struct hal_soc *hal_soc)
{
/* init and setup */
.hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic,
.hal_srng_src_hw_init = hal_srng_src_hw_init_generic,
.hal_get_hw_hptp = hal_get_hw_hptp_generic,
.hal_reo_setup = hal_reo_setup_generic,
.hal_setup_link_idle_list = hal_setup_link_idle_list_generic,
.hal_get_window_address = hal_get_window_address_9000,
hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
hal_soc->ops->hal_reo_setup = hal_reo_setup_generic;
hal_soc->ops->hal_setup_link_idle_list = hal_setup_link_idle_list_generic;
hal_soc->ops->hal_get_window_address = hal_get_window_address_9000;
/* tx */
.hal_tx_desc_set_dscp_tid_table_id =
hal_tx_desc_set_dscp_tid_table_id_9000,
.hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_9000,
.hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_9000,
.hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_9000,
.hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic,
.hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic,
.hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic,
.hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic,
.hal_tx_comp_get_status = hal_tx_comp_get_status_generic,
.hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic,
.hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic,
.hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_9000,
.hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_9000,
hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
hal_tx_desc_set_dscp_tid_table_id_9000;
hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_9000;
hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_9000;
hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_9000;
hal_soc->ops->hal_tx_desc_set_buf_addr = hal_tx_desc_set_buf_addr_generic;
hal_soc->ops->hal_tx_desc_set_search_type = hal_tx_desc_set_search_type_generic;
hal_soc->ops->hal_tx_desc_set_search_index = hal_tx_desc_set_search_index_generic;
hal_soc->ops->hal_tx_desc_set_cache_set_num = hal_tx_desc_set_cache_set_num_generic;
hal_soc->ops->hal_tx_comp_get_status = hal_tx_comp_get_status_generic;
hal_soc->ops->hal_tx_comp_get_release_reason =
hal_tx_comp_get_release_reason_generic;
hal_soc->ops->hal_get_wbm_internal_error = hal_get_wbm_internal_error_generic;
hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_9000;
hal_soc->ops->hal_tx_init_cmd_credit_ring = hal_tx_init_cmd_credit_ring_9000;
/* rx */
.hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_9000,
.hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_9000,
.hal_rx_get_tlv = hal_rx_get_tlv_9000,
.hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_9000,
.hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_9000,
.hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_9000,
.hal_get_link_desc_size = hal_get_link_desc_size_9000,
.hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_9000,
.hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_9000,
.hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_9000,
.hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_9000,
.hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_9000,
.hal_reo_status_get_header = hal_reo_status_get_header_9000,
.hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic,
.hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic,
.hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic,
hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_msdu_start_nss_get_9000;
hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
hal_rx_mon_hw_desc_get_mpdu_status_9000;
hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_9000;
hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
hal_rx_proc_phyrx_other_receive_info_tlv_9000;
hal_soc->ops->hal_rx_dump_msdu_start_tlv = hal_rx_dump_msdu_start_tlv_9000;
hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_9000;
hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_9000;
hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_mpdu_start_tid_get_9000;
hal_soc->ops->hal_rx_msdu_start_reception_type_get =
hal_rx_msdu_start_reception_type_get_9000;
hal_soc->ops->hal_rx_msdu_end_da_idx_get = hal_rx_msdu_end_da_idx_get_9000;
hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = hal_rx_msdu_desc_info_get_ptr_9000;
hal_soc->ops->hal_rx_link_desc_msdu0_ptr = hal_rx_link_desc_msdu0_ptr_9000;
hal_soc->ops->hal_reo_status_get_header = hal_reo_status_get_header_9000;
hal_soc->ops->hal_rx_status_get_tlv_info = hal_rx_status_get_tlv_info_generic;
hal_soc->ops->hal_rx_wbm_err_info_get = hal_rx_wbm_err_info_get_generic;
hal_soc->ops->hal_rx_dump_mpdu_start_tlv = hal_rx_dump_mpdu_start_tlv_generic;
.hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic,
.hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic,
.hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic,
.hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_9000,
.hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_9000,
.hal_rx_msdu_end_sa_is_valid_get = hal_rx_msdu_end_sa_is_valid_get_9000,
.hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_9000,
.hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_9000,
.hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_9000,
.hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_9000,
.hal_rx_print_pn = hal_rx_print_pn_9000,
.hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_9000,
.hal_rx_msdu_end_da_is_valid_get = hal_rx_msdu_end_da_is_valid_get_9000,
.hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_9000,
.hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_9000,
.hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_9000,
.hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_9000,
.hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_9000,
.hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_9000,
.hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_9000,
.hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_9000,
.hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_9000,
.hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_9000,
.hal_rx_get_mpdu_sequence_control_valid =
hal_rx_get_mpdu_sequence_control_valid_9000,
.hal_rx_is_unicast = hal_rx_is_unicast_9000,
.hal_rx_tid_get = hal_rx_tid_get_9000,
.hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_9000,
.hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000,
.hal_rx_msdu_end_sa_sw_peer_id_get =
hal_rx_msdu_end_sa_sw_peer_id_get_9000,
.hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_9000,
.hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_9000,
.hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_9000,
.hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_9000,
.hal_rx_get_fc_valid = hal_rx_get_fc_valid_9000,
.hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_9000,
.hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_9000,
.hal_rx_get_filter_category = hal_rx_get_filter_category_9000,
.hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_9000,
.hal_reo_config = hal_reo_config_9000,
.hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_9000,
.hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_9000,
.hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_9000,
.hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_9000,
.hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_9000,
.hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_9000,
.hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_9000,
.hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_9000,
hal_soc->ops->hal_tx_set_pcp_tid_map = hal_tx_set_pcp_tid_map_generic;
hal_soc->ops->hal_tx_update_pcp_tid_map = hal_tx_update_pcp_tid_generic;
hal_soc->ops->hal_tx_set_tidmap_prty = hal_tx_update_tidmap_prty_generic;
hal_soc->ops->hal_rx_get_rx_fragment_number = hal_rx_get_rx_fragment_number_9000;
hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = hal_rx_msdu_end_da_is_mcbc_get_9000;
hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = hal_rx_msdu_end_sa_is_valid_get_9000;
hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_msdu_end_sa_idx_get_9000;
hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_9000;
hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
hal_rx_msdu_end_l3_hdr_padding_get_9000;
hal_soc->ops->hal_rx_encryption_info_valid = hal_rx_encryption_info_valid_9000;
hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_9000;
hal_soc->ops->hal_rx_msdu_end_first_msdu_get = hal_rx_msdu_end_first_msdu_get_9000;
hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = hal_rx_msdu_end_da_is_valid_get_9000;
hal_soc->ops->hal_rx_msdu_end_last_msdu_get = hal_rx_msdu_end_last_msdu_get_9000;
hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = hal_rx_get_mpdu_mac_ad4_valid_9000;
hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
hal_rx_mpdu_start_sw_peer_id_get_9000;
hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_9000;
hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_9000;
hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
hal_rx_get_mpdu_frame_control_valid_9000;
hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_9000;
hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_9000;
hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_9000;
hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_9000;
hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
hal_rx_get_mpdu_sequence_control_valid_9000;
hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_9000;
hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_9000;
hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = hal_rx_hw_desc_get_ppduid_get_9000;
hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
hal_rx_mpdu_start_mpdu_qos_control_valid_get_9000;
hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
hal_rx_msdu_end_sa_sw_peer_id_get_9000;
hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = hal_rx_msdu0_buffer_addr_lsb_9000;
hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = hal_rx_msdu_desc_info_ptr_get_9000;
hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_9000;
hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_9000;
hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_9000;
hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_9000;
hal_soc->ops->hal_rx_get_mac_addr2_valid = hal_rx_get_mac_addr2_valid_9000;
hal_soc->ops->hal_rx_get_filter_category = hal_rx_get_filter_category_9000;
hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_9000;
hal_soc->ops->hal_reo_config = hal_reo_config_9000;
hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_9000;
hal_soc->ops->hal_rx_msdu_flow_idx_invalid = hal_rx_msdu_flow_idx_invalid_9000;
hal_soc->ops->hal_rx_msdu_flow_idx_timeout = hal_rx_msdu_flow_idx_timeout_9000;
hal_soc->ops->hal_rx_msdu_fse_metadata_get = hal_rx_msdu_fse_metadata_get_9000;
hal_soc->ops->hal_rx_msdu_cce_metadata_get = hal_rx_msdu_cce_metadata_get_9000;
hal_soc->ops->hal_rx_msdu_get_flow_params = hal_rx_msdu_get_flow_params_9000;
hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_9000;
hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_9000;
#if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
.hal_rx_get_bb_info = hal_rx_get_bb_info_9000,
.hal_rx_get_rtt_info = hal_rx_get_rtt_info_9000,
hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_9000;
hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_9000;
#endif
/* rx - msdu fast path info fields */
.hal_rx_msdu_packet_metadata_get = hal_rx_msdu_packet_metadata_get_9000,
.hal_rx_mpdu_start_tlv_tag_valid = hal_rx_mpdu_start_tlv_tag_valid_9000,
.hal_rx_sw_mon_desc_info_get = hal_rx_sw_mon_desc_info_get_9000,
.hal_rx_wbm_err_msdu_continuation_get =
hal_rx_wbm_err_msdu_continuation_get_9000,
hal_soc->ops->hal_rx_msdu_packet_metadata_get = hal_rx_msdu_packet_metadata_get_9000;
hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = hal_rx_mpdu_start_tlv_tag_valid_9000;
hal_soc->ops->hal_rx_sw_mon_desc_info_get = hal_rx_sw_mon_desc_info_get_9000;
hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get =
hal_rx_wbm_err_msdu_continuation_get_9000;
/* rx - TLV struct offsets */
.hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic,
.hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic,
.hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic,
.hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic,
.hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic,
hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic;
hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic;
hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic;
#ifndef NO_RX_PKT_HDR_TLV
.hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic,
hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic;
#endif
.hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_9000,
.hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_9000,
hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_9000;
hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_9000;
};
struct hal_hw_srng_config hw_srng_table_9000[] = {
@@ -2309,7 +2311,7 @@ void hal_qcn9000_attach(struct hal_soc *hal_soc)
{
hal_soc->hw_srng_table = hw_srng_table_9000;
hal_soc->hal_hw_reg_offset = hal_hw_reg_offset_qcn9000;
hal_soc->ops = &qcn9000_hal_hw_txrx_ops;
hal_hw_txrx_ops_attach_qcn9000(hal_soc);
if (hal_soc->static_window_map)
hal_write_window_register(hal_soc);
}