qcacmn: Add missing lock protection between DP Tx and Tx completions
Change-Id: I68dd5371688235c173a5bc6576601389146e0ecb CRs-Fixed: 2004658
This commit is contained in:

committed by
qcabuildsw

parent
25aa822c28
commit
4d5d436e8a
@@ -114,11 +114,10 @@ dp_tx_desc_release(struct dp_vdev *vdev, struct dp_tx_desc_s *tx_desc,
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if (tx_desc->flags & DP_TX_DESC_FLAG_FRAG)
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dp_tx_ext_desc_free(soc, tx_desc->msdu_ext_desc, desc_pool_id);
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vdev->num_tx_outstanding--;
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pdev->num_tx_outstanding--;
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qdf_atomic_dec(&pdev->num_tx_outstanding);
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if (tx_desc->flags & DP_TX_DESC_FLAG_TO_FW)
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pdev->num_tx_exception--;
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qdf_atomic_dec(&pdev->num_tx_exception);
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if (HAL_TX_COMP_RELEASE_SOURCE_TQM ==
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hal_tx_comp_get_buffer_source(&tx_desc->comp))
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@@ -311,8 +310,7 @@ struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
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}
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/* Flow control/Congestion Control counters */
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vdev->num_tx_outstanding++;
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pdev->num_tx_outstanding++;
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qdf_atomic_inc(&pdev->num_tx_outstanding);
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/* Initialize the SW tx descriptor */
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tx_desc->nbuf = nbuf;
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@@ -346,7 +344,6 @@ struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
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align_pad);
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tx_desc->pkt_offset += htt_hdr_size;
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tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
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pdev->num_tx_exception++;
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is_exception = 1;
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}
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@@ -354,7 +351,6 @@ struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
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eh = (struct ether_header *) qdf_nbuf_data(nbuf);
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if (DP_FRAME_IS_MULTICAST((eh)->ether_dhost)) {
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tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
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pdev->num_tx_exception++;
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is_exception = 1;
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}
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}
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@@ -365,7 +361,7 @@ struct dp_tx_desc_s *dp_tx_prepare_desc_single(struct dp_vdev *vdev,
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{
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/* Temporary WAR due to TQM VP issues */
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tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
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pdev->num_tx_exception++;
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qdf_atomic_inc(&pdev->num_tx_exception);
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}
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return tx_desc;
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@@ -412,11 +408,8 @@ static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
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if (!tx_desc)
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return NULL;
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tx_desc->flags |= DP_TX_DESC_FLAG_ALLOCATED;
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/* Flow control/Congestion Control counters */
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vdev->num_tx_outstanding++;
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pdev->num_tx_outstanding++;
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qdf_atomic_inc(&pdev->num_tx_outstanding);
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/* Initialize the SW tx descriptor */
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tx_desc->nbuf = nbuf;
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@@ -438,7 +431,7 @@ static struct dp_tx_desc_s *dp_tx_prepare_desc(struct dp_vdev *vdev,
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#if TQM_BYPASS_WAR
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/* Temporary WAR due to TQM VP issues */
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tx_desc->flags |= DP_TX_DESC_FLAG_TO_FW;
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pdev->num_tx_exception++;
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qdf_atomic_inc(&pdev->num_tx_exception);
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#endif
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tx_desc->msdu_ext_desc = msdu_ext_desc;
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@@ -1071,7 +1064,7 @@ void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
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switch (tx_status) {
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case HTT_TX_FW2WBM_TX_STATUS_OK:
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{
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pdev->num_tx_exception--;
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qdf_atomic_dec(&pdev->num_tx_exception);
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DP_TX_FREE_SINGLE_BUF(soc, vdev,
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tx_desc->nbuf);
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break;
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@@ -1081,7 +1074,7 @@ void dp_tx_process_htt_completion(struct dp_tx_desc_s *tx_desc, uint8_t *status)
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{
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DP_TX_FREE_SINGLE_BUF(soc, vdev,
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tx_desc->nbuf);
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pdev->num_tx_exception--;
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qdf_atomic_dec(&pdev->num_tx_exception);
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DP_STATS_MSDU_INCR(soc, tx.dropped.pkts, tx_desc->nbuf);
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break;
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}
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@@ -1372,8 +1365,6 @@ uint32_t dp_tx_comp_handler(struct dp_soc *soc, uint32_t ring_id,
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QDF_STATUS dp_tx_vdev_attach(struct dp_vdev *vdev)
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{
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vdev->num_tx_outstanding = 0;
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/*
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* Fill HTT TCL Metadata with Vdev ID and MAC ID
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*/
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@@ -1418,8 +1409,8 @@ QDF_STATUS dp_tx_pdev_attach(struct dp_pdev *pdev)
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struct dp_soc *soc = pdev->soc;
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/* Initialize Flow control counters */
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pdev->num_tx_exception = 0;
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pdev->num_tx_outstanding = 0;
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qdf_atomic_init(&pdev->num_tx_exception);
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qdf_atomic_init(&pdev->num_tx_outstanding);
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if (wlan_cfg_per_pdev_tx_ring(soc->wlan_cfg_ctx)) {
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/* Initialize descriptors in TCL Ring */
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@@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016 The Linux Foundation. All rights reserved.
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* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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@@ -36,26 +36,10 @@
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#define DP_TX_DESC_ID_OFFSET_MASK 0x0003FF
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#define DP_TX_DESC_ID_OFFSET_OS 0
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/**
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* In case of TX descriptor pool and CPU core is combined
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* TX context and TX comp context also should running on the same core
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* in this case, each TX desciptror pool operation will be serialized by core
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* TX and TX_COMP will not race. locking for protection is not requried
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* TX_DESC_POOL_PER_CORE : this is most likely for WIN
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* MCL, TX descriptor pool will be tied to VDEV instance.
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* Then locking protection is required
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*/
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#ifdef TX_CORE_ALIGNED_SEND
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#define TX_DESC_LOCK_CREATE(lock) /* NOOP */
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#define TX_DESC_LOCK_DESTROY(lock) /* NOOP */
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#define TX_DESC_LOCK_LOCK(lock) /* NOOP */
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#define TX_DESC_LOCK_UNLOCK(lock) /* NOOP */
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#else
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#define TX_DESC_LOCK_CREATE(lock) qdf_spinlock_create(lock)
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#define TX_DESC_LOCK_DESTROY(lock) qdf_spinlock_destroy(lock)
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#define TX_DESC_LOCK_LOCK(lock) qdf_spin_lock(lock)
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#define TX_DESC_LOCK_UNLOCK(lock) qdf_spin_unlock(lock)
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#endif /* TX_CORE_ALIGNED_SEND */
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QDF_STATUS dp_tx_desc_pool_alloc(struct dp_soc *soc, uint8_t pool_id,
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uint16_t num_elem);
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@@ -91,7 +75,7 @@ static inline struct dp_tx_desc_s *dp_tx_desc_alloc(struct dp_soc *soc,
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soc->tx_desc[desc_pool_id].num_allocated++;
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}
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DP_STATS_ADD(pdev, pub.tx.desc_in_use, 1);
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tx_desc->flags |= DP_TX_DESC_FLAG_ALLOCATED;
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tx_desc->flags = DP_TX_DESC_FLAG_ALLOCATED;
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TX_DESC_LOCK_UNLOCK(&soc->tx_desc[desc_pool_id].lock);
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return tx_desc;
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@@ -111,7 +95,7 @@ dp_tx_desc_free(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc,
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{
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TX_DESC_LOCK_LOCK(&soc->tx_desc[desc_pool_id].lock);
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tx_desc->flags &= ~DP_TX_DESC_FLAG_ALLOCATED;
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tx_desc->flags = 0;
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tx_desc->next = soc->tx_desc[desc_pool_id].freelist;
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soc->tx_desc[desc_pool_id].freelist = tx_desc;
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DP_STATS_SUB(pdev, pub.tx.desc_in_use, 1);
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@@ -537,9 +537,9 @@ struct dp_pdev {
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/* Enhanced Stats is enabled */
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bool ap_stats_tx_cal_enable;
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uint32_t num_tx_outstanding;
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qdf_atomic_t num_tx_outstanding;
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uint32_t num_tx_exception;
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qdf_atomic_t num_tx_exception;
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/* MCL specific local peer handle */
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struct {
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@@ -655,8 +655,6 @@ struct dp_vdev {
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/* Multicast enhancement enabled */
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uint8_t mcast_enhancement_en;
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uint32_t num_tx_outstanding;
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/* per vdev rx nbuf queue */
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qdf_nbuf_queue_t rxq;
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@@ -280,7 +280,7 @@ static inline void hal_tx_desc_set_buf_addr(void *desc,
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HAL_SET_FLD(desc, TCL_DATA_CMD_1,
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BUFFER_ADDR_INFO_BUF_ADDR_INFO) |=
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HAL_TX_SM(BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32,
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(((uint64_t) paddr) << 32));
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(((uint64_t) paddr) >> 32));
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/* Set buffer_addr_info.return_buffer_manager = pool id */
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HAL_SET_FLD(desc, TCL_DATA_CMD_1,
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