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qcacmn: SDIO bus support (Part 1 - HIF SDIO)

Przeglądaj źródła 
Add legacy hif sdio code.
Implement new hif sdio interfaces with respect to new hif design.
Add datapath to HIF interfaces.
Refactor hif-sdio codebase.
Remove references to older kernel version.

Change-Id: Ieca3e512edca5f960d6f2b64d15121db6c8138c7
CRs-Fixed: 969334
This commit is contained in:
Govind Singh
2016-05-12 20:02:01 +05:30
zatwierdzone przez Vishwajith Upendra
rodzic 28803728da
commit 4cc8213cc2
27 zmienionych plików z 9172 dodań i 208 usunięć
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70
hif/inc/hif.h
Wyświetl plik

@@ -218,6 +218,42 @@ enum hif_disable_type {
HIF_DISABLE_TYPE_SHUTDOWN,
HIF_DISABLE_TYPE_MAX
};
/**
* enum hif_device_config_opcode: configure mode
*
* @HIF_DEVICE_POWER_STATE: device power state
* @HIF_DEVICE_GET_MBOX_BLOCK_SIZE: get mbox block size
* @HIF_DEVICE_GET_MBOX_ADDR: get mbox block address
* @HIF_DEVICE_GET_PENDING_EVENTS_FUNC: get pending events functions
* @HIF_DEVICE_GET_IRQ_PROC_MODE: get irq proc mode
* @HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC: receive event function
* @HIF_DEVICE_POWER_STATE_CHANGE: change power state
* @HIF_DEVICE_GET_IRQ_YIELD_PARAMS: get yield params
* @HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT: configure scatter request
* @HIF_DEVICE_GET_OS_DEVICE: get OS device
* @HIF_DEVICE_DEBUG_BUS_STATE: debug bus state
* @HIF_BMI_DONE: bmi done
* @HIF_DEVICE_SET_TARGET_TYPE: set target type
* @HIF_DEVICE_SET_HTC_CONTEXT: set htc context
* @HIF_DEVICE_GET_HTC_CONTEXT: get htc context
*/
enum hif_device_config_opcode {
HIF_DEVICE_POWER_STATE = 0,
HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
HIF_DEVICE_GET_MBOX_ADDR,
HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
HIF_DEVICE_GET_IRQ_PROC_MODE,
HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC,
HIF_DEVICE_POWER_STATE_CHANGE,
HIF_DEVICE_GET_IRQ_YIELD_PARAMS,
HIF_CONFIGURE_QUERY_SCATTER_REQUEST_SUPPORT,
HIF_DEVICE_GET_OS_DEVICE,
HIF_DEVICE_DEBUG_BUS_STATE,
HIF_BMI_DONE,
HIF_DEVICE_SET_TARGET_TYPE,
HIF_DEVICE_SET_HTC_CONTEXT,
HIF_DEVICE_GET_HTC_CONTEXT,
};
#ifdef CONFIG_ATH_PCIE_ACCESS_DEBUG
typedef struct _HID_ACCESS_LOG {
@@ -238,8 +274,8 @@ struct htc_callbacks {
void *context; /* context to pass to the dsrhandler
* note : rwCompletionHandler is provided
* the context passed to hif_read_write */
int (*rwCompletionHandler)(void *rwContext, int status);
int (*dsrHandler)(void *context);
QDF_STATUS(*rwCompletionHandler)(void *rwContext, QDF_STATUS status);
QDF_STATUS(*dsrHandler)(void *context);
};
/**
@@ -342,33 +378,10 @@ static inline int hif_ce_fastpath_cb_register(struct hif_opaque_softc *hif_ctx,
*/
#define CONFIG_DISABLE_CDC_MAX_PERF_WAR 0
#ifdef IPA_OFFLOAD
void hif_ipa_get_ce_resource(struct hif_opaque_softc *scn,
qdf_dma_addr_t *ce_sr_base_paddr,
uint32_t *ce_sr_ring_size,
qdf_dma_addr_t *ce_reg_paddr);
#else
/**
* hif_ipa_get_ce_resource() - get uc resource on hif
* @scn: bus context
* @ce_sr_base_paddr: copyengine source ring base physical address
* @ce_sr_ring_size: copyengine source ring size
* @ce_reg_paddr: copyengine register physical address
*
* IPA micro controller data path offload feature enabled,
* HIF should release copy engine related resource information to IPA UC
* IPA UC will access hardware resource with released information
*
* Return: None
*/
static inline void hif_ipa_get_ce_resource(struct hif_opaque_softc *scn,
qdf_dma_addr_t *ce_sr_base_paddr,
uint32_t *ce_sr_ring_size,
qdf_dma_addr_t *ce_reg_paddr)
{
return;
}
#endif /* IPA_OFFLOAD */
/**
* @brief List of callbacks - filled in by HTC.
@@ -437,6 +450,11 @@ struct hif_pipe_addl_info {
struct hif_bus_id;
typedef struct hif_bus_id hif_bus_id;
void hif_claim_device(struct hif_opaque_softc *hif_ctx);
QDF_STATUS hif_get_config_item(struct hif_opaque_softc *hif_ctx,
int opcode, void *config, uint32_t config_len);
void hif_set_mailbox_swap(struct hif_opaque_softc *hif_ctx);
void hif_mask_interrupt_call(struct hif_opaque_softc *scn);
void hif_post_init(struct hif_opaque_softc *scn, void *hHTC,
struct hif_msg_callbacks *callbacks);
QDF_STATUS hif_start(struct hif_opaque_softc *scn);
@@ -554,6 +572,8 @@ void hif_process_runtime_resume_success(struct hif_opaque_softc *);
int hif_dump_registers(struct hif_opaque_softc *scn);
int ol_copy_ramdump(struct hif_opaque_softc *scn);
void hif_crash_shutdown(struct hif_opaque_softc *hif_ctx);
void hif_bus_pkt_dl_len_set(struct hif_opaque_softc *hif_sc,
unsigned int pkt_download_len);
void hif_get_hw_info(struct hif_opaque_softc *scn, u32 *version, u32 *revision,
const char **target_name);
void hif_lro_flush_cb_register(struct hif_opaque_softc *scn,

5
hif/inc/regtable.h
Wyświetl plik

@@ -28,6 +28,11 @@
#ifndef _REGTABLE_H_
#define _REGTABLE_H_
#ifdef HIF_SDIO
#include "regtable_sdio.h"
#endif
#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
#include "reg_struct.h"
#include "regtable_pcie.h"
#endif
#endif

145
hif/src/ar6320def.h
Wyświetl plik

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2011-2015 The Linux Foundation. All rights reserved.
* Copyright (c) 2011-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -33,7 +33,6 @@
#define AR6320_RTC_WMAC_BASE_ADDRESS 0x00001000
#define AR6320_MAC_COEX_BASE_ADDRESS 0x0000f000
#define AR6320_BT_COEX_BASE_ADDRESS 0x00002000
#define AR6320_SOC_PCIE_BASE_ADDRESS 0x00038000
#define AR6320_SOC_CORE_BASE_ADDRESS 0x0003a000
#define AR6320_WLAN_UART_BASE_ADDRESS 0x0000c000
#define AR6320_WLAN_SI_BASE_ADDRESS 0x00010000
@@ -43,17 +42,7 @@
#define AR6320_EFUSE_BASE_ADDRESS 0x00024000
#define AR6320_FPGA_REG_BASE_ADDRESS 0x00039000
#define AR6320_WLAN_UART2_BASE_ADDRESS 0x00054c00
#define AR6320_CE_WRAPPER_BASE_ADDRESS 0x00034000
#define AR6320_CE0_BASE_ADDRESS 0x00034400
#define AR6320_CE1_BASE_ADDRESS 0x00034800
#define AR6320_CE2_BASE_ADDRESS 0x00034c00
#define AR6320_CE3_BASE_ADDRESS 0x00035000
#define AR6320_CE4_BASE_ADDRESS 0x00035400
#define AR6320_CE5_BASE_ADDRESS 0x00035800
#define AR6320_CE6_BASE_ADDRESS 0x00035c00
#define AR6320_CE7_BASE_ADDRESS 0x00036000
#define AR6320_DBI_BASE_ADDRESS 0x0003c000
#define AR6320_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x00007800
#define AR6320_SCRATCH_3_ADDRESS 0x0028
#define AR6320_TARG_DRAM_START 0x00400000
@@ -107,7 +96,6 @@
#define AR6320_SI_CS_RX_CNT_MASK 0x000000f0
#define AR6320_SI_CS_TX_CNT_LSB 0
#define AR6320_SI_CS_TX_CNT_MASK 0x0000000f
#define AR6320_CE_COUNT 8
#define AR6320_SR_WR_INDEX_ADDRESS 0x003c
#define AR6320_DST_WATERMARK_ADDRESS 0x0050
#define AR6320_RX_MSDU_END_4_FIRST_MSDU_LSB 14
@@ -118,6 +106,46 @@
#define AR6320_RX_MPDU_START_0_SEQ_NUM_MASK 0x0fff0000
#define AR6320_RX_MPDU_START_2_TID_LSB 28
#define AR6320_RX_MPDU_START_2_TID_MASK 0xf0000000
#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
#define AR6320_SOC_PCIE_BASE_ADDRESS 0x00038000
#define AR6320_CE_WRAPPER_BASE_ADDRESS 0x00034000
#define AR6320_CE0_BASE_ADDRESS 0x00034400
#define AR6320_CE1_BASE_ADDRESS 0x00034800
#define AR6320_CE2_BASE_ADDRESS 0x00034c00
#define AR6320_CE3_BASE_ADDRESS 0x00035000
#define AR6320_CE4_BASE_ADDRESS 0x00035400
#define AR6320_CE5_BASE_ADDRESS 0x00035800
#define AR6320_CE6_BASE_ADDRESS 0x00035c00
#define AR6320_CE7_BASE_ADDRESS 0x00036000
#define AR6320_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x00007800
#define AR6320_CE_COUNT 8
#define AR6320_CE_CTRL1_ADDRESS 0x0010
#define AR6320_CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff
#define AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
#define AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00
#define AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8
#define AR6320_CE_CTRL1_DMAX_LENGTH_LSB 0
#define AR6320_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000
#define AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000
#define AR6320_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16
#define AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17
#define AR6320_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000020
#define AR6320_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB 5
#define AR6320_PCIE_SOC_WAKE_RESET 0x00000000
#define AR6320_PCIE_SOC_WAKE_ADDRESS 0x0004
#define AR6320_PCIE_SOC_WAKE_V_MASK 0x00000001
#define AR6320_MUX_ID_MASK 0x0000
#define AR6320_TRANSACTION_ID_MASK 0x3fff
#define AR6320_PCIE_LOCAL_BASE_ADDRESS 0x80000
#define AR6320_FW_IND_HELPER 4
#define AR6320_PCIE_INTR_ENABLE_ADDRESS 0x0008
#define AR6320_PCIE_INTR_CLR_ADDRESS 0x0014
#define AR6320_PCIE_INTR_FIRMWARE_MASK 0x00000400
#define AR6320_PCIE_INTR_CE0_MASK 0x00000800
#define AR6320_PCIE_INTR_CE_MASK_ALL 0x0007f800
#define AR6320_PCIE_INTR_CAUSE_ADDRESS 0x000c
#define AR6320_SOC_RESET_CONTROL_CE_RST_MASK 0x00000001
#endif
#define AR6320_RX_MPDU_START_2_PN_47_32_LSB 0
#define AR6320_RX_MPDU_START_2_PN_47_32_MASK 0x0000ffff
#define AR6320_RX_MSDU_END_1_KEY_ID_OCT_MASK 0x000000ff
@@ -157,13 +185,10 @@
#define AR6320_HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010
#define AR6320_HOST_IS_ADDRESS 0x0030
#define AR6320_HOST_IS_COPY_COMPLETE_MASK 0x00000001
#define AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
#define AR6320_HOST_IE_ADDRESS 0x002c
#define AR6320_HOST_IE_COPY_COMPLETE_MASK 0x00000001
#define AR6320_SR_BA_ADDRESS 0x0000
#define AR6320_SR_SIZE_ADDRESS 0x0004
#define AR6320_CE_CTRL1_ADDRESS 0x0010
#define AR6320_CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff
#define AR6320_DR_BA_ADDRESS 0x0008
#define AR6320_DR_SIZE_ADDRESS 0x000c
#define AR6320_MISC_IE_ADDRESS 0x0034
@@ -177,41 +202,18 @@
#define AR6320_SRC_WATERMARK_HIGH_LSB 0
#define AR6320_DST_WATERMARK_LOW_LSB 16
#define AR6320_DST_WATERMARK_HIGH_LSB 0
#define AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00
#define AR6320_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8
#define AR6320_CE_CTRL1_DMAX_LENGTH_LSB 0
#define AR6320_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000
#define AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000
#define AR6320_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16
#define AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17
#define AR6320_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000020
#define AR6320_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB 5
#define AR6320_SOC_GLOBAL_RESET_ADDRESS 0x0008
#define AR6320_RTC_STATE_ADDRESS 0x0000
#define AR6320_RTC_STATE_COLD_RESET_MASK 0x00002000
#define AR6320_PCIE_SOC_WAKE_RESET 0x00000000
#define AR6320_PCIE_SOC_WAKE_ADDRESS 0x0004
#define AR6320_PCIE_SOC_WAKE_V_MASK 0x00000001
#define AR6320_RTC_STATE_V_MASK 0x00000007
#define AR6320_RTC_STATE_V_LSB 0
#define AR6320_RTC_STATE_V_ON 3
#define AR6320_MUX_ID_MASK 0x0000
#define AR6320_TRANSACTION_ID_MASK 0x3fff
#define AR6320_PCIE_LOCAL_BASE_ADDRESS 0x80000
#define AR6320_FW_IND_EVENT_PENDING 1
#define AR6320_FW_IND_INITIALIZED 2
#define AR6320_FW_IND_HELPER 4
#define AR6320_PCIE_INTR_ENABLE_ADDRESS 0x0008
#define AR6320_PCIE_INTR_CLR_ADDRESS 0x0014
#define AR6320_PCIE_INTR_FIRMWARE_MASK 0x00000400
#define AR6320_PCIE_INTR_CE0_MASK 0x00000800
#define AR6320_PCIE_INTR_CE_MASK_ALL 0x0007f800
#define AR6320_PCIE_INTR_CAUSE_ADDRESS 0x000c
#define AR6320_CPU_INTR_ADDRESS 0x0010
#define AR6320_SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050
#define AR6320_SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
#define AR6320_SOC_RESET_CONTROL_ADDRESS 0x00000000
#define AR6320_SOC_RESET_CONTROL_CE_RST_MASK 0x00000001
#define AR6320_SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
#define AR6320_CORE_CTRL_ADDRESS 0x0000
#define AR6320_CORE_CTRL_CPU_INTR_MASK 0x00002000
@@ -224,8 +226,8 @@
#define AR6320_SOC_CHIP_ID_VERSION_LSB 18
#define AR6320_SOC_CHIP_ID_REVISION_MASK 0x00000f00
#define AR6320_SOC_CHIP_ID_REVISION_LSB 8
#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
#define AR6320_SOC_POWER_REG_OFFSET 0x0000010c
/* Copy Engine Debug */
#define AR6320_WLAN_DEBUG_INPUT_SEL_OFFSET 0x0000010c
#define AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MSB 3
@@ -312,9 +314,9 @@
#define AR6320_SOC_CPU_CLOCK_STANDARD_LSB 0
#define AR6320_SOC_CPU_CLOCK_STANDARD_MASK 0x00000003
/* PLL end */
#define AR6320_PCIE_INTR_CE_MASK(n) \
(AR6320_PCIE_INTR_CE0_MASK << (n))
#endif
#define AR6320_DRAM_BASE_ADDRESS AR6320_TARG_DRAM_START
#define AR6320_FW_INDICATOR_ADDRESS \
(AR6320_SOC_CORE_BASE_ADDRESS + AR6320_SCRATCH_3_ADDRESS)
@@ -380,6 +382,8 @@
#define AR6320_WINDOW_DATA_ADDRESS 0x0874
#define AR6320_WINDOW_READ_ADDR_ADDRESS 0x087c
#define AR6320_WINDOW_WRITE_ADDR_ADDRESS 0x0878
#define AR6320_HOST_INT_STATUS_MBOX_DATA_MASK 0x0f
#define AR6320_HOST_INT_STATUS_MBOX_DATA_LSB 0
struct targetdef_s ar6320_targetdef = {
.d_RTC_SOC_BASE_ADDRESS = AR6320_RTC_SOC_BASE_ADDRESS,
@@ -456,14 +460,8 @@ struct targetdef_s ar6320_targetdef = {
.d_DRAM_BASE_ADDRESS = AR6320_DRAM_BASE_ADDRESS,
.d_SOC_CORE_BASE_ADDRESS = AR6320_SOC_CORE_BASE_ADDRESS,
.d_CORE_CTRL_ADDRESS = AR6320_CORE_CTRL_ADDRESS,
.d_CE_COUNT = AR6320_CE_COUNT,
.d_MSI_NUM_REQUEST = MSI_NUM_REQUEST,
.d_MSI_ASSIGN_FW = MSI_ASSIGN_FW,
.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
.d_PCIE_INTR_ENABLE_ADDRESS = AR6320_PCIE_INTR_ENABLE_ADDRESS,
.d_PCIE_INTR_CLR_ADDRESS = AR6320_PCIE_INTR_CLR_ADDRESS,
.d_PCIE_INTR_FIRMWARE_MASK = AR6320_PCIE_INTR_FIRMWARE_MASK,
.d_PCIE_INTR_CE_MASK_ALL = AR6320_PCIE_INTR_CE_MASK_ALL,
.d_CORE_CTRL_CPU_INTR_MASK = AR6320_CORE_CTRL_CPU_INTR_MASK,
.d_SR_WR_INDEX_ADDRESS = AR6320_SR_WR_INDEX_ADDRESS,
.d_DST_WATERMARK_ADDRESS = AR6320_DST_WATERMARK_ADDRESS,
@@ -521,6 +519,13 @@ struct targetdef_s ar6320_targetdef = {
AR6320_RX_ATTENTION_0_MSDU_DONE_MASK,
.d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK =
AR6320_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK,
#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
.d_CE_COUNT = AR6320_CE_COUNT,
.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
.d_PCIE_INTR_ENABLE_ADDRESS = AR6320_PCIE_INTR_ENABLE_ADDRESS,
.d_PCIE_INTR_CLR_ADDRESS = AR6320_PCIE_INTR_CLR_ADDRESS,
.d_PCIE_INTR_FIRMWARE_MASK = AR6320_PCIE_INTR_FIRMWARE_MASK,
.d_PCIE_INTR_CE_MASK_ALL = AR6320_PCIE_INTR_CE_MASK_ALL,
/* PLL start */
.d_EFUSE_OFFSET = AR6320_EFUSE_OFFSET,
.d_EFUSE_XTAL_SEL_MSB = AR6320_EFUSE_XTAL_SEL_MSB,
@@ -601,13 +606,6 @@ struct targetdef_s ar6320_targetdef = {
AR6320_SOC_LF_TIMER_CONTROL0_ADDRESS,
.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
AR6320_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
/* chip id start */
.d_SOC_CHIP_ID_ADDRESS = AR6320_SOC_CHIP_ID_ADDRESS,
.d_SOC_CHIP_ID_VERSION_MASK = AR6320_SOC_CHIP_ID_VERSION_MASK,
.d_SOC_CHIP_ID_VERSION_LSB = AR6320_SOC_CHIP_ID_VERSION_LSB,
.d_SOC_CHIP_ID_REVISION_MASK = AR6320_SOC_CHIP_ID_REVISION_MASK,
.d_SOC_CHIP_ID_REVISION_LSB = AR6320_SOC_CHIP_ID_REVISION_LSB,
/* chip id end */
.d_WLAN_DEBUG_INPUT_SEL_OFFSET = AR6320_WLAN_DEBUG_INPUT_SEL_OFFSET,
.d_WLAN_DEBUG_INPUT_SEL_SRC_MSB = AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MSB,
@@ -635,7 +633,14 @@ struct targetdef_s ar6320_targetdef = {
.d_AMBA_DEBUG_BUS_SEL_MSB = AR6320_AMBA_DEBUG_BUS_SEL_MSB,
.d_AMBA_DEBUG_BUS_SEL_LSB = AR6320_AMBA_DEBUG_BUS_SEL_LSB,
.d_AMBA_DEBUG_BUS_SEL_MASK = AR6320_AMBA_DEBUG_BUS_SEL_MASK,
#endif
/* chip id start */
.d_SOC_CHIP_ID_ADDRESS = AR6320_SOC_CHIP_ID_ADDRESS,
.d_SOC_CHIP_ID_VERSION_MASK = AR6320_SOC_CHIP_ID_VERSION_MASK,
.d_SOC_CHIP_ID_VERSION_LSB = AR6320_SOC_CHIP_ID_VERSION_LSB,
.d_SOC_CHIP_ID_REVISION_MASK = AR6320_SOC_CHIP_ID_REVISION_MASK,
.d_SOC_CHIP_ID_REVISION_LSB = AR6320_SOC_CHIP_ID_REVISION_LSB,
/* chip id end */
};
struct hostdef_s ar6320_hostdef = {
@@ -695,24 +700,14 @@ struct hostdef_s ar6320_hostdef = {
.d_SOC_GLOBAL_RESET_ADDRESS = AR6320_SOC_GLOBAL_RESET_ADDRESS,
.d_RTC_STATE_ADDRESS = AR6320_RTC_STATE_ADDRESS,
.d_RTC_STATE_COLD_RESET_MASK = AR6320_RTC_STATE_COLD_RESET_MASK,
#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
.d_PCIE_LOCAL_BASE_ADDRESS = AR6320_PCIE_LOCAL_BASE_ADDRESS,
.d_PCIE_SOC_WAKE_RESET = AR6320_PCIE_SOC_WAKE_RESET,
.d_PCIE_SOC_WAKE_ADDRESS = AR6320_PCIE_SOC_WAKE_ADDRESS,
.d_PCIE_SOC_WAKE_V_MASK = AR6320_PCIE_SOC_WAKE_V_MASK,
.d_RTC_STATE_V_MASK = AR6320_RTC_STATE_V_MASK,
.d_RTC_STATE_V_LSB = AR6320_RTC_STATE_V_LSB,
.d_FW_IND_EVENT_PENDING = AR6320_FW_IND_EVENT_PENDING,
.d_FW_IND_INITIALIZED = AR6320_FW_IND_INITIALIZED,
.d_FW_IND_HELPER = AR6320_FW_IND_HELPER,
.d_RTC_STATE_V_ON = AR6320_RTC_STATE_V_ON,
.d_MUX_ID_MASK = AR6320_MUX_ID_MASK,
.d_TRANSACTION_ID_MASK = AR6320_TRANSACTION_ID_MASK,
#if defined(SDIO_3_0)
.d_HOST_INT_STATUS_MBOX_DATA_MASK =
AR6320_HOST_INT_STATUS_MBOX_DATA_MASK,
.d_HOST_INT_STATUS_MBOX_DATA_LSB =
AR6320_HOST_INT_STATUS_MBOX_DATA_LSB,
#endif
.d_FW_IND_HELPER = AR6320_FW_IND_HELPER,
.d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS,
.d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK,
.d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS,
@@ -720,9 +715,21 @@ struct hostdef_s ar6320_hostdef = {
.d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS,
.d_HOST_CE_COUNT = 8,
.d_ENABLE_MSI = 0,
#endif
.d_RTC_STATE_V_MASK = AR6320_RTC_STATE_V_MASK,
.d_RTC_STATE_V_LSB = AR6320_RTC_STATE_V_LSB,
.d_FW_IND_EVENT_PENDING = AR6320_FW_IND_EVENT_PENDING,
.d_FW_IND_INITIALIZED = AR6320_FW_IND_INITIALIZED,
.d_RTC_STATE_V_ON = AR6320_RTC_STATE_V_ON,
#if defined(SDIO_3_0)
.d_HOST_INT_STATUS_MBOX_DATA_MASK =
AR6320_HOST_INT_STATUS_MBOX_DATA_MASK,
.d_HOST_INT_STATUS_MBOX_DATA_LSB =
AR6320_HOST_INT_STATUS_MBOX_DATA_LSB,
#endif
};
#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
struct ce_reg_def ar6320_ce_targetdef = {
/* copy_engine.c */
.d_DST_WR_INDEX_ADDRESS = AR6320_DST_WR_INDEX_ADDRESS,
@@ -792,5 +799,5 @@ struct ce_reg_def ar6320_ce_targetdef = {
.d_CE1_BASE_ADDRESS = AR6320_CE1_BASE_ADDRESS,
};
#endif
#endif

141
hif/src/ar6320v2def.h
Wyświetl plik

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2013-2015 The Linux Foundation. All rights reserved.
* Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -43,17 +43,7 @@
#define AR6320V2_EFUSE_BASE_ADDRESS 0x00024000
#define AR6320V2_FPGA_REG_BASE_ADDRESS 0x00039000
#define AR6320V2_WLAN_UART2_BASE_ADDRESS 0x00054c00
#define AR6320V2_CE_WRAPPER_BASE_ADDRESS 0x00034000
#define AR6320V2_CE0_BASE_ADDRESS 0x00034400
#define AR6320V2_CE1_BASE_ADDRESS 0x00034800
#define AR6320V2_CE2_BASE_ADDRESS 0x00034c00
#define AR6320V2_CE3_BASE_ADDRESS 0x00035000
#define AR6320V2_CE4_BASE_ADDRESS 0x00035400
#define AR6320V2_CE5_BASE_ADDRESS 0x00035800
#define AR6320V2_CE6_BASE_ADDRESS 0x00035c00
#define AR6320V2_CE7_BASE_ADDRESS 0x00036000
#define AR6320V2_DBI_BASE_ADDRESS 0x0003c000
#define AR6320V2_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x00007800
#define AR6320V2_SCRATCH_3_ADDRESS 0x0028
#define AR6320V2_TARG_DRAM_START 0x00400000
@@ -156,13 +146,10 @@
#define AR6320V2_HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010
#define AR6320V2_HOST_IS_ADDRESS 0x0030
#define AR6320V2_HOST_IS_COPY_COMPLETE_MASK 0x00000001
#define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
#define AR6320V2_HOST_IE_ADDRESS 0x002c
#define AR6320V2_HOST_IE_COPY_COMPLETE_MASK 0x00000001
#define AR6320V2_SR_BA_ADDRESS 0x0000
#define AR6320V2_SR_SIZE_ADDRESS 0x0004
#define AR6320V2_CE_CTRL1_ADDRESS 0x0010
#define AR6320V2_CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff
#define AR6320V2_DR_BA_ADDRESS 0x0008
#define AR6320V2_DR_SIZE_ADDRESS 0x000c
#define AR6320V2_MISC_IE_ADDRESS 0x0034
@@ -176,41 +163,18 @@
#define AR6320V2_SRC_WATERMARK_HIGH_LSB 0
#define AR6320V2_DST_WATERMARK_LOW_LSB 16
#define AR6320V2_DST_WATERMARK_HIGH_LSB 0
#define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00
#define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8
#define AR6320V2_CE_CTRL1_DMAX_LENGTH_LSB 0
#define AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000
#define AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000
#define AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16
#define AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17
#define AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000020
#define AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB 5
#define AR6320V2_SOC_GLOBAL_RESET_ADDRESS 0x0008
#define AR6320V2_RTC_STATE_ADDRESS 0x0000
#define AR6320V2_RTC_STATE_COLD_RESET_MASK 0x00002000
#define AR6320V2_PCIE_SOC_WAKE_RESET 0x00000000
#define AR6320V2_PCIE_SOC_WAKE_ADDRESS 0x0004
#define AR6320V2_PCIE_SOC_WAKE_V_MASK 0x00000001
#define AR6320V2_RTC_STATE_V_MASK 0x00000007
#define AR6320V2_RTC_STATE_V_LSB 0
#define AR6320V2_RTC_STATE_V_ON 3
#define AR6320V2_MUX_ID_MASK 0x0000
#define AR6320V2_TRANSACTION_ID_MASK 0x3fff
#define AR6320V2_PCIE_LOCAL_BASE_ADDRESS 0x80000
#define AR6320V2_FW_IND_EVENT_PENDING 1
#define AR6320V2_FW_IND_INITIALIZED 2
#define AR6320V2_FW_IND_HELPER 4
#define AR6320V2_PCIE_INTR_ENABLE_ADDRESS 0x0008
#define AR6320V2_PCIE_INTR_CLR_ADDRESS 0x0014
#define AR6320V2_PCIE_INTR_FIRMWARE_MASK 0x00000400
#define AR6320V2_PCIE_INTR_CE0_MASK 0x00000800
#define AR6320V2_PCIE_INTR_CE_MASK_ALL 0x0007f800
#define AR6320V2_PCIE_INTR_CAUSE_ADDRESS 0x000c
#define AR6320V2_CPU_INTR_ADDRESS 0x0010
#define AR6320V2_SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050
#define AR6320V2_SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
#define AR6320V2_SOC_RESET_CONTROL_ADDRESS 0x00000000
#define AR6320V2_SOC_RESET_CONTROL_CE_RST_MASK 0x00000001
#define AR6320V2_SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
#define AR6320V2_CORE_CTRL_ADDRESS 0x0000
#define AR6320V2_CORE_CTRL_CPU_INTR_MASK 0x00002000
@@ -223,8 +187,44 @@
#define AR6320V2_SOC_CHIP_ID_VERSION_LSB 18
#define AR6320V2_SOC_CHIP_ID_REVISION_MASK 0x00000f00
#define AR6320V2_SOC_CHIP_ID_REVISION_LSB 8
#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
#define AR6320V2_CE_WRAPPER_BASE_ADDRESS 0x00034000
#define AR6320V2_CE0_BASE_ADDRESS 0x00034400
#define AR6320V2_CE1_BASE_ADDRESS 0x00034800
#define AR6320V2_CE2_BASE_ADDRESS 0x00034c00
#define AR6320V2_CE3_BASE_ADDRESS 0x00035000
#define AR6320V2_CE4_BASE_ADDRESS 0x00035400
#define AR6320V2_CE5_BASE_ADDRESS 0x00035800
#define AR6320V2_CE6_BASE_ADDRESS 0x00035c00
#define AR6320V2_CE7_BASE_ADDRESS 0x00036000
#define AR6320V2_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x00007800
#define AR6320V2_CE_CTRL1_ADDRESS 0x0010
#define AR6320V2_CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff
#define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
#define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00
#define AR6320V2_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8
#define AR6320V2_CE_CTRL1_DMAX_LENGTH_LSB 0
#define AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000
#define AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000
#define AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16
#define AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17
#define AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000020
#define AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB 5
#define AR6320V2_PCIE_SOC_WAKE_RESET 0x00000000
#define AR6320V2_PCIE_SOC_WAKE_ADDRESS 0x0004
#define AR6320V2_PCIE_SOC_WAKE_V_MASK 0x00000001
#define AR6320V2_MUX_ID_MASK 0x0000
#define AR6320V2_TRANSACTION_ID_MASK 0x3fff
#define AR6320V2_PCIE_LOCAL_BASE_ADDRESS 0x80000
#define AR6320V2_FW_IND_HELPER 4
#define AR6320V2_PCIE_INTR_ENABLE_ADDRESS 0x0008
#define AR6320V2_PCIE_INTR_CLR_ADDRESS 0x0014
#define AR6320V2_PCIE_INTR_FIRMWARE_MASK 0x00000400
#define AR6320V2_PCIE_INTR_CE0_MASK 0x00000800
#define AR6320V2_PCIE_INTR_CE_MASK_ALL 0x0007f800
#define AR6320V2_PCIE_INTR_CAUSE_ADDRESS 0x000c
#define AR6320V2_SOC_RESET_CONTROL_CE_RST_MASK 0x00000001
#define AR6320V2_SOC_POWER_REG_OFFSET 0x0000010c
/* Copy Engine Debug */
#define AR6320V2_WLAN_DEBUG_INPUT_SEL_OFFSET 0x0000010c
#define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MSB 3
@@ -314,6 +314,7 @@
#define AR6320V2_PCIE_INTR_CE_MASK(n) \
(AR6320V2_PCIE_INTR_CE0_MASK << (n))
#endif
#define AR6320V2_DRAM_BASE_ADDRESS AR6320V2_TARG_DRAM_START
#define AR6320V2_FW_INDICATOR_ADDRESS \
(AR6320V2_SOC_CORE_BASE_ADDRESS + AR6320V2_SCRATCH_3_ADDRESS)
@@ -382,6 +383,8 @@
#define AR6320V2_WINDOW_DATA_ADDRESS 0x0874
#define AR6320V2_WINDOW_READ_ADDR_ADDRESS 0x087c
#define AR6320V2_WINDOW_WRITE_ADDR_ADDRESS 0x0878
#define AR6320V2_HOST_INT_STATUS_MBOX_DATA_MASK 0x0f
#define AR6320V2_HOST_INT_STATUS_MBOX_DATA_LSB 0
struct targetdef_s ar6320v2_targetdef = {
.d_RTC_SOC_BASE_ADDRESS = AR6320V2_RTC_SOC_BASE_ADDRESS,
@@ -461,14 +464,8 @@ struct targetdef_s ar6320v2_targetdef = {
.d_DRAM_BASE_ADDRESS = AR6320V2_DRAM_BASE_ADDRESS,
.d_SOC_CORE_BASE_ADDRESS = AR6320V2_SOC_CORE_BASE_ADDRESS,
.d_CORE_CTRL_ADDRESS = AR6320V2_CORE_CTRL_ADDRESS,
.d_CE_COUNT = AR6320V2_CE_COUNT,
.d_MSI_NUM_REQUEST = MSI_NUM_REQUEST,
.d_MSI_ASSIGN_FW = MSI_ASSIGN_FW,
.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
.d_PCIE_INTR_ENABLE_ADDRESS = AR6320V2_PCIE_INTR_ENABLE_ADDRESS,
.d_PCIE_INTR_CLR_ADDRESS = AR6320V2_PCIE_INTR_CLR_ADDRESS,
.d_PCIE_INTR_FIRMWARE_MASK = AR6320V2_PCIE_INTR_FIRMWARE_MASK,
.d_PCIE_INTR_CE_MASK_ALL = AR6320V2_PCIE_INTR_CE_MASK_ALL,
.d_CORE_CTRL_CPU_INTR_MASK = AR6320V2_CORE_CTRL_CPU_INTR_MASK,
.d_SR_WR_INDEX_ADDRESS = AR6320V2_SR_WR_INDEX_ADDRESS,
.d_DST_WATERMARK_ADDRESS = AR6320V2_DST_WATERMARK_ADDRESS,
@@ -532,6 +529,13 @@ struct targetdef_s ar6320v2_targetdef = {
AR6320V2_RX_ATTENTION_0_MSDU_DONE_MASK,
.d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK =
AR6320V2_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK,
#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
.d_CE_COUNT = AR6320V2_CE_COUNT,
.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
.d_PCIE_INTR_ENABLE_ADDRESS = AR6320V2_PCIE_INTR_ENABLE_ADDRESS,
.d_PCIE_INTR_CLR_ADDRESS = AR6320V2_PCIE_INTR_CLR_ADDRESS,
.d_PCIE_INTR_FIRMWARE_MASK = AR6320V2_PCIE_INTR_FIRMWARE_MASK,
.d_PCIE_INTR_CE_MASK_ALL = AR6320V2_PCIE_INTR_CE_MASK_ALL,
/* PLL start */
.d_EFUSE_OFFSET = AR6320V2_EFUSE_OFFSET,
.d_EFUSE_XTAL_SEL_MSB = AR6320V2_EFUSE_XTAL_SEL_MSB,
@@ -609,21 +613,6 @@ struct targetdef_s ar6320v2_targetdef = {
AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB,
.d_SOC_RESET_CONTROL_CE_RST_MASK =
AR6320V2_SOC_RESET_CONTROL_CE_RST_MASK,
.d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK =
AR6320V2_SOC_RESET_CONTROL_CPU_WARM_RST_MASK,
.d_CPU_INTR_ADDRESS = AR6320V2_CPU_INTR_ADDRESS,
.d_SOC_LF_TIMER_CONTROL0_ADDRESS =
AR6320V2_SOC_LF_TIMER_CONTROL0_ADDRESS,
.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
AR6320V2_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
/* chip id start */
.d_SOC_CHIP_ID_ADDRESS = AR6320V2_SOC_CHIP_ID_ADDRESS,
.d_SOC_CHIP_ID_VERSION_MASK = AR6320V2_SOC_CHIP_ID_VERSION_MASK,
.d_SOC_CHIP_ID_VERSION_LSB = AR6320V2_SOC_CHIP_ID_VERSION_LSB,
.d_SOC_CHIP_ID_REVISION_MASK = AR6320V2_SOC_CHIP_ID_REVISION_MASK,
.d_SOC_CHIP_ID_REVISION_LSB = AR6320V2_SOC_CHIP_ID_REVISION_LSB,
/* chip id end */
.d_WLAN_DEBUG_INPUT_SEL_OFFSET = AR6320V2_WLAN_DEBUG_INPUT_SEL_OFFSET,
.d_WLAN_DEBUG_INPUT_SEL_SRC_MSB =
AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MSB,
@@ -652,6 +641,21 @@ struct targetdef_s ar6320v2_targetdef = {
.d_AMBA_DEBUG_BUS_SEL_MSB = AR6320V2_AMBA_DEBUG_BUS_SEL_MSB,
.d_AMBA_DEBUG_BUS_SEL_LSB = AR6320V2_AMBA_DEBUG_BUS_SEL_LSB,
.d_AMBA_DEBUG_BUS_SEL_MASK = AR6320V2_AMBA_DEBUG_BUS_SEL_MASK,
#endif
.d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK =
AR6320V2_SOC_RESET_CONTROL_CPU_WARM_RST_MASK,
.d_CPU_INTR_ADDRESS = AR6320V2_CPU_INTR_ADDRESS,
.d_SOC_LF_TIMER_CONTROL0_ADDRESS =
AR6320V2_SOC_LF_TIMER_CONTROL0_ADDRESS,
.d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK =
AR6320V2_SOC_LF_TIMER_CONTROL0_ENABLE_MASK,
/* chip id start */
.d_SOC_CHIP_ID_ADDRESS = AR6320V2_SOC_CHIP_ID_ADDRESS,
.d_SOC_CHIP_ID_VERSION_MASK = AR6320V2_SOC_CHIP_ID_VERSION_MASK,
.d_SOC_CHIP_ID_VERSION_LSB = AR6320V2_SOC_CHIP_ID_VERSION_LSB,
.d_SOC_CHIP_ID_REVISION_MASK = AR6320V2_SOC_CHIP_ID_REVISION_MASK,
.d_SOC_CHIP_ID_REVISION_LSB = AR6320V2_SOC_CHIP_ID_REVISION_LSB,
/* chip id end */
};
struct hostdef_s ar6320v2_hostdef = {
@@ -714,24 +718,25 @@ struct hostdef_s ar6320v2_hostdef = {
.d_SOC_GLOBAL_RESET_ADDRESS = AR6320V2_SOC_GLOBAL_RESET_ADDRESS,
.d_RTC_STATE_ADDRESS = AR6320V2_RTC_STATE_ADDRESS,
.d_RTC_STATE_COLD_RESET_MASK = AR6320V2_RTC_STATE_COLD_RESET_MASK,
.d_PCIE_LOCAL_BASE_ADDRESS = AR6320V2_PCIE_LOCAL_BASE_ADDRESS,
.d_PCIE_SOC_WAKE_RESET = AR6320V2_PCIE_SOC_WAKE_RESET,
.d_PCIE_SOC_WAKE_ADDRESS = AR6320V2_PCIE_SOC_WAKE_ADDRESS,
.d_PCIE_SOC_WAKE_V_MASK = AR6320V2_PCIE_SOC_WAKE_V_MASK,
.d_RTC_STATE_V_MASK = AR6320V2_RTC_STATE_V_MASK,
.d_RTC_STATE_V_LSB = AR6320V2_RTC_STATE_V_LSB,
.d_FW_IND_EVENT_PENDING = AR6320V2_FW_IND_EVENT_PENDING,
.d_FW_IND_INITIALIZED = AR6320V2_FW_IND_INITIALIZED,
.d_FW_IND_HELPER = AR6320V2_FW_IND_HELPER,
.d_RTC_STATE_V_ON = AR6320V2_RTC_STATE_V_ON,
.d_MUX_ID_MASK = AR6320V2_MUX_ID_MASK,
.d_TRANSACTION_ID_MASK = AR6320V2_TRANSACTION_ID_MASK,
#if defined(SDIO_3_0)
.d_HOST_INT_STATUS_MBOX_DATA_MASK =
AR6320V2_HOST_INT_STATUS_MBOX_DATA_MASK,
.d_HOST_INT_STATUS_MBOX_DATA_LSB =
AR6320V2_HOST_INT_STATUS_MBOX_DATA_LSB,
#endif
#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
.d_FW_IND_HELPER = AR6320V2_FW_IND_HELPER,
.d_MUX_ID_MASK = AR6320V2_MUX_ID_MASK,
.d_TRANSACTION_ID_MASK = AR6320V2_TRANSACTION_ID_MASK,
.d_PCIE_LOCAL_BASE_ADDRESS = AR6320V2_PCIE_LOCAL_BASE_ADDRESS,
.d_PCIE_SOC_WAKE_RESET = AR6320V2_PCIE_SOC_WAKE_RESET,
.d_PCIE_SOC_WAKE_ADDRESS = AR6320V2_PCIE_SOC_WAKE_ADDRESS,
.d_PCIE_SOC_WAKE_V_MASK = AR6320V2_PCIE_SOC_WAKE_V_MASK,
.d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS,
.d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK,
.d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS,
@@ -739,8 +744,10 @@ struct hostdef_s ar6320v2_hostdef = {
.d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS,
.d_HOST_CE_COUNT = 8,
.d_ENABLE_MSI = 0,
#endif
};
#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
struct ce_reg_def ar6320v2_ce_targetdef = {
/* copy_engine.c */
.d_DST_WR_INDEX_ADDRESS = AR6320V2_DST_WR_INDEX_ADDRESS,
@@ -811,5 +818,5 @@ struct ce_reg_def ar6320v2_ce_targetdef = {
.d_CE1_BASE_ADDRESS = AR6320V2_CE1_BASE_ADDRESS,
};
#endif
#endif

94
hif/src/ar9888def.h
Wyświetl plik

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2011-2015 The Linux Foundation. All rights reserved.
* Copyright (c) 2011-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -43,6 +43,7 @@
#define AR9888_EFUSE_BASE_ADDRESS 0x00030000
#define AR9888_FPGA_REG_BASE_ADDRESS 0x00039000
#define AR9888_WLAN_UART2_BASE_ADDRESS 0x00054c00
#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
#define AR9888_CE_WRAPPER_BASE_ADDRESS 0x00057000
#define AR9888_CE0_BASE_ADDRESS 0x00057400
#define AR9888_CE1_BASE_ADDRESS 0x00057800
@@ -52,9 +53,35 @@
#define AR9888_CE5_BASE_ADDRESS 0x00058800
#define AR9888_CE6_BASE_ADDRESS 0x00058c00
#define AR9888_CE7_BASE_ADDRESS 0x00059000
#define AR9888_DBI_BASE_ADDRESS 0x00060000
#define AR9888_WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000
#define AR9888_CE_CTRL1_ADDRESS 0x0010
#define AR9888_CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff
#define AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
#define AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00
#define AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8
#define AR9888_CE_CTRL1_DMAX_LENGTH_LSB 0
#define AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000
#define AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000
#define AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16
#define AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17
#define AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000004
#define AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB 2
#define AR9888_PCIE_SOC_WAKE_RESET 0x00000000
#define AR9888_PCIE_SOC_WAKE_ADDRESS 0x0004
#define AR9888_PCIE_SOC_WAKE_V_MASK 0x00000001
#define AR9888_PCIE_INTR_ENABLE_ADDRESS 0x0008
#define AR9888_PCIE_INTR_CLR_ADDRESS 0x0014
#define AR9888_PCIE_INTR_FIRMWARE_MASK 0x00000400
#define AR9888_PCIE_INTR_CE0_MASK 0x00000800
#define AR9888_PCIE_INTR_CE_MASK_ALL 0x0007f800
#define AR9888_PCIE_INTR_CAUSE_ADDRESS 0x000c
#define AR9888_MUX_ID_MASK 0x0000
#define AR9888_TRANSACTION_ID_MASK 0x3fff
#define AR9888_PCIE_LOCAL_BASE_ADDRESS 0x80000
#define AR9888_SOC_RESET_CONTROL_CE_RST_MASK 0x00040000
#define AR9888_PCIE_INTR_CE_MASK(n) (AR9888_PCIE_INTR_CE0_MASK << (n))
#endif
#define AR9888_DBI_BASE_ADDRESS 0x00060000
#define AR9888_SCRATCH_3_ADDRESS 0x0030
#define AR9888_TARG_DRAM_START 0x00400000
#define AR9888_SOC_SYSTEM_SLEEP_OFFSET 0x000000c4
@@ -156,13 +183,10 @@
#define AR9888_HOST_IS_DST_RING_LOW_WATERMARK_MASK 0x00000010
#define AR9888_HOST_IS_ADDRESS 0x0030
#define AR9888_HOST_IS_COPY_COMPLETE_MASK 0x00000001
#define AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
#define AR9888_HOST_IE_ADDRESS 0x002c
#define AR9888_HOST_IE_COPY_COMPLETE_MASK 0x00000001
#define AR9888_SR_BA_ADDRESS 0x0000
#define AR9888_SR_SIZE_ADDRESS 0x0004
#define AR9888_CE_CTRL1_ADDRESS 0x0010
#define AR9888_CE_CTRL1_DMAX_LENGTH_MASK 0x0000ffff
#define AR9888_DR_BA_ADDRESS 0x0008
#define AR9888_DR_SIZE_ADDRESS 0x000c
#define AR9888_MISC_IE_ADDRESS 0x0034
@@ -176,40 +200,19 @@
#define AR9888_SRC_WATERMARK_HIGH_LSB 0
#define AR9888_DST_WATERMARK_LOW_LSB 16
#define AR9888_DST_WATERMARK_HIGH_LSB 0
#define AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK 0x0000ff00
#define AR9888_CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB 8
#define AR9888_CE_CTRL1_DMAX_LENGTH_LSB 0
#define AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK 0x00010000
#define AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK 0x00020000
#define AR9888_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB 16
#define AR9888_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB 17
#define AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK 0x00000004
#define AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB 2
#define AR9888_SOC_GLOBAL_RESET_ADDRESS 0x0008
#define AR9888_RTC_STATE_ADDRESS 0x0000
#define AR9888_RTC_STATE_COLD_RESET_MASK 0x00000400
#define AR9888_PCIE_SOC_WAKE_RESET 0x00000000
#define AR9888_PCIE_SOC_WAKE_ADDRESS 0x0004
#define AR9888_PCIE_SOC_WAKE_V_MASK 0x00000001
#define AR9888_RTC_STATE_V_MASK 0x00000007
#define AR9888_RTC_STATE_V_LSB 0
#define AR9888_RTC_STATE_V_ON 3
#define AR9888_MUX_ID_MASK 0x0000
#define AR9888_TRANSACTION_ID_MASK 0x3fff
#define AR9888_PCIE_LOCAL_BASE_ADDRESS 0x80000
#define AR9888_FW_IND_EVENT_PENDING 1
#define AR9888_FW_IND_INITIALIZED 2
#define AR9888_PCIE_INTR_ENABLE_ADDRESS 0x0008
#define AR9888_PCIE_INTR_CLR_ADDRESS 0x0014
#define AR9888_PCIE_INTR_FIRMWARE_MASK 0x00000400
#define AR9888_PCIE_INTR_CE0_MASK 0x00000800
#define AR9888_PCIE_INTR_CE_MASK_ALL 0x0007f800
#define AR9888_PCIE_INTR_CAUSE_ADDRESS 0x000c
#define AR9888_CPU_INTR_ADDRESS 0x0010
#define AR9888_SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050
#define AR9888_SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
#define AR9888_SOC_RESET_CONTROL_ADDRESS 0x00000000
#define AR9888_SOC_RESET_CONTROL_CE_RST_MASK 0x00040000
#define AR9888_SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
#define AR9888_CORE_CTRL_ADDRESS 0x0000
#define AR9888_CORE_CTRL_CPU_INTR_MASK 0x00002000
@@ -218,7 +221,6 @@
#define AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0
#define AR9888_CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0
#define AR9888_PCIE_INTR_CE_MASK(n) (AR9888_PCIE_INTR_CE0_MASK << (n))
#define AR9888_FW_EVENT_PENDING_ADDRESS \
(AR9888_SOC_CORE_BASE_ADDRESS + AR9888_SCRATCH_3_ADDRESS)
#define AR9888_DRAM_BASE_ADDRESS AR9888_TARG_DRAM_START
@@ -287,6 +289,8 @@
#define AR9888_WINDOW_DATA_ADDRESS MISSING
#define AR9888_WINDOW_READ_ADDR_ADDRESS MISSING
#define AR9888_WINDOW_WRITE_ADDR_ADDRESS MISSING
#define AR9888_HOST_INT_STATUS_MBOX_DATA_MASK 0x0f
#define AR9888_HOST_INT_STATUS_MBOX_DATA_LSB 0
struct targetdef_s ar9888_targetdef = {
.d_RTC_SOC_BASE_ADDRESS = AR9888_RTC_SOC_BASE_ADDRESS,
@@ -363,14 +367,8 @@ struct targetdef_s ar9888_targetdef = {
.d_DRAM_BASE_ADDRESS = AR9888_DRAM_BASE_ADDRESS,
.d_SOC_CORE_BASE_ADDRESS = AR9888_SOC_CORE_BASE_ADDRESS,
.d_CORE_CTRL_ADDRESS = AR9888_CORE_CTRL_ADDRESS,
.d_CE_COUNT = AR9888_CE_COUNT,
.d_MSI_NUM_REQUEST = MSI_NUM_REQUEST,
.d_MSI_ASSIGN_FW = MSI_ASSIGN_FW,
.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
.d_PCIE_INTR_ENABLE_ADDRESS = AR9888_PCIE_INTR_ENABLE_ADDRESS,
.d_PCIE_INTR_CLR_ADDRESS = AR9888_PCIE_INTR_CLR_ADDRESS,
.d_PCIE_INTR_FIRMWARE_MASK = AR9888_PCIE_INTR_FIRMWARE_MASK,
.d_PCIE_INTR_CE_MASK_ALL = AR9888_PCIE_INTR_CE_MASK_ALL,
.d_CORE_CTRL_CPU_INTR_MASK = AR9888_CORE_CTRL_CPU_INTR_MASK,
.d_SR_WR_INDEX_ADDRESS = AR9888_SR_WR_INDEX_ADDRESS,
.d_DST_WATERMARK_ADDRESS = AR9888_DST_WATERMARK_ADDRESS,
@@ -424,7 +422,13 @@ struct targetdef_s ar9888_targetdef = {
AR9888_RX_ATTENTION_0_MSDU_DONE_MASK,
.d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK =
AR9888_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK,
#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
.d_CE_COUNT = AR9888_CE_COUNT,
.d_MSI_ASSIGN_CE_INITIAL = MSI_ASSIGN_CE_INITIAL,
.d_PCIE_INTR_ENABLE_ADDRESS = AR9888_PCIE_INTR_ENABLE_ADDRESS,
.d_PCIE_INTR_CLR_ADDRESS = AR9888_PCIE_INTR_CLR_ADDRESS,
.d_PCIE_INTR_FIRMWARE_MASK = AR9888_PCIE_INTR_FIRMWARE_MASK,
.d_PCIE_INTR_CE_MASK_ALL = AR9888_PCIE_INTR_CE_MASK_ALL,
.d_PCIE_INTR_CAUSE_ADDRESS = AR9888_PCIE_INTR_CAUSE_ADDRESS,
.d_SOC_RESET_CONTROL_ADDRESS = AR9888_SOC_RESET_CONTROL_ADDRESS,
.d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK =
@@ -433,6 +437,7 @@ struct targetdef_s ar9888_targetdef = {
AR9888_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_LSB,
.d_SOC_RESET_CONTROL_CE_RST_MASK =
AR9888_SOC_RESET_CONTROL_CE_RST_MASK,
#endif
.d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK =
AR9888_SOC_RESET_CONTROL_CPU_WARM_RST_MASK,
.d_CPU_INTR_ADDRESS = AR9888_CPU_INTR_ADDRESS,
@@ -499,23 +504,24 @@ struct hostdef_s ar9888_hostdef = {
.d_SOC_GLOBAL_RESET_ADDRESS = AR9888_SOC_GLOBAL_RESET_ADDRESS,
.d_RTC_STATE_ADDRESS = AR9888_RTC_STATE_ADDRESS,
.d_RTC_STATE_COLD_RESET_MASK = AR9888_RTC_STATE_COLD_RESET_MASK,
.d_PCIE_LOCAL_BASE_ADDRESS = AR9888_PCIE_LOCAL_BASE_ADDRESS,
.d_PCIE_SOC_WAKE_RESET = AR9888_PCIE_SOC_WAKE_RESET,
.d_PCIE_SOC_WAKE_ADDRESS = AR9888_PCIE_SOC_WAKE_ADDRESS,
.d_PCIE_SOC_WAKE_V_MASK = AR9888_PCIE_SOC_WAKE_V_MASK,
.d_RTC_STATE_V_MASK = AR9888_RTC_STATE_V_MASK,
.d_RTC_STATE_V_LSB = AR9888_RTC_STATE_V_LSB,
.d_FW_IND_EVENT_PENDING = AR9888_FW_IND_EVENT_PENDING,
.d_FW_IND_INITIALIZED = AR9888_FW_IND_INITIALIZED,
.d_RTC_STATE_V_ON = AR9888_RTC_STATE_V_ON,
.d_MUX_ID_MASK = AR9888_MUX_ID_MASK,
.d_TRANSACTION_ID_MASK = AR9888_TRANSACTION_ID_MASK,
#if defined(SDIO_3_0)
.d_HOST_INT_STATUS_MBOX_DATA_MASK =
AR9888_HOST_INT_STATUS_MBOX_DATA_MASK,
.d_HOST_INT_STATUS_MBOX_DATA_LSB =
AR9888_HOST_INT_STATUS_MBOX_DATA_LSB,
#endif
#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
.d_MUX_ID_MASK = AR9888_MUX_ID_MASK,
.d_TRANSACTION_ID_MASK = AR9888_TRANSACTION_ID_MASK,
.d_PCIE_LOCAL_BASE_ADDRESS = AR9888_PCIE_LOCAL_BASE_ADDRESS,
.d_PCIE_SOC_WAKE_RESET = AR9888_PCIE_SOC_WAKE_RESET,
.d_PCIE_SOC_WAKE_ADDRESS = AR9888_PCIE_SOC_WAKE_ADDRESS,
.d_PCIE_SOC_WAKE_V_MASK = AR9888_PCIE_SOC_WAKE_V_MASK,
.d_PCIE_SOC_RDY_STATUS_ADDRESS = PCIE_SOC_RDY_STATUS_ADDRESS,
.d_PCIE_SOC_RDY_STATUS_BAR_MASK = PCIE_SOC_RDY_STATUS_BAR_MASK,
.d_SOC_PCIE_BASE_ADDRESS = SOC_PCIE_BASE_ADDRESS,
@@ -523,9 +529,10 @@ struct hostdef_s ar9888_hostdef = {
.d_MSI_MAGIC_ADDRESS = MSI_MAGIC_ADDRESS,
.d_HOST_CE_COUNT = 8,
.d_ENABLE_MSI = 0,
#endif
};
#if defined(HIF_PCI) || defined(HIF_SNOC) || defined(HIF_AHB)
struct ce_reg_def ar9888_ce_targetdef = {
/* copy_engine.c */
.d_DST_WR_INDEX_ADDRESS = AR9888_DST_WR_INDEX_ADDRESS,
@@ -588,3 +595,4 @@ struct ce_reg_def ar9888_ce_targetdef = {
};
#endif
#endif

9
hif/src/hif_debug.h
Wyświetl plik

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2014 The Linux Foundation. All rights reserved.
* Copyright (c) 2014, 2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
@@ -39,4 +39,11 @@
QDF_TRACE(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_ERROR, ## args)
#define HIF_DBG(args ...) \
QDF_TRACE(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_DEBUG, ## args)
#define HIF_ENTER(fmt, ...) QDF_TRACE(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_INFO, \
"Enter: %s "fmt, __func__, ## __VA_ARGS__)
#define HIF_EXIT(fmt, ...) QDF_TRACE(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_INFO, \
"Exit: %s "fmt, __func__, ## __VA_ARGS__)
#endif /* __HIF_DEBUG_H__ */

2
hif/src/hif_hw_version.h
Wyświetl plik

@@ -38,7 +38,7 @@
#define AR6320_REV3_VERSION 0x5020000
#define AR6320_REV3_2_VERSION 0x5030000
#define AR6320_DEV_VERSION 0x1000000
#define QCA9377_REV1_1_VERSION 0x5020001
struct qwlan_hw {
u32 id;

2
hif/src/hif_io32.h
Wyświetl plik

@@ -30,6 +30,7 @@
#include <linux/io.h>
#include "hif.h"
#include "hif_main.h"
#define hif_read32_mb(addr) ioread32((void __iomem *)addr)
#define hif_write32_mb(addr, value) \
@@ -80,7 +81,6 @@
#ifdef HIF_PCI
#include "hif_io32_pci.h"
#endif
#ifdef HIF_SNOC
#include "hif_io32_snoc.h"
#endif /* HIF_PCI */

4
hif/src/hif_main.h
Wyświetl plik

@@ -94,6 +94,7 @@
#define HIF_GET_PCI_SOFTC(scn) ((struct hif_pci_softc *)scn)
#define HIF_GET_CE_STATE(scn) ((struct HIF_CE_state *)scn)
#define HIF_GET_SDIO_SOFTC(scn) ((struct hif_sdio_softc *)scn)
#define HIF_GET_SOFTC(scn) ((struct hif_softc *)scn)
#define GET_HIF_OPAQUE_HDL(scn) ((struct hif_opaque_softc *)scn)
@@ -162,7 +163,9 @@ A_target_id_t hif_get_target_id(struct hif_softc *scn);
void hif_dump_pipe_debug_count(struct hif_softc *scn);
bool hif_max_num_receives_reached(struct hif_softc *scn, unsigned int count);
void hif_shutdown_device(struct hif_opaque_softc *hif_ctx);
int hif_bus_configure(struct hif_softc *scn);
void hif_cancel_deferred_target_sleep(struct hif_softc *scn);
int hif_config_ce(struct hif_softc *scn);
void hif_unconfig_ce(struct hif_softc *scn);
void hif_ce_prepare_config(struct hif_softc *scn);
@@ -195,6 +198,7 @@ struct hif_driver_state_callbacks *hif_get_callbacks_handle(struct hif_softc *sc
bool hif_is_driver_unloading(struct hif_softc *scn);
bool hif_is_load_or_unload_in_progress(struct hif_softc *scn);
bool hif_is_recovery_in_progress(struct hif_softc *scn);
void hif_wlan_disable(struct hif_softc *scn);
int hif_target_sleep_state_adjust(struct hif_softc *scn,
bool sleep_ok,
bool wait_for_it);

527
hif/src/sdio/hif_bmi_reg_access.c Normal file
Wyświetl plik

@@ -0,0 +1,527 @@
/*
* Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
*
***Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#include "athdefs.h"
#include "a_types.h"
#include "a_osapi.h"
#define ATH_MODULE_NAME hif
#include "a_debug.h"
#define ATH_DEBUG_BMI ATH_DEBUG_MAKE_MODULE_MASK(0)
#include "hif.h"
#include "bmi.h"
#include "htc_api.h"
#include "if_sdio.h"
#include "regtable_sdio.h"
#define BMI_COMMUNICATION_TIMEOUT 100000
static bool pending_events_func_check;
static uint32_t command_credits;
static uint32_t *p_bmi_cmd_credits = &command_credits;
/* BMI Access routines */
/**
* hif_bmi_buffer_send - call to send bmi buffer
* @device: hif context
* @buffer: buffer
* @length: length
*
* Return: QDF_STATUS_SUCCESS for success.
*/
static QDF_STATUS
hif_bmi_buffer_send(struct hif_sdio_dev *device, char *buffer, uint32_t length)
{
QDF_STATUS status;
uint32_t timeout;
uint32_t address;
uint32_t mbox_address[HTC_MAILBOX_NUM_MAX];
hif_configure_device(device, HIF_DEVICE_GET_MBOX_ADDR,
&mbox_address[0], sizeof(mbox_address));
*p_bmi_cmd_credits = 0;
timeout = BMI_COMMUNICATION_TIMEOUT;
while (timeout-- && !(*p_bmi_cmd_credits)) {
/* Read the counter register to get the command credits */
address =
COUNT_DEC_ADDRESS + (HTC_MAILBOX_NUM_MAX + ENDPOINT1) * 4;
/* hit the credit counter with a 4-byte access, the first
* byte read will hit the counter and cause
* a decrement, while the remaining 3 bytes has no effect.
* The rationale behind this is to make all HIF accesses
* 4-byte aligned */
status =
hif_read_write(device, address,
(uint8_t *) p_bmi_cmd_credits, 4,
HIF_RD_SYNC_BYTE_INC, NULL);
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s:Unable to decrement the credit count register\n",
__func__));
return QDF_STATUS_E_FAILURE;
}
/* the counter is only 8=bits, ignore anything in the
*upper 3 bytes */
(*p_bmi_cmd_credits) &= 0xFF;
}
if (*p_bmi_cmd_credits) {
address = mbox_address[ENDPOINT1];
status = hif_read_write(device, address, buffer, length,
HIF_WR_SYNC_BYTE_INC, NULL);
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s:Unable to send the BMI data to the device\n",
__func__));
return QDF_STATUS_E_FAILURE;
}
} else {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s:BMI Communication timeout - hif_bmi_buffer_send\n",
__func__));
return QDF_STATUS_E_FAILURE;
}
return status;
}
#if defined(SDIO_3_0)
static QDF_STATUS
hif_bmi_read_write(struct hif_sdio_dev *device,
char *buffer, uint32_t length)
{
QDF_STATUS status;
status = hif_read_write(device, HOST_INT_STATUS_ADDRESS,
buffer, length,
HIF_RD_SYNC_BYTE_INC, NULL);
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s:Unable to read int status reg\n",
__func__));
return QDF_STATUS_E_FAILURE;
}
*buffer = (HOST_INT_STATUS_MBOX_DATA_GET(*buffer) & (1 << ENDPOINT1));
return status;
}
#else
static QDF_STATUS
hif_bmi_read_write(struct hif_sdio_dev *device,
char *buffer, uint32_t length)
{
QDF_STATUS status;
status = hif_read_write(device, RX_LOOKAHEAD_VALID_ADDRESS,
buffer, length,
HIF_RD_SYNC_BYTE_INC, NULL);
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s:Unable to read rx lookahead reg\n",
__func__));
return QDF_STATUS_E_FAILURE;
}
*buffer &= (1 << ENDPOINT1);
return status;
}
#endif
/**
* hif_bmi_buffer_receive - call when bmi buffer is received
* @device: hif context
* @buffer: buffer
* @length: length
* @want_timeout: timeout is needed or not
*
* Return: QDF_STATUS_SUCCESS for success.
*/
static QDF_STATUS
hif_bmi_buffer_receive(struct hif_sdio_dev *device,
char *buffer, uint32_t length, bool want_timeout)
{
QDF_STATUS status;
uint32_t address;
uint32_t mbox_address[HTC_MAILBOX_NUM_MAX];
struct _HIF_PENDING_EVENTS_INFO hif_pending_events;
static HIF_PENDING_EVENTS_FUNC get_pending_events_func;
if (!pending_events_func_check) {
/* see if the HIF layer implements an alternative
* function to get pending events
* do this only once! */
hif_configure_device(device,
HIF_DEVICE_GET_PENDING_EVENTS_FUNC,
&get_pending_events_func,
sizeof(get_pending_events_func));
pending_events_func_check = true;
}
hif_configure_device(device, HIF_DEVICE_GET_MBOX_ADDR,
&mbox_address[0], sizeof(mbox_address));
/*
* During normal bootup, small reads may be required.
* Rather than issue an HIF Read and then wait as the Target
* adds successive bytes to the FIFO, we wait here until
* we know that response data is available.
*
* This allows us to cleanly timeout on an unexpected
* Target failure rather than risk problems at the HIF level. In
* particular, this avoids SDIO timeouts and possibly garbage
* data on some host controllers. And on an interconnect
* such as Compact Flash (as well as some SDIO masters) which
* does not provide any indication on data timeout, it avoids
* a potential hang or garbage response.
*
* Synchronization is more difficult for reads larger than the
* size of the MBOX FIFO (128B), because the Target is unable
* to push the 129th byte of data until AFTER the Host posts an
* HIF Read and removes some FIFO data. So for large reads the
* Host proceeds to post an HIF Read BEFORE all the data is
* actually available to read. Fortunately, large BMI reads do
* not occur in practice -- they're supported for debug/development.
*
* So Host/Target BMI synchronization is divided into these cases:
* CASE 1: length < 4
* Should not happen
*
* CASE 2: 4 <= length <= 128
* Wait for first 4 bytes to be in FIFO
* If CONSERVATIVE_BMI_READ is enabled, also wait for
* a BMI command credit, which indicates that the ENTIRE
* response is available in the the FIFO
*
* CASE 3: length > 128
* Wait for the first 4 bytes to be in FIFO
*
* For most uses, a small timeout should be sufficient and we will
* usually see a response quickly; but there may be some unusual
* (debug) cases of BMI_EXECUTE where we want an larger timeout.
* For now, we use an unbounded busy loop while waiting for
* BMI_EXECUTE.
*
* If BMI_EXECUTE ever needs to support longer-latency execution,
* especially in production, this code needs to be enhanced to sleep
* and yield. Also note that BMI_COMMUNICATION_TIMEOUT is currently
* a function of Host processor speed.
*/
if (length >= 4) { /* NB: Currently, always true */
/*
* NB: word_available is declared static for esoteric reasons
* having to do with protection on some OSes.
*/
static uint32_t word_available;
uint32_t timeout;
word_available = 0;
timeout = BMI_COMMUNICATION_TIMEOUT;
while ((!want_timeout || timeout--) && !word_available) {
if (get_pending_events_func != NULL) {
status = get_pending_events_func(device,
&hif_pending_events,
NULL);
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s:Failed to get pending events\n",
__func__));
break;
}
if (hif_pending_events.available_recv_bytes >=
sizeof(uint32_t)) {
word_available = 1;
}
continue;
}
status = hif_bmi_read_write(device,
(uint8_t *) &word_available,
sizeof(word_available));
if (status != QDF_STATUS_SUCCESS)
return QDF_STATUS_E_FAILURE;
}
if (!word_available) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s:BMI Communication timeout FIFO empty\n",
__func__));
return QDF_STATUS_E_FAILURE;
}
}
address = mbox_address[ENDPOINT1];
status = hif_read_write(device, address, buffer, length,
HIF_RD_SYNC_BYTE_INC, NULL);
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s:Unable to read the BMI data from the device\n",
__func__));
return QDF_STATUS_E_FAILURE;
}
return QDF_STATUS_SUCCESS;
}
/**
* hif_reg_based_get_target_info - to retrieve target info
* @hif_ctx: hif context
* @targ_info: bmi target info
*
* Return: QDF_STATUS_SUCCESS for success.
*/
QDF_STATUS hif_reg_based_get_target_info(struct hif_opaque_softc *hif_ctx,
struct bmi_target_info
*targ_info) {
QDF_STATUS status;
uint32_t cid;
struct hif_sdio_softc *scn = HIF_GET_SDIO_SOFTC(hif_ctx);
struct hif_sdio_dev *device = scn->hif_handle;
AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
("BMI Get Target Info: Enter (device: 0x%p)\n",
device));
cid = BMI_GET_TARGET_INFO;
status = hif_bmi_buffer_send(device, (char *) &cid, sizeof(cid));
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s:Unable to write to the device\n",
__func__));
return QDF_STATUS_E_FAILURE;
}
status = hif_bmi_buffer_receive(device,
(char *) &targ_info->target_ver,
sizeof(targ_info->target_ver), true);
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s:Unable to read Target Version from the device\n",
__func__));
return QDF_STATUS_E_FAILURE;
}
if (targ_info->target_ver == TARGET_VERSION_SENTINAL) {
/* Determine how many bytes are in the Target's targ_info */
status = hif_bmi_buffer_receive(device,
(char *) &targ_info->
target_info_byte_count,
sizeof(targ_info->
target_info_byte_count),
true);
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s:Unable to read target Info\n",
__func__));
return QDF_STATUS_E_FAILURE;
}
/*
* The Target's targ_info doesn't match the Host's targ_info.
* We need to do some backwards compatibility work to make this
* OK.*/
QDF_ASSERT(targ_info->target_info_byte_count ==
sizeof(*targ_info));
/* Read the remainder of the targ_info */
status = hif_bmi_buffer_receive(device,
((char *) targ_info) +
sizeof(targ_info->
target_info_byte_count),
sizeof(*targ_info) -
sizeof(targ_info->
target_info_byte_count),
true);
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s:Unable to read Target Info (%d bytes)\n",
__func__, targ_info->target_info_byte_count));
return QDF_STATUS_E_FAILURE;
}
} else {
/*
* Target must be an AR6001 whose firmware does not
* support BMI_GET_TARGET_INFO. Construct the data
* that it would have sent.
*/
targ_info->target_info_byte_count = sizeof(*targ_info);
targ_info->target_type = TARGET_TYPE_AR6001;
}
AR_DEBUG_PRINTF(ATH_DEBUG_BMI,
("BMI Get Target Info: Exit (ver: 0x%x type: 0x%x)\n",
targ_info->target_ver,
targ_info->target_type));
return QDF_STATUS_SUCCESS;
}
/**
* hif_exchange_bmi_msg - API to handle HIF-specific BMI message exchanges
* @hif_ctx: hif context
* @bmi_cmd_da: bmi cmd
* @bmi_rsp_da: bmi rsp
* @send_message: send message
* @length: length
* @response_message: response message
* @response_length: response length
* @timeout_ms: timeout in ms
*
* This API is synchronous
* and only allowed to be called from a context that can block (sleep)
*
* Return: QDF_STATUS_SUCCESS for success.
*/
QDF_STATUS hif_exchange_bmi_msg(struct hif_opaque_softc *hif_ctx,
qdf_dma_addr_t bmi_cmd_da,
qdf_dma_addr_t bmi_rsp_da,
uint8_t *send_message,
uint32_t length,
uint8_t *response_message,
uint32_t *response_length,
uint32_t timeout_ms) {
struct hif_sdio_softc *scn = HIF_GET_SDIO_SOFTC(hif_ctx);
struct hif_sdio_dev *device = scn->hif_handle;
QDF_STATUS status = QDF_STATUS_SUCCESS;
if (device == NULL) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s:Null device argument\n",
__func__));
return QDF_STATUS_E_INVAL;
}
status = hif_bmi_buffer_send(device, send_message, length);
if (QDF_IS_STATUS_ERROR(status)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s:Unable to Send Message to device\n",
__func__));
return status;
}
if (response_message != NULL) {
status = hif_bmi_buffer_receive(device, response_message,
*response_length,
timeout_ms ? true : false);
if (QDF_IS_STATUS_ERROR(status)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s:Unable to read response\n",
__func__));
return status;
}
}
return status;
}
/**
* hif_bmi_raw_write - API to handle bmi raw buffer
* @device: hif context
* @buffer: buffer
* @length: length
*
* Return: QDF_STATUS_SUCCESS for success.
*/
QDF_STATUS
hif_bmi_raw_write(struct hif_sdio_dev *device, char *buffer,
uint32_t length) {
return hif_bmi_buffer_send(device, buffer, length);
}
/**
* hif_bmi_raw_read - call when bmi buffer is received
* @device: hif context
* @buffer: buffer
* @length: length
* @want_timeout: timeout is needed or not
*
* Return: QDF_STATUS_SUCCESS for success.
*/
QDF_STATUS
hif_bmi_raw_read(struct hif_sdio_dev *device, char *buffer,
uint32_t length, bool want_timeout)
{
return hif_bmi_buffer_receive(device, buffer, length,
want_timeout);
}
#ifdef BRINGUP_DEBUG
#define SDIO_SCRATCH_1_ADDRESS 0x864
/*Functions used for debugging*/
/**
* hif_bmi_write_scratch_register - API to write scratch register
* @device: hif context
* @buffer: buffer
*
* Return: QDF_STATUS_SUCCESS for success.
*/
QDF_STATUS hif_bmi_write_scratch_register(struct hif_sdio_dev *device,
uint32_t buffer) {
QDF_STATUS status = QDF_STATUS_SUCCESS;
status = hif_read_write(device, SDIO_SCRATCH_1_ADDRESS,
(uint8_t *) &buffer, 4,
HIF_WR_SYNC_BYTE_INC, NULL);
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s: Unable to write to 0x%x\n",
__func__, SDIO_SCRATCH_1_ADDRESS));
return QDF_STATUS_E_FAILURE;
} else {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s: wrote 0x%x to 0x%x\n", __func__,
buffer, SDIO_SCRATCH_1_ADDRESS));
}
return status;
}
/**
* hif_bmi_read_scratch_register - API to read from scratch register
* @device: hif context
*
* Return: QDF_STATUS_SUCCESS for success.
*/
QDF_STATUS hif_bmi_read_scratch_register(struct hif_sdio_dev *device)
{
QDF_STATUS status = QDF_STATUS_SUCCESS;
uint32_t buffer = 0;
status = hif_read_write(device, SDIO_SCRATCH_1_ADDRESS,
(uint8_t *) &buffer, 4,
HIF_RD_SYNC_BYTE_INC, NULL);
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s: Unable to read from 0x%x\n",
__func__, SDIO_SCRATCH_1_ADDRESS));
return QDF_STATUS_E_FAILURE;
} else {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s: read 0x%x from 0x%x\n", __func__,
buffer, SDIO_SCRATCH_1_ADDRESS));
}
return status;
}
#endif

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/*
* Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#include "athdefs.h"
#include "a_types.h"
#include "a_osapi.h"
#define ATH_MODULE_NAME hif
#include "a_debug.h"
#include "targaddrs.h"
#include "hif.h"
#include "if_sdio.h"
#include "regtable_sdio.h"
#define CPU_DBG_SEL_ADDRESS 0x00000483
#define CPU_DBG_ADDRESS 0x00000484
#define WORD_NON_ALIGNMENT_MASK 0x03
/**
* hif_ar6000_set_address_window_register - set the window address register (using 4-byte register access ).
* @hif_device: hif context
* @register_addr: register address
* @addr: addr
*
* This mitigates host interconnect issues with non-4byte aligned bus requests,
* some interconnects use bus adapters that impose strict limitations.
* Since diag window access is not intended for performance critical operations,
* the 4byte mode should be satisfactory as it generates 4X the bus activity.
*
* Return: QDF_STATUS_SUCCESS for success.
*/
static
QDF_STATUS hif_ar6000_set_address_window_register(
struct hif_sdio_dev *hif_device,
uint32_t register_addr,
uint32_t addr)
{
QDF_STATUS status;
static uint32_t address;
address = addr;
/*AR6320,just write the 4-byte address to window register*/
status = hif_read_write(hif_device,
register_addr,
(char *) (&address),
4, HIF_WR_SYNC_BYTE_INC, NULL);
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_LOG_ERR,
("Cannot write 0x%x to window reg: 0x%X\n",
addr, register_addr));
return status;
}
return QDF_STATUS_SUCCESS;
}
/**
* hif_diag_read_access - Read from the AR6000 through its diagnostic window.
* @hif_ctx: hif context
* @address: address
* @data: data
*
* No cooperation from the Target is required for this.
*
* Return: QDF_STATUS_SUCCESS for success.
*/
QDF_STATUS hif_diag_read_access(struct hif_opaque_softc *hif_ctx,
uint32_t address,
uint32_t *data)
{
QDF_STATUS status;
static uint32_t readvalue;
struct hif_sdio_softc *scn = HIF_GET_SDIO_SOFTC(hif_ctx);
struct hif_sdio_dev *hif_device = scn->hif_handle;
if (address & WORD_NON_ALIGNMENT_MASK) {
AR_DEBUG_PRINTF(ATH_LOG_ERR,
("[%s]addr is not 4 bytes align.addr[0x%08x]\n",
__func__, address));
return QDF_STATUS_E_FAILURE;
}
/* set window register to start read cycle */
status = hif_ar6000_set_address_window_register(hif_device,
WINDOW_READ_ADDR_ADDRESS,
address);
if (status != QDF_STATUS_SUCCESS)
return status;
/* read the data */
status = hif_read_write(hif_device,
WINDOW_DATA_ADDRESS,
(char *) &readvalue,
sizeof(uint32_t), HIF_RD_SYNC_BYTE_INC, NULL);
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_LOG_ERR,
("Cannot read from WINDOW_DATA_ADDRESS\n"));
return status;
}
*data = readvalue;
return status;
}
/**
* hif_diag_write_access - Write to the AR6000 through its diagnostic window.
* @hif_ctx: hif context
* @address: address
* @data: data
*
* No cooperation from the Target is required for this.
*
* Return: QDF_STATUS_SUCCESS for success.
*/
QDF_STATUS hif_diag_write_access(struct hif_opaque_softc *hif_ctx,
uint32_t address, uint32_t data)
{
QDF_STATUS status;
static uint32_t write_value;
struct hif_sdio_softc *scn = HIF_GET_SDIO_SOFTC(hif_ctx);
struct hif_sdio_dev *hif_device = scn->hif_handle;
if (address & WORD_NON_ALIGNMENT_MASK) {
AR_DEBUG_PRINTF(ATH_LOG_ERR,
("[%s]addr is not 4 bytes align.addr[0x%08x]\n",
__func__, address));
return QDF_STATUS_E_FAILURE;
}
write_value = data;
/* set write data */
status = hif_read_write(hif_device,
WINDOW_DATA_ADDRESS,
(char *) &write_value,
sizeof(uint32_t), HIF_WR_SYNC_BYTE_INC, NULL);
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_LOG_ERR,
("Cannot write 0x%x to WINDOW_DATA_ADDRESS\n",
data));
return status;
}
/* set window register, which starts the write cycle */
return hif_ar6000_set_address_window_register(hif_device,
WINDOW_WRITE_ADDR_ADDRESS,
address);
}
/**
* hif_diag_write_mem - Write a block data to the AR6000 through its diagnostic window.
* @scn: hif context
* @address: address
* @data: data
* @nbytes: nbytes
*
* This function may take some time.
* No cooperation from the Target is required for this.
*
* Return: QDF_STATUS_SUCCESS for success.
*/
QDF_STATUS hif_diag_write_mem(struct hif_opaque_softc *scn, uint32_t address,
uint8_t *data, int nbytes)
{
QDF_STATUS status;
int32_t i;
uint32_t tmp_data;
if ((address & WORD_NON_ALIGNMENT_MASK) ||
(nbytes & WORD_NON_ALIGNMENT_MASK)) {
AR_DEBUG_PRINTF(ATH_LOG_ERR,
("[%s]addr or length is not 4 bytes"
" align.addr[0x%08x] len[0x%08x]\n",
__func__, address, nbytes));
return QDF_STATUS_E_FAILURE;
}
for (i = 0; i < nbytes; i += 4) {
tmp_data =
data[i] | (data[i + 1] << 8) | (data[i + 2] << 16) |
(data[i + 3] << 24);
status = hif_diag_write_access(scn, address + i, tmp_data);
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_LOG_ERR,
("Diag Write mem failed.addr[0x%08x]"
" value[0x%08x]\n",
address + i, tmp_data));
return status;
}
}
return QDF_STATUS_SUCCESS;
}
/**
* hif_diag_read_mem - Read a block data to the AR6000 through its diagnostic window.
* @scn: hif context
* @data: data
* @nbytes: nbytes
*
* This function may take some time.
* No cooperation from the Target is required for this.
*
* Return: QDF_STATUS_SUCCESS for success.
*/
QDF_STATUS hif_diag_read_mem(struct hif_opaque_softc *scn,
uint32_t address, uint8_t *data,
int nbytes)
{
QDF_STATUS status;
int32_t i;
uint32_t tmp_data;
if ((address & WORD_NON_ALIGNMENT_MASK) ||
(nbytes & WORD_NON_ALIGNMENT_MASK)) {
AR_DEBUG_PRINTF(ATH_LOG_ERR,
("[%s]addr or length is not 4 bytes"
" align.addr[0x%08x] len[0x%08x]\n",
__func__, address, nbytes));
return QDF_STATUS_E_FAILURE;
}
for (i = 0; i < nbytes; i += 4) {
status = hif_diag_read_access(scn, address + i, &tmp_data);
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_LOG_ERR,
("Diag Write mem failed.addr[0x%08x]"
" value[0x%08x]\n",
address + i, tmp_data));
return status;
}
data[i] = tmp_data & 0xff;
data[i + 1] = tmp_data >> 8 & 0xff;
data[i + 2] = tmp_data >> 16 & 0xff;
data[i + 3] = tmp_data >> 24 & 0xff;
}
return QDF_STATUS_SUCCESS;
}
/**
* hif_ar6k_read_target_register - call to read target register values
* @hif_device: hif context
* @regsel: register selection
* @regval: reg value
*
* Return: QDF_STATUS_SUCCESS for success.
*/
QDF_STATUS hif_ar6k_read_target_register(struct hif_sdio_dev *hif_device,
int regsel, uint32_t *regval)
{
QDF_STATUS status;
char vals[4];
char register_selection[4];
register_selection[0] = regsel & 0xff;
register_selection[1] = regsel & 0xff;
register_selection[2] = regsel & 0xff;
register_selection[3] = regsel & 0xff;
status = hif_read_write(hif_device, CPU_DBG_SEL_ADDRESS,
register_selection, 4,
HIF_WR_SYNC_BYTE_FIX, NULL);
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_LOG_ERR,
("Cannot write CPU_DBG_SEL (%d)\n", regsel));
return status;
}
status = hif_read_write(hif_device,
CPU_DBG_ADDRESS,
(char *) vals,
sizeof(vals), HIF_RD_SYNC_BYTE_INC, NULL);
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_LOG_ERR,
("Cannot read from CPU_DBG_ADDRESS\n"));
return status;
}
*regval = vals[0] << 0 | vals[1] << 8 |
vals[2] << 16 | vals[3] << 24;
return status;
}
/**
* hif_ar6k_fetch_target_regs - call to fetch target reg values
* @hif_device: hif context
* @targregs: target regs
*
* Return: None
*/
void hif_ar6k_fetch_target_regs(struct hif_sdio_dev *hif_device,
uint32_t *targregs)
{
int i;
uint32_t val;
for (i = 0; i < AR6003_FETCH_TARG_REGS_COUNT; i++) {
val = 0xffffffff;
hif_ar6k_read_target_register(hif_device, i, &val);
targregs[i] = val;
}
}

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/*
* Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#include <qdf_types.h>
#include <qdf_status.h>
#include <qdf_timer.h>
#include <qdf_time.h>
#include <qdf_lock.h>
#include <qdf_mem.h>
#include <qdf_util.h>
#include <qdf_defer.h>
#include <qdf_atomic.h>
#include <qdf_nbuf.h>
#include <athdefs.h>
#include "qdf_net_types.h"
#include "a_types.h"
#include "athdefs.h"
#include "a_osapi.h"
#include <hif.h>
#include <htc_services.h>
#include <a_debug.h>
#include "hif_sdio_dev.h"
#include "if_sdio.h"
#include "regtable_sdio.h"
#define ATH_MODULE_NAME hif_sdio
/**
* hif_start() - start hif bus interface.
* @hif_ctx: HIF context
*
* Enables hif device interrupts
*
* Return: int
*/
uint32_t hif_start(struct hif_opaque_softc *hif_ctx)
{
struct hif_sdio_softc *scn = HIF_GET_SDIO_SOFTC(hif_ctx);
struct hif_sdio_dev *hif_device = scn->hif_handle;
struct hif_sdio_device *htc_sdio_device = hif_dev_from_hif(hif_device);
HIF_ENTER();
hif_dev_enable_interrupts(htc_sdio_device);
HIF_EXIT();
return QDF_STATUS_SUCCESS;
}
/**
* hif_flush_surprise_remove() - remove hif bus interface.
* @hif_ctx: HIF context
*
*
* Return: none
*/
void hif_flush_surprise_remove(struct hif_opaque_softc *hif_ctx)
{
}
/**
* hif_sdio_stop() - stop hif bus interface.
* @hif_ctx: HIF context
*
* Disable hif device interrupts and destroy hif context
*
* Return: none
*/
void hif_sdio_stop(struct hif_softc *hif_ctx)
{
struct hif_sdio_softc *scn = HIF_GET_SDIO_SOFTC(hif_ctx);
struct hif_sdio_dev *hif_device = scn->hif_handle;
struct hif_sdio_device *htc_sdio_device = hif_dev_from_hif(hif_device);
HIF_ENTER();
if (htc_sdio_device != NULL) {
hif_dev_disable_interrupts(htc_sdio_device);
hif_dev_destroy(htc_sdio_device);
}
HIF_EXIT();
}
/**
* hif_send_head() - send data on hif bus interface.
* @hif_ctx: HIF context
*
* send tx data on a given pipe id
*
* Return: int
*/
QDF_STATUS hif_send_head(struct hif_opaque_softc *hif_ctx, uint8_t pipe,
uint32_t transfer_id, uint32_t nbytes, qdf_nbuf_t buf,
uint32_t data_attr)
{
struct hif_sdio_softc *scn = HIF_GET_SDIO_SOFTC(hif_ctx);
struct hif_sdio_dev *hif_device = scn->hif_handle;
struct hif_sdio_device *htc_sdio_device = hif_dev_from_hif(hif_device);
return hif_dev_send_buffer(htc_sdio_device,
transfer_id, pipe,
nbytes, buf);
}
/**
* hif_map_service_to_pipe() - maps ul/dl pipe to service id.
* @hif_ctx: HIF hdl
* @ServiceId: sevice index
* @ULPipe: uplink pipe id
* @DLPipe: down-linklink pipe id
* @ul_is_polled: if ul is polling based
* @ul_is_polled: if dl is polling based
*
* Return: int
*/
int hif_map_service_to_pipe(struct hif_opaque_softc *hif_hdl,
uint16_t service_id, uint8_t *ul_pipe,
uint8_t *dl_pipe, int *ul_is_polled,
int *dl_is_polled)
{
struct hif_sdio_softc *scn = HIF_GET_SDIO_SOFTC(hif_hdl);
struct hif_sdio_dev *hif_device = scn->hif_handle;
struct hif_sdio_device *htc_sdio_device = hif_dev_from_hif(hif_device);
return hif_dev_map_service_to_pipe(htc_sdio_device,
service_id, ul_pipe, dl_pipe,
hif_device->swap_mailbox);
}
/**
* hif_map_service_to_pipe() - maps ul/dl pipe to service id.
* @scn: HIF context
* @ServiceId: sevice index
* @ULPipe: uplink pipe id
* @DLPipe: down-linklink pipe id
* @ul_is_polled: if ul is polling based
* @ul_is_polled: if dl is polling based
*
* Return: int
*/
void hif_get_default_pipe(struct hif_opaque_softc *scn, uint8_t *ul_pipe,
uint8_t *dl_pipe)
{
hif_map_service_to_pipe(scn, HTC_CTRL_RSVD_SVC,
ul_pipe, dl_pipe, NULL, NULL);
}
/**
* hif_post_init() - create hif device after probe.
* @hif_ctx: HIF context
* @target: HIF target
* @callbacks: htc callbacks
*
*
* Return: int
*/
void hif_post_init(struct hif_opaque_softc *hif_ctx, void *target,
struct hif_msg_callbacks *callbacks)
{
struct hif_sdio_softc *scn = HIF_GET_SDIO_SOFTC(hif_ctx);
struct hif_sdio_dev *hif_device = scn->hif_handle;
struct hif_sdio_device *htc_sdio_device = hif_dev_from_hif(hif_device);
if (htc_sdio_device == NULL)
htc_sdio_device = hif_dev_create(hif_device, callbacks, target);
if (htc_sdio_device)
hif_dev_setup(htc_sdio_device);
return;
}
/**
* hif_get_free_queue_number() - create hif device after probe.
* @hif_ctx: HIF context
* @pipe: pipe id
*
* SDIO uses credit based flow control at the HTC layer
* so transmit resource checks are bypassed
* Return: int
*/
uint16_t hif_get_free_queue_number(struct hif_opaque_softc *hif_ctx,
uint8_t pipe)
{
uint16_t rv;
rv = 1;
return rv;
}
/**
* hif_send_complete_check() - check tx complete on a given pipe.
* @hif_ctx: HIF context
* @pipe: HIF target
* @force: check if need to pool for completion
* Decide whether to actually poll for completions, or just
* wait for a later chance.
*
* Return: int
*/
void hif_send_complete_check(struct hif_opaque_softc *hif_ctx, uint8_t pipe,
int force)
{
}
/**
* hif_set_bundle_mode() - set bundling mode.
* @hif_ctx: HIF context
* @enabled: enable/disable bundling
* @rx_bundle_cnt: bundling count
*
* Return: none
*/
void hif_set_bundle_mode(struct hif_opaque_softc *hif_ctx, bool enabled,
uint64_t rx_bundle_cnt)
{
}

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/*
* Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _HIF_SDIO_COMMON_H_
#define _HIF_SDIO_COMMON_H_
/* SDIO manufacturer ID and Codes */
#define MANUFACTURER_ID_AR6002_BASE 0x200
#define MANUFACTURER_ID_AR6003_BASE 0x300
#define MANUFACTURER_ID_AR6004_BASE 0x400
#define MANUFACTURER_ID_AR6320_BASE 0x500
#define MANUFACTURER_ID_QCA9377_BASE 0x700
#define MANUFACTURER_ID_AR6K_BASE_MASK 0xFF00
#define MANUFACTURER_ID_AR6K_REV_MASK 0x00FF
#define FUNCTION_CLASS 0x0
#define MANUFACTURER_CODE 0x271
/* Mailbox address in SDIO address space */
#if defined(SDIO_3_0)
#define HIF_MBOX_BASE_ADDR 0x1000
#define HIF_MBOX_DUMMY_WIDTH 0x800
#else
#define HIF_MBOX_BASE_ADDR 0x800
#define HIF_MBOX_DUMMY_WIDTH 0
#endif
#define HIF_MBOX_WIDTH 0x800
#define HIF_MBOX_START_ADDR(mbox) \
(HIF_MBOX_BASE_ADDR + mbox * (HIF_MBOX_WIDTH + HIF_MBOX_DUMMY_WIDTH))
#define HIF_MBOX_END_ADDR(mbox) \
(HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1)
/* extended MBOX address for larger MBOX writes to MBOX 0*/
#if defined(SDIO_3_0)
#define HIF_MBOX0_EXTENDED_BASE_ADDR 0x5000
#else
#define HIF_MBOX0_EXTENDED_BASE_ADDR 0x2800
#endif
#define HIF_MBOX0_EXTENDED_WIDTH_AR6002 (6*1024)
#define HIF_MBOX0_EXTENDED_WIDTH_AR6003 (18*1024)
/* version 1 of the chip has only a 12K extended mbox range */
#define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6003_V1 0x4000
#define HIF_MBOX0_EXTENDED_WIDTH_AR6003_V1 (12*1024)
#define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6004 0x2800
#define HIF_MBOX0_EXTENDED_WIDTH_AR6004 (18*1024)
#if defined(SDIO_3_0)
#define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6320 0x5000
#define HIF_MBOX0_EXTENDED_WIDTH_AR6320 (36*1024)
#define HIF_MBOX0_EXTENDED_WIDTH_AR6320_ROME_2_0 (56*1024)
#define HIF_MBOX1_EXTENDED_WIDTH_AR6320 (36*1024)
#define HIF_MBOX_DUMMY_SPACE_SIZE_AR6320 (2*1024)
#else
#define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6320 0x2800
#define HIF_MBOX0_EXTENDED_WIDTH_AR6320 (24*1024)
#define HIF_MBOX1_EXTENDED_WIDTH_AR6320 (24*1024)
#define HIF_MBOX_DUMMY_SPACE_SIZE_AR6320 0
#endif
/* GMBOX addresses */
#define HIF_GMBOX_BASE_ADDR 0x7000
#define HIF_GMBOX_WIDTH 0x4000
/* for SDIO we recommend a 128-byte block size */
#if defined(WITH_BACKPORTS)
#define HIF_DEFAULT_IO_BLOCK_SIZE 128
#else
#define HIF_DEFAULT_IO_BLOCK_SIZE 256
#endif
#define FIFO_TIMEOUT_AND_CHIP_CONTROL 0x00000868
#define FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_OFF 0xFFFEFFFF
#define FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_ON 0x10000
/* In SDIO 2.0, asynchronous interrupt is not in SPEC
* requirement, but AR6003 support it, so the register
* is placed in vendor specific field 0xF0(bit0)
* In SDIO 3.0, the register is defined in SPEC, and its
* address is 0x16(bit1) */
/* interrupt mode register of AR6003 */
#define CCCR_SDIO_IRQ_MODE_REG_AR6003 0xF0
/* mode to enable special 4-bit interrupt assertion without clock */
#define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ_AR6003 (1 << 0)
/* interrupt mode register of AR6320 */
#define CCCR_SDIO_IRQ_MODE_REG_AR6320 0x16
/* mode to enable special 4-bit interrupt assertion without clock */
#define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ_AR6320 (1 << 1)
#define CCCR_SDIO_ASYNC_INT_DELAY_ADDRESS 0xF0
#define CCCR_SDIO_ASYNC_INT_DELAY_LSB 0x06
#define CCCR_SDIO_ASYNC_INT_DELAY_MASK 0xC0
/* Vendor Specific Driver Strength Settings */
#define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_ADDR 0xf2
#define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_MASK 0x0e
#define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_A 0x02
#define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_C 0x04
#define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_D 0x08
#endif /* _HIF_SDIO_COMMON_H_ */

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/*
* Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#define ATH_MODULE_NAME hif
#include "a_debug.h"
#include <qdf_types.h>
#include <qdf_status.h>
#include <qdf_timer.h>
#include <qdf_time.h>
#include <qdf_lock.h>
#include <qdf_mem.h>
#include <qdf_util.h>
#include <qdf_defer.h>
#include <qdf_atomic.h>
#include <qdf_nbuf.h>
#include <athdefs.h>
#include <qdf_net_types.h>
#include <a_types.h>
#include <athdefs.h>
#include <a_osapi.h>
#include <hif.h>
#include <htc_services.h>
#include "hif_sdio_internal.h"
#include "if_sdio.h"
#include "regtable_sdio.h"
/* under HL SDIO, with Interface Memory support, we have
* the following reasons to support 2 mboxs:
* a) we need place different buffers in different
* mempool, for example, data using Interface Memory,
* desc and other using DRAM, they need different SDIO
* mbox channels.
* b) currently, tx mempool in LL case is seperated from
* main mempool, the structure (descs at the beginning
* of every pool buffer) is different, because they only
* need store tx desc from host. To align with LL case,
* we also need 2 mbox support just as PCIe LL cases.
*/
#define INVALID_MAILBOX_NUMBER 0xFF
/**
* hif_dev_map_pipe_to_mail_box() - maps pipe id to mailbox.
* @pdev: sdio device context
* @pipeid: pipe index
*
*
* Return: mailbox index
*/
uint8_t hif_dev_map_pipe_to_mail_box(struct hif_sdio_device *pdev,
uint8_t pipeid)
{
/* TODO: temp version, should not hardcoded here, will be
* updated after HIF design */
if (2 == pipeid || 3 == pipeid)
return 1;
else if (0 == pipeid || 1 == pipeid)
return 0;
else {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s: pipeid=%d,should not happen\n",
__func__, pipeid));
qdf_assert(0);
return INVALID_MAILBOX_NUMBER;
}
}
/**
* hif_dev_map_mail_box_to_pipe() - map sdio mailbox to htc pipe.
* @pdev: sdio device
* @mboxIndex: mailbox index
* @upload: boolean to decide mailbox index
*
* Disable hif device interrupts and destroy hif context
*
* Return: none
*/
uint8_t hif_dev_map_mail_box_to_pipe(struct hif_sdio_device *pdev,
uint8_t mbox_index,
bool upload)
{
/* TODO: temp version, should not hardcoded here, will be
* updated after HIF design */
if (mbox_index == 0) {
return upload ? 1 : 0;
} else if (mbox_index == 1) {
return upload ? 3 : 2;
} else {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s:--------------------mboxIndex=%d,upload=%d,"
" should not happen\n",
__func__, mbox_index, upload));
qdf_assert(0);
return 0xff;
}
}
/**
* hif_dev_map_service_to_pipe() - maps ul/dl pipe to service id.
* @pDev: sdio device context
* @ServiceId: sevice index
* @ULPipe: uplink pipe id
* @DLPipe: down-linklink pipe id
* @SwapMapping: mailbox swap mapping
*
* Return: int
*/
QDF_STATUS hif_dev_map_service_to_pipe(struct hif_sdio_device *pdev,
uint16_t service_id,
uint8_t *ul_pipe, uint8_t *dl_pipe,
bool swap_mapping)
{
QDF_STATUS status = QDF_STATUS_SUCCESS;
switch (service_id) {
case HTT_DATA_MSG_SVC:
if (swap_mapping) {
*ul_pipe = 1;
*dl_pipe = 0;
} else {
*ul_pipe = 3;
*dl_pipe = 2;
}
break;
case HTC_CTRL_RSVD_SVC:
case HTC_RAW_STREAMS_SVC:
*ul_pipe = 1;
*dl_pipe = 0;
break;
case WMI_DATA_BE_SVC:
case WMI_DATA_BK_SVC:
case WMI_DATA_VI_SVC:
case WMI_DATA_VO_SVC:
*ul_pipe = 1;
*dl_pipe = 0;
break;
case WMI_CONTROL_SVC:
if (swap_mapping) {
*ul_pipe = 3;
*dl_pipe = 2;
} else {
*ul_pipe = 1;
*dl_pipe = 0;
}
break;
default:
status = !QDF_STATUS_SUCCESS;
break;
}
return status;
}
/**
* hif_dev_alloc_rx_buffer() - allocate rx buffer.
* @pDev: sdio device context
*
*
* Return: htc buffer pointer
*/
HTC_PACKET *hif_dev_alloc_rx_buffer(struct hif_sdio_device *pdev)
{
HTC_PACKET *packet;
qdf_nbuf_t netbuf;
uint32_t bufsize = 0, headsize = 0;
bufsize = HIF_SDIO_RX_BUFFER_SIZE + HIF_SDIO_RX_DATA_OFFSET;
headsize = sizeof(HTC_PACKET);
netbuf = qdf_nbuf_alloc(NULL, bufsize + headsize, 0, 4, false);
if (netbuf == NULL) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("(%s)Allocate netbuf failed\n", __func__));
return NULL;
}
packet = (HTC_PACKET *) qdf_nbuf_data(netbuf);
qdf_nbuf_reserve(netbuf, headsize);
SET_HTC_PACKET_INFO_RX_REFILL(packet,
pdev,
qdf_nbuf_data(netbuf),
bufsize, ENDPOINT_0);
SET_HTC_PACKET_NET_BUF_CONTEXT(packet, netbuf);
return packet;
}
/**
* hif_dev_create() - create hif device after probe.
* @scn: HIF context
* @callbacks: htc callbacks
* @target: HIF target
*
*
* Return: int
*/
struct hif_sdio_device *hif_dev_create(struct hif_sdio_dev *hif_device,
struct hif_msg_callbacks *callbacks, void *target)
{
QDF_STATUS status;
struct hif_sdio_device *pdev;
pdev = qdf_mem_malloc(sizeof(struct hif_sdio_device));
if (!pdev) {
A_ASSERT(false);
return NULL;
}
qdf_mem_zero(pdev, sizeof(struct hif_sdio_device));
qdf_spinlock_create(&pdev->Lock);
qdf_spinlock_create(&pdev->TxLock);
qdf_spinlock_create(&pdev->RxLock);
pdev->HIFDevice = hif_device;
pdev->pTarget = target;
status = hif_configure_device(hif_device,
HIF_DEVICE_SET_HTC_CONTEXT,
(void *)pdev, sizeof(pdev));
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("(%s)HIF_DEVICE_SET_HTC_CONTEXT failed!!!\n",
__func__));
}
A_MEMCPY(&pdev->hif_callbacks, callbacks, sizeof(*callbacks));
return pdev;
}
/**
* hif_dev_destroy() - destroy hif device.
* @pDev: sdio device context
*
*
* Return: none
*/
void hif_dev_destroy(struct hif_sdio_device *pdev)
{
QDF_STATUS status;
status = hif_configure_device(pdev->HIFDevice,
HIF_DEVICE_SET_HTC_CONTEXT,
(void *)NULL, 0);
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("(%s)HIF_DEVICE_SET_HTC_CONTEXT failed!!!\n",
__func__));
}
qdf_mem_free(pdev);
}
/**
* hif_dev_from_hif() - get sdio device from hif device.
* @pDev: hif device context
*
*
* Return: hif sdio device context
*/
struct hif_sdio_device *hif_dev_from_hif(struct hif_sdio_dev *hif_device)
{
struct hif_sdio_device *pdev = NULL;
QDF_STATUS status;
status = hif_configure_device(hif_device,
HIF_DEVICE_GET_HTC_CONTEXT,
(void **)&pdev, sizeof(struct hif_sdio_device));
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("(%s)HTC_SDIO_CONTEXT is NULL!!!\n",
__func__));
}
return pdev;
}
/**
* hif_dev_disable_interrupts() - disable hif device interrupts.
* @pDev: sdio device context
*
*
* Return: int
*/
QDF_STATUS hif_dev_disable_interrupts(struct hif_sdio_device *pdev)
{
struct MBOX_IRQ_ENABLE_REGISTERS regs;
QDF_STATUS status = QDF_STATUS_SUCCESS;
HIF_ENTER();
LOCK_HIF_DEV(pdev);
/* Disable all interrupts */
pdev->IrqEnableRegisters.int_status_enable = 0;
pdev->IrqEnableRegisters.cpu_int_status_enable = 0;
pdev->IrqEnableRegisters.error_status_enable = 0;
pdev->IrqEnableRegisters.counter_int_status_enable = 0;
/* copy into our temp area */
A_MEMCPY(&regs,
&pdev->IrqEnableRegisters, sizeof(pdev->IrqEnableRegisters));
UNLOCK_HIF_DEV(pdev);
/* always synchronous */
status = hif_read_write(pdev->HIFDevice,
INT_STATUS_ENABLE_ADDRESS,
(char *) &regs,
sizeof(struct MBOX_IRQ_ENABLE_REGISTERS),
HIF_WR_SYNC_BYTE_INC, NULL);
if (status != QDF_STATUS_SUCCESS) {
/* Can't write it for some reason */
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("Failed to update interrupt control registers err: %d",
status));
}
/* To Do mask the host controller interrupts */
hif_mask_interrupt(pdev->HIFDevice);
HIF_EXIT("status :%d", status);
return status;
}
/**
* hif_dev_enable_interrupts() - enables hif device interrupts.
* @pDev: sdio device context
*
*
* Return: int
*/
QDF_STATUS hif_dev_enable_interrupts(struct hif_sdio_device *pdev)
{
QDF_STATUS status;
struct MBOX_IRQ_ENABLE_REGISTERS regs;
HIF_ENTER();
/* for good measure, make sure interrupt are disabled
* before unmasking at the HIF layer.
* The rationale here is that between device insertion
* (where we clear the interrupts the first time)
* and when HTC is finally ready to handle interrupts,
* other software can perform target "soft" resets.
* The AR6K interrupt enables reset back to an "enabled"
* state when this happens. */
hif_dev_disable_interrupts(pdev);
/* Unmask the host controller interrupts */
hif_un_mask_interrupt(pdev->HIFDevice);
LOCK_HIF_DEV(pdev);
/* Enable all the interrupts except for the internal
* AR6000 CPU interrupt */
pdev->IrqEnableRegisters.int_status_enable =
INT_STATUS_ENABLE_ERROR_SET(0x01) |
INT_STATUS_ENABLE_CPU_SET(0x01)
| INT_STATUS_ENABLE_COUNTER_SET(0x01);
/* enable 2 mboxs INT */
pdev->IrqEnableRegisters.int_status_enable |=
INT_STATUS_ENABLE_MBOX_DATA_SET(0x01) |
INT_STATUS_ENABLE_MBOX_DATA_SET(0x02);
/* Set up the CPU Interrupt Status Register, enable
* CPU sourced interrupt #0, #1.
* #0 is used for report assertion from target
* #1 is used for inform host that credit arrived
* */
pdev->IrqEnableRegisters.cpu_int_status_enable = 0x03;
/* Set up the Error Interrupt Status Register */
pdev->IrqEnableRegisters.error_status_enable =
(ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(0x01)
| ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(0x01)) >> 16;
/* Set up the Counter Interrupt Status Register
* (only for debug interrupt to catch fatal errors) */
pdev->IrqEnableRegisters.counter_int_status_enable =
(COUNTER_INT_STATUS_ENABLE_BIT_SET(AR6K_TARGET_DEBUG_INTR_MASK)) >>
24;
/* copy into our temp area */
A_MEMCPY(&regs,
&pdev->IrqEnableRegisters,
sizeof(struct MBOX_IRQ_ENABLE_REGISTERS));
UNLOCK_HIF_DEV(pdev);
/* always synchronous */
status = hif_read_write(pdev->HIFDevice,
INT_STATUS_ENABLE_ADDRESS,
(char *) &regs,
sizeof(struct MBOX_IRQ_ENABLE_REGISTERS),
HIF_WR_SYNC_BYTE_INC, NULL);
if (status != QDF_STATUS_SUCCESS) {
/* Can't write it for some reason */
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("Failed to update interrupt control registers err: %d\n",
status));
}
HIF_EXIT();
return status;
}
/**
* hif_dev_setup() - set up sdio device.
* @pDev: sdio device context
*
*
* Return: int
*/
QDF_STATUS hif_dev_setup(struct hif_sdio_device *pdev)
{
QDF_STATUS status;
uint32_t blocksizes[MAILBOX_COUNT];
HTC_CALLBACKS htc_callbacks;
struct hif_sdio_dev *hif_device = pdev->HIFDevice;
HIF_ENTER();
status = hif_configure_device(hif_device,
HIF_DEVICE_GET_MBOX_ADDR,
&pdev->MailBoxInfo,
sizeof(pdev->MailBoxInfo));
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("(%s)HIF_DEVICE_GET_MBOX_ADDR failed!!!\n",
__func__));
A_ASSERT(false);
}
status = hif_configure_device(hif_device,
HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
blocksizes, sizeof(blocksizes));
if (status != QDF_STATUS_SUCCESS) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("(%s)HIF_DEVICE_GET_MBOX_BLOCK_SIZE failed!!!\n",
__func__));
A_ASSERT(false);
}
pdev->BlockSize = blocksizes[MAILBOX_FOR_BLOCK_SIZE];
pdev->BlockMask = pdev->BlockSize - 1;
A_ASSERT((pdev->BlockSize & pdev->BlockMask) == 0);
/* assume we can process HIF interrupt events asynchronously */
pdev->HifIRQProcessingMode = HIF_DEVICE_IRQ_ASYNC_SYNC;
/* see if the HIF layer overrides this assumption */
hif_configure_device(hif_device,
HIF_DEVICE_GET_IRQ_PROC_MODE,
&pdev->HifIRQProcessingMode,
sizeof(pdev->HifIRQProcessingMode));
switch (pdev->HifIRQProcessingMode) {
case HIF_DEVICE_IRQ_SYNC_ONLY:
AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
("HIF Interrupt processing is SYNC ONLY\n"));
/* see if HIF layer wants HTC to yield */
hif_configure_device(hif_device,
HIF_DEVICE_GET_IRQ_YIELD_PARAMS,
&pdev->HifIRQYieldParams,
sizeof(pdev->HifIRQYieldParams));
if (pdev->HifIRQYieldParams.recv_packet_yield_count > 0) {
AR_DEBUG_PRINTF(ATH_DEBUG_WARN,
("HIF req of DSR yield per %d RECV packets\n",
pdev->HifIRQYieldParams.
recv_packet_yield_count));
pdev->DSRCanYield = true;
}
break;
case HIF_DEVICE_IRQ_ASYNC_SYNC:
AR_DEBUG_PRINTF(ATH_DEBUG_TRC,
("HIF Interrupt processing is ASYNC and SYNC\n"));
break;
default:
A_ASSERT(false);
break;
}
pdev->HifMaskUmaskRecvEvent = NULL;
/* see if the HIF layer implements the mask/unmask recv
* events function */
hif_configure_device(hif_device,
HIF_DEVICE_GET_RECV_EVENT_MASK_UNMASK_FUNC,
&pdev->HifMaskUmaskRecvEvent,
sizeof(pdev->HifMaskUmaskRecvEvent));
status = hif_dev_disable_interrupts(pdev);
qdf_mem_zero(&htc_callbacks, sizeof(HTC_CALLBACKS));
/* the device layer handles these */
htc_callbacks.rwCompletionHandler = hif_dev_rw_completion_handler;
htc_callbacks.dsrHandler = hif_dev_dsr_handler;
htc_callbacks.context = pdev;
status = hif_attach_htc(pdev->HIFDevice, &htc_callbacks);
HIF_EXIT();
return status;
}

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/*
* Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef HIF_SDIO_DEV_H_
#define HIF_SDIO_DEV_H_
#include "qdf_net_types.h"
#include "a_types.h"
#include "athdefs.h"
#include "a_osapi.h"
#include <hif.h>
#include "athstartpack.h"
#include "hif_internal.h"
struct hif_sdio_device *hif_dev_from_hif(struct hif_sdio_dev *hif_device);
struct hif_sdio_device *hif_dev_create(struct hif_sdio_dev *hif_device,
struct hif_msg_callbacks *callbacks,
void *target);
void hif_dev_destroy(struct hif_sdio_device *htc_sdio_device);
QDF_STATUS hif_dev_setup(struct hif_sdio_device *htc_sdio_device);
QDF_STATUS hif_dev_enable_interrupts(struct hif_sdio_device *htc_sdio_device);
QDF_STATUS hif_dev_disable_interrupts(struct hif_sdio_device *htc_sdio_device);
QDF_STATUS hif_dev_send_buffer(struct hif_sdio_device *htc_sdio_device,
unsigned int transfer_id, uint8_t pipe,
unsigned int nbytes, qdf_nbuf_t buf);
QDF_STATUS hif_dev_map_service_to_pipe(struct hif_sdio_device *pdev,
uint16_t service_id,
uint8_t *ul_pipe,
uint8_t *dl_pipe,
bool swap_mapping);
#endif /* HIF_SDIO_DEV_H_ */

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/*
* Copyright (c) 2013-2014, 2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _HIF_SDIO_INTERNAL_H_
#define _HIF_SDIO_INTERNAL_H_
#include "a_debug.h"
#include "hif_sdio_dev.h"
#include "htc_packet.h"
#include "htc_api.h"
#include "hif_internal.h"
#define HIF_SDIO_RX_BUFFER_SIZE 1792
#define HIF_SDIO_RX_DATA_OFFSET 64
/* TODO: print output level and mask control */
#define ATH_DEBUG_IRQ ATH_DEBUG_MAKE_MODULE_MASK(4)
#define ATH_DEBUG_XMIT ATH_DEBUG_MAKE_MODULE_MASK(5)
#define ATH_DEBUG_RECV ATH_DEBUG_MAKE_MODULE_MASK(6)
#define ATH_DEBUG_MAX_MASK 32
#define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK | \
INT_STATUS_ENABLE_CPU_MASK | \
INT_STATUS_ENABLE_COUNTER_MASK)
/* HTC operational parameters */
#define HTC_TARGET_RESPONSE_TIMEOUT 2000 /* in ms */
#define HTC_TARGET_DEBUG_INTR_MASK 0x01
#define HTC_TARGET_CREDIT_INTR_MASK 0xF0
#define MAILBOX_COUNT 4
#define MAILBOX_FOR_BLOCK_SIZE 1
#define MAILBOX_USED_COUNT 2
#if defined(SDIO_3_0)
#define MAILBOX_LOOKAHEAD_SIZE_IN_WORD 2
#else
#define MAILBOX_LOOKAHEAD_SIZE_IN_WORD 1
#endif
#define AR6K_TARGET_DEBUG_INTR_MASK 0x01
PREPACK struct MBOX_IRQ_PROC_REGISTERS {
uint8_t host_int_status;
uint8_t cpu_int_status;
uint8_t error_int_status;
uint8_t counter_int_status;
uint8_t mbox_frame;
uint8_t rx_lookahead_valid;
uint8_t host_int_status2;
uint8_t gmbox_rx_avail;
uint32_t rx_lookahead[MAILBOX_LOOKAHEAD_SIZE_IN_WORD * MAILBOX_COUNT];
uint32_t int_status_enable;
} POSTPACK;
PREPACK struct MBOX_IRQ_ENABLE_REGISTERS {
uint8_t int_status_enable;
uint8_t cpu_int_status_enable;
uint8_t error_status_enable;
uint8_t counter_int_status_enable;
} POSTPACK;
#define TOTAL_CREDIT_COUNTER_CNT 4
PREPACK struct MBOX_COUNTER_REGISTERS {
uint32_t counter[TOTAL_CREDIT_COUNTER_CNT];
} POSTPACK;
#define SDIO_NUM_DATA_RX_BUFFERS 64
#define SDIO_DATA_RX_SIZE 1664
struct hif_sdio_device {
struct hif_sdio_dev *HIFDevice;
qdf_spinlock_t Lock;
qdf_spinlock_t TxLock;
qdf_spinlock_t RxLock;
struct MBOX_IRQ_PROC_REGISTERS IrqProcRegisters;
struct MBOX_IRQ_ENABLE_REGISTERS IrqEnableRegisters;
struct MBOX_COUNTER_REGISTERS MailBoxCounterRegisters;
struct hif_msg_callbacks hif_callbacks;
struct hif_device_mbox_info MailBoxInfo;
uint32_t BlockSize;
uint32_t BlockMask;
enum hif_device_irq_mode HifIRQProcessingMode;
struct hif_device_irq_yield_params HifIRQYieldParams;
bool DSRCanYield;
HIF_MASK_UNMASK_RECV_EVENT HifMaskUmaskRecvEvent;
int CurrentDSRRecvCount;
int RecheckIRQStatusCnt;
uint32_t RecvStateFlags;
void *pTarget;
};
#define LOCK_HIF_DEV(device) qdf_spin_lock(&(device)->Lock);
#define UNLOCK_HIF_DEV(device) qdf_spin_unlock(&(device)->Lock);
#define LOCK_HIF_DEV_RX(t) qdf_spin_lock(&(t)->RxLock);
#define UNLOCK_HIF_DEV_RX(t) qdf_spin_unlock(&(t)->RxLock);
#define LOCK_HIF_DEV_TX(t) qdf_spin_lock(&(t)->TxLock);
#define UNLOCK_HIF_DEV_TX(t) qdf_spin_unlock(&(t)->TxLock);
#define DEV_CALC_RECV_PADDED_LEN(pDev, length) \
(((length) + (pDev)->BlockMask) & (~((pDev)->BlockMask)))
#define DEV_CALC_SEND_PADDED_LEN(pDev, length) \
DEV_CALC_RECV_PADDED_LEN(pDev, length)
#define DEV_IS_LEN_BLOCK_ALIGNED(pDev, length) \
(((length) % (pDev)->BlockSize) == 0)
#define HTC_RECV_WAIT_BUFFERS (1 << 0)
#define HTC_OP_STATE_STOPPING (1 << 0)
#define HTC_RX_PKT_IGNORE_LOOKAHEAD (1 << 0)
#define HTC_RX_PKT_REFRESH_HDR (1 << 1)
#define HTC_RX_PKT_PART_OF_BUNDLE (1 << 2)
#define HTC_RX_PKT_NO_RECYCLE (1 << 3)
#define HTC_RX_PKT_LAST_BUNDLED_PKT_HAS_ADDTIONAL_BLOCK (1 << 4)
#define IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(pDev) \
((pDev)->HifIRQProcessingMode != HIF_DEVICE_IRQ_SYNC_ONLY)
/* hif_sdio_dev.c */
HTC_PACKET *hif_dev_alloc_rx_buffer(struct hif_sdio_device *pDev);
uint8_t hif_dev_map_pipe_to_mail_box(struct hif_sdio_device *pDev,
uint8_t pipeid);
uint8_t hif_dev_map_mail_box_to_pipe(struct hif_sdio_device *pDev,
uint8_t mboxIndex,
bool upload);
/* hif_sdio_recv.c */
QDF_STATUS hif_dev_rw_completion_handler(void *context, QDF_STATUS status);
QDF_STATUS hif_dev_dsr_handler(void *context);
#endif /* _HIF_SDIO_INTERNAL_H_ */

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hif/src/sdio/hif_sdio_recv.c Normal file
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hif/src/sdio/hif_sdio_send.c Normal file
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/*
* Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#include <qdf_types.h>
#include <qdf_status.h>
#include <qdf_timer.h>
#include <qdf_time.h>
#include <qdf_lock.h>
#include <qdf_mem.h>
#include <qdf_util.h>
#include <qdf_defer.h>
#include <qdf_atomic.h>
#include <qdf_nbuf.h>
#include <athdefs.h>
#include <qdf_net_types.h>
#include <a_types.h>
#include <athdefs.h>
#include <a_osapi.h>
#include <hif.h>
#include <htc_services.h>
#include <a_debug.h>
#include "hif_sdio_internal.h"
/*
* Data structure to record required sending context data
*/
struct hif_sendContext {
bool bNewAlloc;
struct hif_sdio_device *pDev;
qdf_nbuf_t netbuf;
unsigned int transferID;
unsigned int head_data_len;
};
/**
* hif_dev_rw_completion_handler() - Completion routine
* for ALL HIF layer async I/O
* @context: hif send context
* @status: completion routine sync/async context
*
* Return: 0 for success and non-zero for failure
*/
QDF_STATUS hif_dev_rw_completion_handler(void *context, QDF_STATUS status)
{
struct hif_sendContext *send_context =
(struct hif_sendContext *)context;
unsigned int transfer_id = send_context->transferID;
struct hif_sdio_device *pdev = send_context->pDev;
qdf_nbuf_t buf = send_context->netbuf;
/* Fix Me: Do we need toeplitz_hash_result for SDIO */
uint32_t toeplitz_hash_result = 0;
if (send_context->bNewAlloc)
qdf_mem_free((void *)send_context);
else
qdf_nbuf_pull_head(buf, send_context->head_data_len);
if (pdev->hif_callbacks.txCompletionHandler)
pdev->hif_callbacks.txCompletionHandler(pdev->hif_callbacks.
Context, buf,
transfer_id, toeplitz_hash_result);
return QDF_STATUS_SUCCESS;
}
/**
* hif_dev_send_buffer() - send buffer to sdio device
* @pDev: sdio function
* @transferID: transfer id
* @pipe: ul/dl pipe
* @nbytes: no of bytes to transfer
* @buf: pointer to buffer
*
* Return: 0 for success and non-zero for failure
*/
QDF_STATUS hif_dev_send_buffer(struct hif_sdio_device *pdev,
unsigned int transfer_id,
uint8_t pipe, unsigned int nbytes,
qdf_nbuf_t buf)
{
QDF_STATUS status;
uint32_t padded_length;
int frag_count = 0, i, head_data_len;
struct hif_sendContext *send_context;
unsigned char *pData;
uint32_t request = HIF_WR_ASYNC_BLOCK_INC;
uint8_t mbox_index = hif_dev_map_pipe_to_mail_box(pdev, pipe);
padded_length = DEV_CALC_SEND_PADDED_LEN(pdev, nbytes);
A_ASSERT(padded_length - nbytes < HIF_DUMMY_SPACE_MASK + 1);
/*
* two most significant bytes to save dummy data count
* data written into the dummy space will not put into
* the final mbox FIFO.
*/
request |= ((padded_length - nbytes) << 16);
frag_count = qdf_nbuf_get_num_frags(buf);
if (frag_count > 1) {
/* header data length should be total sending length substract
* internal data length of netbuf */
head_data_len = sizeof(struct hif_sendContext) +
(nbytes - qdf_nbuf_get_frag_len(buf, frag_count - 1));
} else {
/*
* | hif_sendContext | netbuf->data
*/
head_data_len = sizeof(struct hif_sendContext);
}
/* Check whether head room is enough to save extra head data */
if ((head_data_len <= qdf_nbuf_headroom(buf)) &&
(qdf_nbuf_tailroom(buf) >= (padded_length - nbytes))) {
send_context =
(struct hif_sendContext *)qdf_nbuf_push_head(buf,
head_data_len);
send_context->bNewAlloc = false;
} else {
send_context =
(struct hif_sendContext *)
qdf_mem_malloc(sizeof(struct hif_sendContext) +
padded_length);
send_context->bNewAlloc = true;
}
send_context->netbuf = buf;
send_context->pDev = pdev;
send_context->transferID = transfer_id;
send_context->head_data_len = head_data_len;
/*
* Copy data to head part of netbuf or head of allocated buffer.
* if buffer is new allocated, the last buffer should be copied also.
* It assume last fragment is internal buffer of netbuf
* sometime total length of fragments larger than nbytes
*/
pData = (unsigned char *)send_context + sizeof(struct hif_sendContext);
for (i = 0; i < (send_context->bNewAlloc ? frag_count : frag_count - 1);
i++) {
int frag_len = qdf_nbuf_get_frag_len(buf, i);
unsigned char *frag_addr = qdf_nbuf_get_frag_vaddr(buf, i);
if (frag_len > nbytes)
frag_len = nbytes;
memcpy(pData, frag_addr, frag_len);
pData += frag_len;
nbytes -= frag_len;
if (nbytes <= 0)
break;
}
/* Reset pData pointer and send_context out */
pData = (unsigned char *)send_context + sizeof(struct hif_sendContext);
status = hif_read_write(pdev->HIFDevice,
pdev->MailBoxInfo.mbox_prop[mbox_index].
extended_address, (char *)pData, padded_length,
request, (void *)send_context);
if (status == QDF_STATUS_E_PENDING)
/*
* it will return QDF_STATUS_E_PENDING in native HIF
* implementation, which should be treated as successful
* result here.
*/
status = QDF_STATUS_SUCCESS;
/* release buffer or move back data pointer when failed */
if (status != QDF_STATUS_SUCCESS) {
if (send_context->bNewAlloc)
qdf_mem_free(send_context);
else
qdf_nbuf_pull_head(buf, head_data_len);
}
return status;
}

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hif/src/sdio/if_sdio.c Normal file
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/*
* Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef EXPORT_SYMTAB
#define EXPORT_SYMTAB
#endif
#include <osdep.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/if_arp.h>
#include <linux/mmc/card.h>
#include <linux/mmc/mmc.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sdio_func.h>
#include <linux/mmc/sdio_ids.h>
#include <linux/mmc/sdio.h>
#include <linux/mmc/sd.h>
#include <linux/wait.h>
#include <qdf_mem.h>
#include "bmi_msg.h" /* TARGET_TYPE_ */
#include "if_sdio.h"
#include <qdf_trace.h>
#include <cds_api.h>
#include "regtable_sdio.h"
#include <hif_debug.h>
#ifndef REMOVE_PKT_LOG
#include "ol_txrx_types.h"
#include "pktlog_ac_api.h"
#include "pktlog_ac.h"
#endif
#include "epping_main.h"
#ifndef ATH_BUS_PM
#ifdef CONFIG_PM
#define ATH_BUS_PM
#endif /* CONFIG_PM */
#endif /* ATH_BUS_PM */
#ifndef REMOVE_PKT_LOG
struct ol_pl_os_dep_funcs *g_ol_pl_os_dep_funcs = NULL;
#endif
#define HIF_SDIO_LOAD_TIMEOUT 1000
struct hif_sdio_softc *scn = NULL;
struct hif_softc *ol_sc;
static atomic_t hif_sdio_load_state;
/* Wait queue for MC thread */
wait_queue_head_t sync_wait_queue;
/**
* hif_sdio_probe() - configure sdio device
* @context: sdio device context
* @hif_handle: pointer to hif handle
*
* Return: 0 for success and non-zero for failure
*/
static A_STATUS hif_sdio_probe(void *context, void *hif_handle)
{
int ret = 0;
struct HIF_DEVICE_OS_DEVICE_INFO os_dev_info;
struct sdio_func *func = NULL;
const struct sdio_device_id *id;
uint32_t target_type;
HIF_ENTER();
scn = (struct hif_sdio_softc *)qdf_mem_malloc(sizeof(*scn));
if (!scn) {
ret = -ENOMEM;
goto err_alloc;
}
qdf_mem_zero(scn, sizeof(*scn));
scn->hif_handle = hif_handle;
hif_configure_device(hif_handle, HIF_DEVICE_GET_OS_DEVICE,
&os_dev_info,
sizeof(os_dev_info));
scn->aps_osdev.device = os_dev_info.os_dev;
scn->aps_osdev.bc.bc_bustype = QDF_BUS_TYPE_SDIO;
spin_lock_init(&scn->target_lock);
ol_sc = qdf_mem_malloc(sizeof(*ol_sc));
if (!ol_sc) {
ret = -ENOMEM;
goto err_attach;
}
OS_MEMZERO(ol_sc, sizeof(*ol_sc));
{
/*
* Attach Target register table. This is needed early on
* even before BMI since PCI and HIF initialization
* directly access Target registers.
*
* TBDXXX: targetdef should not be global -- should be stored
* in per-device struct so that we can support multiple
* different Target types with a single Host driver.
* The whole notion of an "hif type" -- (not as in the hif
* module, but generic "Host Interface Type") is bizarre.
* At first, one one expect it to be things like SDIO, USB, PCI.
* But instead, it's an actual platform type. Inexplicably, the
* values used for HIF platform types are *different* from the
* values used for Target Types.
*/
#if defined(CONFIG_AR9888_SUPPORT)
hif_register_tbl_attach(ol_sc, HIF_TYPE_AR9888);
target_register_tbl_attach(ol_sc, TARGET_TYPE_AR9888);
target_type = TARGET_TYPE_AR9888;
#elif defined(CONFIG_AR6320_SUPPORT)
id = ((struct hif_sdio_dev *) hif_handle)->id;
if ((id->device & MANUFACTURER_ID_AR6K_BASE_MASK) ==
MANUFACTURER_ID_QCA9377_BASE) {
hif_register_tbl_attach(ol_sc, HIF_TYPE_AR6320V2);
target_register_tbl_attach(ol_sc, TARGET_TYPE_AR6320V2);
} else if ((id->device & MANUFACTURER_ID_AR6K_BASE_MASK) ==
MANUFACTURER_ID_AR6320_BASE) {
int ar6kid = id->device & MANUFACTURER_ID_AR6K_REV_MASK;
if (ar6kid >= 1) {
/* v2 or higher silicon */
hif_register_tbl_attach(ol_sc,
HIF_TYPE_AR6320V2);
target_register_tbl_attach(ol_sc,
TARGET_TYPE_AR6320V2);
} else {
/* legacy v1 silicon */
hif_register_tbl_attach(ol_sc,
HIF_TYPE_AR6320);
target_register_tbl_attach(ol_sc,
TARGET_TYPE_AR6320);
}
}
target_type = TARGET_TYPE_AR6320;
#endif
}
func = ((struct hif_sdio_dev *) hif_handle)->func;
scn->targetdef = ol_sc->targetdef;
scn->hostdef = ol_sc->hostdef;
scn->aps_osdev.bdev = func;
ol_sc->bus_type = scn->aps_osdev.bc.bc_bustype;
scn->ol_sc = *ol_sc;
ol_sc->target_info.target_type = target_type;
#ifndef TARGET_DUMP_FOR_NON_QC_PLATFORM
scn->ramdump_base = ioremap(RAMDUMP_ADDR, RAMDUMP_SIZE);
scn->ramdump_size = RAMDUMP_SIZE;
if (scn->ramdump_base == NULL) {
scn->ramdump_base = 0;
scn->ramdump_size = 0;
}
#endif
if (athdiag_procfs_init(scn) != 0) {
QDF_TRACE(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_ERROR,
"%s athdiag_procfs_init failed", __func__);
ret = QDF_STATUS_E_FAILURE;
goto err_attach1;
}
atomic_set(&hif_sdio_load_state, true);
wake_up_interruptible(&sync_wait_queue);
return 0;
err_attach1:
qdf_mem_free(ol_sc);
err_attach:
qdf_mem_free(scn);
scn = NULL;
err_alloc:
return ret;
}
/**
* ol_ath_sdio_configure() - configure sdio device
* @hif_sc: pointer to sdio softc structure
* @dev: pointer to net device
* @hif_handle: pointer to sdio function
*
* Return: 0 for success and non-zero for failure
*/
int
ol_ath_sdio_configure(void *hif_sc, struct net_device *dev,
hif_handle_t *hif_hdl)
{
struct hif_sdio_softc *sc = (struct hif_sdio_softc *)hif_sc;
int ret = 0;
sc->aps_osdev.netdev = dev;
*hif_hdl = sc->hif_handle;
return ret;
}
/**
* hif_sdio_remove() - remove sdio device
* @conext: sdio device context
* @hif_handle: pointer to sdio function
*
* Return: 0 for success and non-zero for failure
*/
static A_STATUS hif_sdio_remove(void *context, void *hif_handle)
{
HIF_ENTER();
if (!scn) {
QDF_TRACE(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_ERROR,
"Global SDIO context is NULL");
return A_ERROR;
}
atomic_set(&hif_sdio_load_state, false);
athdiag_procfs_remove();
#ifndef TARGET_DUMP_FOR_NON_QC_PLATFORM
iounmap(scn->ramdump_base);
#endif
if (scn) {
qdf_mem_free(scn);
scn = NULL;
}
HIF_EXIT();
return 0;
}
/**
* hif_sdio_suspend() - sdio suspend routine
* @context: sdio device context
*
* Return: 0 for success and non-zero for failure
*/
static A_STATUS hif_sdio_suspend(void *context)
{
return 0;
}
/**
* hif_sdio_resume() - sdio resume routine
* @context: sdio device context
*
* Return: 0 for success and non-zero for failure
*/
static A_STATUS hif_sdio_resume(void *context)
{
return 0;
}
/**
* hif_sdio_power_change() - change power state of sdio bus
* @conext: sdio device context
* @config: power state configurartion
*
* Return: 0 for success and non-zero for failure
*/
static A_STATUS hif_sdio_power_change(void *context, uint32_t config)
{
return 0;
}
/*
* Module glue.
*/
#include <linux/version.h>
static char *version = "HIF (Atheros/multi-bss)";
static char *dev_info = "ath_hif_sdio";
/**
* init_ath_hif_sdio() - initialize hif sdio callbacks
* @param: none
*
* Return: 0 for success and non-zero for failure
*/
static int init_ath_hif_sdio(void)
{
static int probed;
QDF_STATUS status;
struct osdrv_callbacks osdrv_callbacks;
HIF_ENTER();
qdf_mem_zero(&osdrv_callbacks, sizeof(osdrv_callbacks));
osdrv_callbacks.device_inserted_handler = hif_sdio_probe;
osdrv_callbacks.device_removed_handler = hif_sdio_remove;
osdrv_callbacks.device_suspend_handler = hif_sdio_suspend;
osdrv_callbacks.device_resume_handler = hif_sdio_resume;
osdrv_callbacks.device_power_change_handler = hif_sdio_power_change;
if (probed)
return -ENODEV;
probed++;
QDF_TRACE(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_INFO, "%s %d", __func__,
__LINE__);
status = hif_init(&osdrv_callbacks);
if (status != QDF_STATUS_SUCCESS) {
QDF_TRACE(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_FATAL,
"%s hif_init failed!", __func__);
return -ENODEV;
}
QDF_TRACE(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_ERROR,
"%s: %s\n", dev_info, version);
return 0;
}
/**
* hif_targ_is_awake(): check if target is awake
*
* This function returns true if the target is awake
*
* @scn: struct hif_softc
* @mem: mapped mem base
*
* Return: bool
*/
bool hif_targ_is_awake(struct hif_softc *scn, void *__iomem *mem)
{
return true;
}
/**
* hif_sdio_bus_suspend() - suspend the bus
*
* This function suspends the bus, but sdio doesn't need to suspend.
* Therefore do nothing.
*
* Return: 0 for success and non-zero for failure
*/
int hif_sdio_bus_suspend(struct hif_softc *hif_ctx)
{
struct hif_sdio_softc *scn = HIF_GET_SDIO_SOFTC(hif_ctx);
struct hif_sdio_dev *hif_device = scn->hif_handle;
struct device *dev = &hif_device->func->dev;
hif_device_suspend(dev);
return 0;
}
/**
* hif_sdio_bus_resume() - hif resume API
*
* This function resumes the bus. but sdio doesn't need to resume.
* Therefore do nothing.
*
* Return: 0 for success and non-zero for failure
*/
int hif_sdio_bus_resume(struct hif_softc *hif_ctx)
{
struct hif_sdio_softc *scn = HIF_GET_SDIO_SOFTC(hif_ctx);
struct hif_sdio_dev *hif_device = scn->hif_handle;
struct device *dev = &hif_device->func->dev;
hif_device_resume(dev);
return 0;
}
/**
* hif_enable_power_gating() - enable HW power gating
*
* Return: n/a
*/
void hif_enable_power_gating(void *hif_ctx)
{
}
/**
* hif_disable_aspm() - hif_disable_aspm
*
* Return: n/a
*/
void hif_disable_aspm(void)
{
}
/**
* hif_sdio_close() - hif_bus_close
*
* Return: None
*/
void hif_sdio_close(struct hif_softc *hif_sc)
{
}
/**
* hif_sdio_open() - hif_bus_open
* @hif_sc: hif context
* @bus_type: bus type
*
* Return: QDF status
*/
QDF_STATUS hif_sdio_open(struct hif_softc *hif_sc,
enum qdf_bus_type bus_type)
{
QDF_STATUS status;
hif_sc->bus_type = bus_type;
status = init_ath_hif_sdio();
return status;
}
/**
* hif_get_target_type() - Get the target type
*
* This function is used to query the target type.
*
* @ol_sc: ol_softc struct pointer
* @dev: device pointer
* @bdev: bus dev pointer
* @bid: bus id pointer
* @hif_type: HIF type such as HIF_TYPE_QCA6180
* @target_type: target type such as TARGET_TYPE_QCA6180
*
* Return: 0 for success
*/
int hif_get_target_type(struct hif_softc *ol_sc, struct device *dev,
void *bdev, const hif_bus_id *bid, uint32_t *hif_type,
uint32_t *target_type)
{
return 0;
}
void hif_get_target_revision(struct hif_softc *ol_sc)
{
struct hif_softc *ol_sc_local = (struct hif_softc *)ol_sc;
struct hif_opaque_softc *hif_hdl = GET_HIF_OPAQUE_HDL(ol_sc_local);
uint32_t chip_id = 0;
QDF_STATUS rv;
rv = hif_diag_read_access(hif_hdl,
(CHIP_ID_ADDRESS | RTC_SOC_BASE_ADDRESS), &chip_id);
if (rv != QDF_STATUS_SUCCESS) {
HIF_ERROR("%s[%d]: get chip id fail\n", __func__, __LINE__);
} else {
ol_sc_local->target_info.target_revision =
CHIP_ID_REVISION_GET(chip_id);
}
}
/**
* hif_sdio_enable_bus() - hif_enable_bus
* @hif_sc: hif context
* @dev: dev
* @bdev: bus dev
* @bid: bus id
* @type: bus type
*
* Return: QDF_STATUS
*/
QDF_STATUS hif_sdio_enable_bus(struct hif_softc *hif_sc,
struct device *dev, void *bdev, const hif_bus_id *bid,
enum hif_enable_type type)
{
int ret = 0;
const struct sdio_device_id *id = (const struct sdio_device_id *)bid;
struct hif_sdio_softc *sc = HIF_GET_SDIO_SOFTC(hif_sc);
init_waitqueue_head(&sync_wait_queue);
if (hif_sdio_device_inserted(dev, id)) {
HIF_ERROR("wlan: %s hif_sdio_device_inserted"
"failed", __func__);
return QDF_STATUS_E_NOMEM;
}
wait_event_interruptible_timeout(sync_wait_queue,
atomic_read(&hif_sdio_load_state) == true,
HIF_SDIO_LOAD_TIMEOUT);
hif_sc->hostdef = ol_sc->hostdef;
hif_sc->targetdef = ol_sc->targetdef;
hif_sc->bus_type = ol_sc->bus_type;
hif_sc->target_info.target_type = ol_sc->target_info.target_type;
sc->hif_handle = scn->hif_handle;
sc->aps_osdev.device = scn->aps_osdev.device;
sc->aps_osdev.bc.bc_bustype = scn->aps_osdev.bc.bc_bustype;
sc->target_lock = scn->target_lock;
sc->targetdef = scn->targetdef;
sc->hostdef = scn->hostdef;
sc->aps_osdev.bdev = scn->aps_osdev.bdev;
sc->ramdump_size = scn->ramdump_size;
sc->ramdump_base = scn->ramdump_base;
return ret;
}
/**
* hif_sdio_disable_bus() - sdio disable bus
* @hif_sc: hif softc pointer
*
* Return: none
*/
void hif_sdio_disable_bus(struct hif_softc *hif_sc)
{
struct hif_sdio_softc *sc = HIF_GET_SDIO_SOFTC(hif_sc);
struct sdio_func *func = sc->aps_osdev.bdev;
hif_sdio_device_removed(func);
}
/**
* hif_sdio_get_config_item - sdio configure bus
* @hif_sc: hif context
* @opcode: configuration type
* @config: configuration value to set
* @config_len: configuration length
*
* Return: QDF_STATUS_SUCCESS for sucess
*/
QDF_STATUS hif_sdio_get_config_item(struct hif_softc *hif_sc,
int opcode, void *config, uint32_t config_len)
{
struct hif_sdio_softc *sc = HIF_GET_SDIO_SOFTC(hif_sc);
struct hif_sdio_dev *hif_device = sc->hif_handle;
return hif_configure_device(hif_device,
opcode, config, config_len);
}
/**
* hif_sdio_set_mailbox_swap - set mailbox swap
* @hif_sc: hif context
*
* Return: None
*/
void hif_sdio_set_mailbox_swap(struct hif_softc *hif_sc)
{
struct hif_sdio_softc *scn = HIF_GET_SDIO_SOFTC(hif_sc);
struct hif_sdio_dev *hif_device = scn->hif_handle;
hif_device->swap_mailbox = true;
return;
}
/**
* hif_sdio_claim_device - set mailbox swap
* @hif_sc: hif context
*
* Return: None
*/
void hif_sdio_claim_device(struct hif_softc *hif_sc)
{
struct hif_sdio_softc *scn = HIF_GET_SDIO_SOFTC(hif_sc);
struct hif_sdio_dev *hif_device = scn->hif_handle;
hif_device->claimed_ctx = hif_sc;
return;
}
/**
* hif_sdio_mask_interrupt_call() - disbale hif device irq
* @scn: pointr to softc structure
*
* Return: None
*/
void hif_sdio_mask_interrupt_call(struct hif_softc *scn)
{
struct hif_sdio_softc *hif_ctx = HIF_GET_SDIO_SOFTC(scn);
struct hif_sdio_dev *hif_device = hif_ctx->hif_handle;
hif_mask_interrupt(hif_device);
return;
}
/**
* hif_trigger_dump() - trigger various dump cmd
* @scn: struct hif_opaque_softc
* @cmd_id: dump command id
* @start: start/stop dump
*
* Return: None
*/
void hif_trigger_dump(struct hif_opaque_softc *scn, uint8_t cmd_id, bool start)
{
}
/**
* hif_check_fw_reg() - hif_check_fw_reg
* @scn: scn
* @state:
*
* Return: int
*/
int hif_check_fw_reg(struct hif_opaque_softc *scn)
{
return 0;
}
/**
* hif_wlan_disable() - call the platform driver to disable wlan
* @scn: scn
*
* Return: void
*/
void hif_wlan_disable(struct hif_softc *scn)
{
}
/**
* hif_config_target() - configure hif bus
* @hif_hdl: hif handle
* @state:
*
* Return: int
*/
int hif_config_target(void *hif_hdl)
{
return 0;
}

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/*
* Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef __IF_SDIO_H__
#define __IF_SDIO_H__
#include <linux/version.h>
#include <linux/semaphore.h>
#include <linux/interrupt.h>
#include <osdep.h>
#include <ol_if_athvar.h>
#include <athdefs.h>
#include "a_osapi.h"
#include "hif_internal.h"
#define AR6320_HEADERS_DEF
#define ATH_DBG_DEFAULT 0
#define RAMDUMP_ADDR 0x8F000000
#define RAMDUMP_SIZE 0x700000
struct hif_sdio_softc {
struct hif_softc ol_sc;
struct device *dev;
struct _NIC_DEV aps_osdev;
struct tasklet_struct intr_tq; /* tasklet */
int irq;
/*
* Guard changes to Target HW state and to software
* structures that track hardware state.
*/
spinlock_t target_lock;
void *hif_handle;
void *ramdump_base;
unsigned long ramdump_address;
unsigned long ramdump_size;
struct targetdef_s *targetdef;
struct hostdef_s *hostdef;
};
#if defined(CONFIG_ATH_PROCFS_DIAG_SUPPORT)
int athdiag_procfs_init(void *scn);
void athdiag_procfs_remove(void);
#else
static inline int athdiag_procfs_init(void *scn)
{
return 0;
}
static inline void athdiag_procfs_remove(void)
{
return;
}
#endif
#ifndef REMOVE_PKT_LOG
extern int pktlogmod_init(void *context);
extern void pktlogmod_exit(void *context);
#endif
#define DMA_MAPPING_ERROR(dev, addr) dma_mapping_error((dev), (addr))
int ath_sdio_probe(void *context, void *hif_handle);
void ath_sdio_remove(void *context, void *hif_handle);
int ath_sdio_suspend(void *context);
int ath_sdio_resume(void *context);
/*These functions are exposed to HDD*/
void hif_init_qdf_ctx(qdf_device_t qdf_dev, void *ol_sc);
void hif_deinit_qdf_ctx(void *ol_sc);
int hif_sdio_device_inserted(struct device *dev,
const struct sdio_device_id *id);
void hif_sdio_stop(struct hif_softc *hif_ctx);
void hif_sdio_shutdown(struct hif_softc *hif_ctx);
void hif_sdio_device_removed(struct sdio_func *func);
int hif_device_suspend(struct device *dev);
int hif_device_resume(struct device *dev);
void hif_register_tbl_attach(struct hif_softc *scn,
u32 hif_type);
void target_register_tbl_attach(struct hif_softc *scn,
u32 target_type);
#endif /* __IF_SDIO_H__ */

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/*
* Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _HIF_INTERNAL_H_
#define _HIF_INTERNAL_H_
#include "athdefs.h"
#include "a_types.h"
#include "a_osapi.h"
#include <qdf_types.h> /* qdf_device_t, qdf_print */
#include <qdf_time.h> /* qdf_system_ticks, etc. */
#include <qdf_status.h>
#include <qdf_timer.h>
#include <qdf_atomic.h>
#include "hif.h"
#include "hif_debug.h"
#include "hif_sdio_common.h"
#include <linux/scatterlist.h>
#include "hif_main.h"
#define HIF_LINUX_MMC_SCATTER_SUPPORT
#define BUS_REQUEST_MAX_NUM 64
#define SDIO_CLOCK_FREQUENCY_DEFAULT 25000000
#define SDWLAN_ENABLE_DISABLE_TIMEOUT 20
#define FLAGS_CARD_ENAB 0x02
#define FLAGS_CARD_IRQ_UNMSK 0x04
#define HIF_MBOX_BLOCK_SIZE HIF_DEFAULT_IO_BLOCK_SIZE
#define HIF_MBOX0_BLOCK_SIZE 1
#define HIF_MBOX1_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
#define HIF_MBOX2_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
#define HIF_MBOX3_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
/*
* direction - Direction of transfer (HIF_SDIO_READ/HIF_SDIO_WRITE).
*/
#define HIF_SDIO_READ 0x00000001
#define HIF_SDIO_WRITE 0x00000002
#define HIF_SDIO_DIR_MASK (HIF_SDIO_READ | HIF_SDIO_WRITE)
/*
* type - An interface may support different kind of rd/wr commands.
* For example: SDIO supports CMD52/CMD53s. In case of MSIO it
* translates to using different kinds of TPCs. The command type
* is thus divided into a basic and an extended command and can
* be specified using HIF_BASIC_IO/HIF_EXTENDED_IO.
*/
#define HIF_BASIC_IO 0x00000004
#define HIF_EXTENDED_IO 0x00000008
#define HIF_TYPE_MASK (HIF_BASIC_IO | HIF_EXTENDED_IO)
/*
* This indicates the whether the command is to be executed in a
* blocking or non-blocking fashion (HIF_SYNCHRONOUS/
* HIF_ASYNCHRONOUS). The read/write data paths in HTC have been
* implemented using the asynchronous mode allowing the the bus
* driver to indicate the completion of operation through the
* registered callback routine. The requirement primarily comes
* from the contexts these operations get called from (a driver's
* transmit context or the ISR context in case of receive).
* Support for both of these modes is essential.
*/
#define HIF_SYNCHRONOUS 0x00000010
#define HIF_ASYNCHRONOUS 0x00000020
#define HIF_EMODE_MASK (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS)
/*
* An interface may support different kinds of commands based on
* the tradeoff between the amount of data it can carry and the
* setup time. Byte and Block modes are supported (HIF_BYTE_BASIS/
* HIF_BLOCK_BASIS). In case of latter, the data is rounded off
* to the nearest block size by padding. The size of the block is
* configurable at compile time using the HIF_BLOCK_SIZE and is
* negotiated with the target during initialization after the
* AR6000 interrupts are enabled.
*/
#define HIF_BYTE_BASIS 0x00000040
#define HIF_BLOCK_BASIS 0x00000080
#define HIF_DMODE_MASK (HIF_BYTE_BASIS | HIF_BLOCK_BASIS)
/*
* This indicates if the address has to be incremented on AR6000
* after every read/write operation (HIF?FIXED_ADDRESS/
* HIF_INCREMENTAL_ADDRESS).
*/
#define HIF_FIXED_ADDRESS 0x00000100
#define HIF_INCREMENTAL_ADDRESS 0x00000200
#define HIF_AMODE_MASK (HIF_FIXED_ADDRESS | \
HIF_INCREMENTAL_ADDRESS)
/*
* data written into the dummy space will not put into the final mbox FIFO
*/
#define HIF_DUMMY_SPACE_MASK 0xFFFF0000
/*
* data written into the dummy space will not put into the final mbox FIFO
*/
#define HIF_DUMMY_SPACE_MASK 0xFFFF0000
#define HIF_WR_ASYNC_BYTE_FIX \
(HIF_SDIO_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | \
HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
#define HIF_WR_ASYNC_BYTE_INC \
(HIF_SDIO_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | \
HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
#define HIF_WR_ASYNC_BLOCK_INC \
(HIF_SDIO_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | \
HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
#define HIF_WR_SYNC_BYTE_FIX \
(HIF_SDIO_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | \
HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
#define HIF_WR_SYNC_BYTE_INC \
(HIF_SDIO_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | \
HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
#define HIF_WR_SYNC_BLOCK_INC \
(HIF_SDIO_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | \
HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
#define HIF_WR_ASYNC_BLOCK_FIX \
(HIF_SDIO_WRITE | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | \
HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
#define HIF_WR_SYNC_BLOCK_FIX \
(HIF_SDIO_WRITE | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | \
HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
#define HIF_RD_SYNC_BYTE_INC \
(HIF_SDIO_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | \
HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
#define HIF_RD_SYNC_BYTE_FIX \
(HIF_SDIO_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | \
HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
#define HIF_RD_ASYNC_BYTE_FIX \
(HIF_SDIO_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | \
HIF_BYTE_BASIS | HIF_FIXED_ADDRESS)
#define HIF_RD_ASYNC_BLOCK_FIX \
(HIF_SDIO_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | \
HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
#define HIF_RD_ASYNC_BYTE_INC \
(HIF_SDIO_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | \
HIF_BYTE_BASIS | HIF_INCREMENTAL_ADDRESS)
#define HIF_RD_ASYNC_BLOCK_INC \
(HIF_SDIO_READ | HIF_ASYNCHRONOUS | HIF_EXTENDED_IO | \
HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
#define HIF_RD_SYNC_BLOCK_INC \
(HIF_SDIO_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | \
HIF_BLOCK_BASIS | HIF_INCREMENTAL_ADDRESS)
#define HIF_RD_SYNC_BLOCK_FIX \
(HIF_SDIO_READ | HIF_SYNCHRONOUS | HIF_EXTENDED_IO | \
HIF_BLOCK_BASIS | HIF_FIXED_ADDRESS)
enum hif_sdio_device_state {
HIF_DEVICE_STATE_ON,
HIF_DEVICE_STATE_DEEPSLEEP,
HIF_DEVICE_STATE_CUTPOWER,
HIF_DEVICE_STATE_WOW
};
struct bus_request {
struct bus_request *next; /* link list of available requests */
struct bus_request *inusenext; /* link list of in use requests */
struct semaphore sem_req;
uint32_t address; /* request data */
char *buffer;
uint32_t length;
uint32_t request;
void *context;
QDF_STATUS status;
struct HIF_SCATTER_REQ_PRIV *scatter_req;
};
struct hif_sdio_dev {
struct sdio_func *func;
qdf_spinlock_t asynclock;
struct task_struct *async_task; /* task to handle async commands */
struct semaphore sem_async; /* wake up for async task */
int async_shutdown; /* stop the async task */
struct completion async_completion; /* thread completion */
struct bus_request *asyncreq; /* request for async tasklet */
struct bus_request *taskreq; /* async tasklet data */
qdf_spinlock_t lock;
struct bus_request *bus_request_free_queue; /* free list */
struct bus_request bus_request[BUS_REQUEST_MAX_NUM]; /* bus requests */
void *claimed_ctx;
struct htc_callbacks htc_callbacks;
uint8_t *dma_buffer;
DL_LIST scatter_req_head; /* scatter request list head */
bool scatter_enabled; /* scatter enabled flag */
bool is_suspend;
bool is_disabled;
atomic_t irq_handling;
HIF_DEVICE_POWER_CHANGE_TYPE power_config;
enum hif_sdio_device_state device_state;
const struct sdio_device_id *id;
struct mmc_host *host;
void *htc_context;
bool swap_mailbox;
};
struct HIF_DEVICE_OS_DEVICE_INFO {
void *os_dev;
};
struct hif_mailbox_properties {
u_int32_t extended_address; /* extended address for larger writes */
u_int32_t extended_size;
};
struct hif_device_irq_yield_params {
int recv_packet_yield_count; /* max number of packets to force DSR
to return */
};
struct hif_device_mbox_info {
u_int32_t mbox_addresses[4]; /*first element for legacy HIFs and
return the address and ARRAY of 32bit words */
struct hif_mailbox_properties mbox_prop[4];
u_int32_t gmbox_address;
u_int32_t gmbox_size;
u_int32_t flags; /* flags to describe mbox behavior or usage */
};
enum hif_device_irq_mode {
HIF_DEVICE_IRQ_SYNC_ONLY, /* DSR to process all
* interrupts before returning */
HIF_DEVICE_IRQ_ASYNC_SYNC, /* DSR to process interrupts */
};
struct osdrv_callbacks {
void *context; /* context to pass for all callbacks
* except device_removed_handler
* the device_removed_handler is only
* called if the device is claimed */
int (*device_inserted_handler)(void *context, void *hif_handle);
int (*device_removed_handler)(void *claimed_ctx,
void *hif_handle);
int (*device_suspend_handler)(void *context);
int (*device_resume_handler)(void *context);
int (*device_wakeup_handler)(void *context);
int (*device_power_change_handler)(void *context,
HIF_DEVICE_POWER_CHANGE_TYPE
config);
};
/* other interrupts are pending, host
* needs to read the to monitor
*/
#define HIF_OTHER_EVENTS (1 << 0)
/* pending recv packet */
#define HIF_RECV_MSG_AVAIL (1 << 1)
struct _HIF_PENDING_EVENTS_INFO {
uint32_t events;
uint32_t look_ahead;
uint32_t available_recv_bytes;
};
/* hif-sdio pending events handler type, some HIF modules
* use special mechanisms to detect packet available and other interrupts
*/
typedef int (*HIF_PENDING_EVENTS_FUNC)(struct hif_sdio_dev *device,
struct _HIF_PENDING_EVENTS_INFO *
events, void *async_context);
#define HIF_MASK_RECV true
#define HIF_UNMASK_RECV false
/* hif-sdio Handler type to mask receive events */
typedef int (*HIF_MASK_UNMASK_RECV_EVENT)(struct hif_sdio_dev *device,
bool mask,
void *async_context);
QDF_STATUS hif_configure_device(struct hif_sdio_dev *device,
enum hif_device_config_opcode opcode,
void *config, uint32_t config_len);
QDF_STATUS hif_init(struct osdrv_callbacks *callbacks);
QDF_STATUS hif_attach_htc(struct hif_sdio_dev *device,
HTC_CALLBACKS *callbacks);
QDF_STATUS hif_read_write(struct hif_sdio_dev *device,
uint32_t address,
char *buffer,
uint32_t length, uint32_t request, void *context);
void hif_ack_interrupt(struct hif_sdio_dev *device);
void hif_mask_interrupt(struct hif_sdio_dev *device);
void hif_un_mask_interrupt(struct hif_sdio_dev *device);
QDF_STATUS hif_wait_for_pending_recv(struct hif_sdio_dev *device);
struct _HIF_SCATTER_ITEM {
u_int8_t *buffer; /* CPU accessible address of buffer */
int length; /* length of transfer to/from this buffer */
void *caller_contexts[2]; /* caller context */
};
struct _HIF_SCATTER_REQ;
typedef void (*HIF_SCATTER_COMP_CB)(struct _HIF_SCATTER_REQ *);
enum HIF_SCATTER_METHOD {
HIF_SCATTER_NONE = 0,
HIF_SCATTER_DMA_REAL, /* Real SG support no restrictions */
HIF_SCATTER_DMA_BOUNCE, /* Uses SG DMA */
};
struct _HIF_SCATTER_REQ {
DL_LIST list_link; /* link management */
u_int32_t address; /* address for the read/write operation */
u_int32_t request; /* request flags */
u_int32_t total_length; /* total length of entire transfer */
u_int32_t caller_flags; /* caller specific flags */
HIF_SCATTER_COMP_CB completion_routine; /* completion callback */
int completion_status; /* status of completion */
void *context; /* caller context for this request */
int valid_scatter_entries; /* no of valid entries */
/* scatter method handled by HIF */
enum HIF_SCATTER_METHOD scatter_method;
void *hif_private[4]; /* HIF private area */
u_int8_t *scatter_bounce_buffer; /* bounce buffers */
struct _HIF_SCATTER_ITEM scatter_list[1]; /* start of scatter list */
};
typedef struct
_HIF_SCATTER_REQ * (*HIF_ALLOCATE_SCATTER_REQUEST)(struct hif_sdio_dev *device);
typedef void (*HIF_FREE_SCATTER_REQUEST)(struct hif_sdio_dev *device,
struct _HIF_SCATTER_REQ *request);
typedef QDF_STATUS (*HIF_READWRITE_SCATTER)(struct hif_sdio_dev *device,
struct _HIF_SCATTER_REQ *request);
struct HIF_DEVICE_SCATTER_SUPPORT_INFO {
/* information returned from HIF layer */
HIF_ALLOCATE_SCATTER_REQUEST allocate_req_func;
HIF_FREE_SCATTER_REQUEST free_req_func;
HIF_READWRITE_SCATTER read_write_scatter_func;
int max_scatter_entries;
int max_tx_size_per_scatter_req;
};
void hif_get_target_revision(struct hif_softc *ol_sc);
struct HIF_SCATTER_REQ_PRIV;
#define HIF_DMA_BUFFER_SIZE (4 * 1024)
#define CMD53_FIXED_ADDRESS 1
#define CMD53_INCR_ADDRESS 2
struct bus_request *hif_allocate_bus_request(struct hif_sdio_dev *device);
void hif_free_bus_request(struct hif_sdio_dev *device,
struct bus_request *busrequest);
void add_to_async_list(struct hif_sdio_dev *device,
struct bus_request *busrequest);
void hif_dump_cccr(struct hif_sdio_dev *hif_device);
#ifdef HIF_LINUX_MMC_SCATTER_SUPPORT
#define MAX_SCATTER_REQUESTS 4
#define MAX_SCATTER_ENTRIES_PER_REQ 16
#define MAX_SCATTER_REQ_TRANSFER_SIZE (32*1024)
struct HIF_SCATTER_REQ_PRIV {
struct _HIF_SCATTER_REQ *hif_scatter_req;
struct hif_sdio_dev *device; /* this device */
struct bus_request *busrequest;
/* scatter list for linux */
struct scatterlist sgentries[MAX_SCATTER_ENTRIES_PER_REQ];
};
#define ATH_DEBUG_SCATTER ATH_DEBUG_MAKE_MODULE_MASK(0)
QDF_STATUS setup_hif_scatter_support(struct hif_sdio_dev *device,
struct HIF_DEVICE_SCATTER_SUPPORT_INFO *info);
void cleanup_hif_scatter_resources(struct hif_sdio_dev *device);
QDF_STATUS do_hif_read_write_scatter(struct hif_sdio_dev *device,
struct bus_request *busrequest);
#else /* HIF_LINUX_MMC_SCATTER_SUPPORT */
static inline QDF_STATUS setup_hif_scatter_support(struct hif_sdio_dev *device,
struct HIF_DEVICE_SCATTER_SUPPORT_INFO *info)
{
return QDF_STATUS_E_NOSUPPORT;
}
static inline QDF_STATUS do_hif_read_write_scatter(struct hif_sdio_dev *device,
struct bus_request *busrequest)
{
return QDF_STATUS_E_NOSUPPORT;
}
#define cleanup_hif_scatter_resources(d) { }
#endif /* HIF_LINUX_MMC_SCATTER_SUPPORT */
#endif /* _HIF_INTERNAL_H_ */

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hif/src/sdio/native_sdio/src/hif.c Normal file
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hif/src/sdio/native_sdio/src/hif_scatter.c Normal file
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/*
* Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sdio_func.h>
#include <linux/mmc/sdio_ids.h>
#include <linux/mmc/sdio.h>
#include <linux/kthread.h>
#include "hif_internal.h"
#include <qdf_mem.h>
#include "dl_list.h"
#define ATH_MODULE_NAME hif
#include "a_debug.h"
#ifdef HIF_LINUX_MMC_SCATTER_SUPPORT
#define _CMD53_ARG_READ 0
#define _CMD53_ARG_WRITE 1
#define _CMD53_ARG_BLOCK_BASIS 1
#define _CMD53_ARG_FIXED_ADDRESS 0
#define _CMD53_ARG_INCR_ADDRESS 1
#define SDIO_SET_CMD53_ARG(arg, rw, func, mode, opcode, address, bytes_blocks) \
((arg) = (((rw) & 1) << 31) | \
((func & 0x7) << 28) | \
(((mode) & 1) << 27) | \
(((opcode) & 1) << 26) | \
(((address) & 0x1FFFF) << 9) | \
((bytes_blocks) & 0x1FF))
/**
* free_scatter_req() - free scattered request.
* @device: hif device context
* @pReq: scatter list node
*
* Return: none
*/
static void free_scatter_req(struct hif_sdio_dev *device,
struct _HIF_SCATTER_REQ *pReq)
{
qdf_spin_lock_irqsave(&device->lock);
dl_list_insert_tail(&device->scatter_req_head, &pReq->list_link);
qdf_spin_unlock_irqrestore(&device->lock);
}
/**
* alloc_scatter_req() - allocate scattered request.
* @device: hif device context
*
*
* Return: pointer to allocated scatter list node
*/
static struct _HIF_SCATTER_REQ *alloc_scatter_req(struct hif_sdio_dev *device)
{
DL_LIST *item;
qdf_spin_lock_irqsave(&device->lock);
item = dl_list_remove_item_from_head(&device->scatter_req_head);
qdf_spin_unlock_irqrestore(&device->lock);
if (item != NULL)
return A_CONTAINING_STRUCT(item,
struct _HIF_SCATTER_REQ, list_link);
return NULL;
}
/**
* do_hif_read_write_scatter() - rd/wr scattered operation.
* @device: hif device context
* @busrequest: rd/wr bus request
*
* called by async task to perform the operation synchronously
* using direct MMC APIs
* Return: int
*/
QDF_STATUS do_hif_read_write_scatter(struct hif_sdio_dev *device,
struct bus_request *busrequest)
{
int i;
uint8_t rw;
uint8_t opcode;
struct mmc_request mmcreq;
struct mmc_command cmd;
struct mmc_data data;
struct HIF_SCATTER_REQ_PRIV *req_priv;
struct _HIF_SCATTER_REQ *req;
QDF_STATUS status = QDF_STATUS_SUCCESS;
struct scatterlist *sg;
HIF_ENTER();
req_priv = busrequest->scatter_req;
A_ASSERT(req_priv != NULL);
req = req_priv->hif_scatter_req;
memset(&mmcreq, 0, sizeof(struct mmc_request));
memset(&cmd, 0, sizeof(struct mmc_command));
memset(&data, 0, sizeof(struct mmc_data));
data.blksz = HIF_MBOX_BLOCK_SIZE;
data.blocks = req->total_length / HIF_MBOX_BLOCK_SIZE;
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER,
("HIF-SCATTER: (%s) Address: 0x%X, (BlockLen: %d, BlockCount: %d), (tot:%d,sg:%d)\n",
(req->request & HIF_SDIO_WRITE) ? "WRITE" : "READ",
req->address, data.blksz, data.blocks,
req->total_length, req->valid_scatter_entries));
if (req->request & HIF_SDIO_WRITE) {
rw = _CMD53_ARG_WRITE;
data.flags = MMC_DATA_WRITE;
} else {
rw = _CMD53_ARG_READ;
data.flags = MMC_DATA_READ;
}
if (req->request & HIF_FIXED_ADDRESS)
opcode = _CMD53_ARG_FIXED_ADDRESS;
else
opcode = _CMD53_ARG_INCR_ADDRESS;
/* fill SG entries */
sg = req_priv->sgentries;
sg_init_table(sg, req->valid_scatter_entries);
/* assemble SG list */
for (i = 0; i < req->valid_scatter_entries; i++, sg++) {
/* setup each sg entry */
if ((unsigned long)req->scatter_list[i].buffer & 0x3) {
/* note some scatter engines can handle unaligned
* buffers, print this as informational only */
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER,
("HIF: (%s) Scatter Buf is unaligned 0x%lx\n",
req->
request & HIF_SDIO_WRITE ? "WRITE" : "READ",
(unsigned long)req->scatter_list[i].
buffer));
}
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER,
(" %d: Addr:0x%lX, Len:%d\n", i,
(unsigned long)req->scatter_list[i].buffer,
req->scatter_list[i].length));
sg_set_buf(sg, req->scatter_list[i].buffer,
req->scatter_list[i].length);
}
/* set scatter-gather table for request */
data.sg = req_priv->sgentries;
data.sg_len = req->valid_scatter_entries;
/* set command argument */
SDIO_SET_CMD53_ARG(cmd.arg,
rw,
device->func->num,
_CMD53_ARG_BLOCK_BASIS,
opcode, req->address, data.blocks);
cmd.opcode = SD_IO_RW_EXTENDED;
cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
mmcreq.cmd = &cmd;
mmcreq.data = &data;
mmc_set_data_timeout(&data, device->func->card);
/* synchronous call to process request */
mmc_wait_for_req(device->func->card->host, &mmcreq);
if (cmd.error) {
status = QDF_STATUS_E_FAILURE;
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
("HIF-SCATTER: cmd error: %d\n", cmd.error));
}
if (data.error) {
status = QDF_STATUS_E_FAILURE;
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
("HIF-SCATTER: data error: %d\n", data.error));
}
if (QDF_IS_STATUS_ERROR(status)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
("HIF-SCATTER: FAILED!!! (%s) Address: 0x%X, Block mode (BlockLen: %d, BlockCount: %d)\n",
(req->request & HIF_SDIO_WRITE) ? "WRITE" : "READ",
req->address, data.blksz, data.blocks));
}
/* set completion status, fail or success */
req->completion_status = status;
if (req->request & HIF_ASYNCHRONOUS) {
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER,
("HIF-SCATTER: async_task completion routine req: 0x%lX (%d)\n",
(unsigned long)busrequest, status));
/* complete the request */
A_ASSERT(req->completion_routine != NULL);
req->completion_routine(req);
} else {
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER,
("HIF-SCATTER async_task upping busreq : 0x%lX (%d)\n",
(unsigned long)busrequest, status));
/* signal wait */
up(&busrequest->sem_req);
}
HIF_EXIT();
return status;
}
/**
* alloc_scatter_req() - callback to issue a read-write
* scatter request.
* @device: hif device context
* @pReq: rd/wr scatter request
*
* Return: int
*/
static QDF_STATUS hif_read_write_scatter(struct hif_sdio_dev *device,
struct _HIF_SCATTER_REQ *req)
{
QDF_STATUS status = QDF_STATUS_E_INVAL;
uint32_t request = req->request;
struct HIF_SCATTER_REQ_PRIV *req_priv =
(struct HIF_SCATTER_REQ_PRIV *) req->hif_private[0];
do {
A_ASSERT(req_priv != NULL);
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER,
("HIF-SCATTER: total len: %d Scatter Entries: %d\n",
req->total_length,
req->valid_scatter_entries));
if (!(request & HIF_EXTENDED_IO)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
("HIF-SCATTER: Invalid command type: 0x%08x\n",
request));
break;
}
if (!(request & (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS))) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
("HIF-SCATTER: Invalid mode: 0x%08x\n",
request));
break;
}
if (!(request & HIF_BLOCK_BASIS)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
("HIF-SCATTER: Invalid data mode: 0x%08x\n",
request));
break;
}
if (req->total_length > MAX_SCATTER_REQ_TRANSFER_SIZE) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
("HIF-SCATTER: Invalid length: %d\n",
req->total_length));
break;
}
if (req->total_length == 0) {
A_ASSERT(false);
break;
}
/* add bus request to the async list for the async
* I/O thread to process */
add_to_async_list(device, req_priv->busrequest);
if (request & HIF_SYNCHRONOUS) {
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER,
("HIF-SCATTER: queued sync req: 0x%lX\n",
(unsigned long)req_priv->busrequest));
/* signal thread and wait */
up(&device->sem_async);
if (down_interruptible(&req_priv->busrequest->sem_req)
!= 0) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
("HIF-SCATTER: interrupted!\n"));
/* interrupted, exit */
status = QDF_STATUS_E_FAILURE;
break;
} else {
status = req->completion_status;
}
} else {
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER,
("HIF-SCATTER: queued async req: 0x%lX\n",
(unsigned long)req_priv->busrequest));
/* wake thread, it will process and then take
* care of the async callback */
up(&device->sem_async);
status = QDF_STATUS_SUCCESS;
}
} while (false);
if (QDF_IS_STATUS_ERROR(status) && (request & HIF_ASYNCHRONOUS)) {
req->completion_status = status;
req->completion_routine(req);
status = QDF_STATUS_SUCCESS;
}
return status;
}
/**
* setup_hif_scatter_support() - setup of HIF scatter resources
* scatter request.
* @device: hif device context
* @pInfo: scatter info
*
* Return: int
*/
QDF_STATUS setup_hif_scatter_support(struct hif_sdio_dev *device,
struct HIF_DEVICE_SCATTER_SUPPORT_INFO *info)
{
QDF_STATUS status = QDF_STATUS_E_FAILURE;
int i;
struct HIF_SCATTER_REQ_PRIV *req_priv;
struct bus_request *busrequest;
if (device->func->card->host->max_segs <
MAX_SCATTER_ENTRIES_PER_REQ) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("host only supports scatter of : %d entries,"
"need: %d\n",
device->func->card->host->max_segs,
MAX_SCATTER_ENTRIES_PER_REQ));
status = QDF_STATUS_E_NOSUPPORT;
goto end;
}
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,
("max scatter req : %d entries: %d\n",
MAX_SCATTER_REQUESTS,
MAX_SCATTER_ENTRIES_PER_REQ));
for (i = 0; i < MAX_SCATTER_REQUESTS; i++) {
/* allocate the private request blob */
req_priv =
(struct HIF_SCATTER_REQ_PRIV *)
qdf_mem_malloc(sizeof(
struct HIF_SCATTER_REQ_PRIV));
if (NULL == req_priv)
goto end;
qdf_mem_zero(req_priv, sizeof(
struct HIF_SCATTER_REQ_PRIV));
/* save the device instance */
req_priv->device = device;
/* allocate the scatter request */
req_priv->hif_scatter_req =
(struct _HIF_SCATTER_REQ *)
qdf_mem_malloc(sizeof(struct _HIF_SCATTER_REQ) +
(MAX_SCATTER_ENTRIES_PER_REQ -
1) * (sizeof(struct _HIF_SCATTER_ITEM)));
if (NULL == req_priv->hif_scatter_req) {
qdf_mem_free(req_priv);
goto end;
}
/* just zero the main part of the scatter request */
qdf_mem_zero(req_priv->hif_scatter_req,
sizeof(struct _HIF_SCATTER_REQ));
/* back pointer to the private struct */
req_priv->hif_scatter_req->hif_private[0] = req_priv;
/* allocate a bus request for this scatter request */
busrequest = hif_allocate_bus_request(device);
if (NULL == busrequest) {
qdf_mem_free(req_priv->hif_scatter_req);
qdf_mem_free(req_priv);
goto end;
}
/* assign the scatter request to this bus request */
busrequest->scatter_req = req_priv;
/* point back to the request */
req_priv->busrequest = busrequest;
/* req_priv it to the scatter pool */
free_scatter_req(device, req_priv->hif_scatter_req);
}
if (i != MAX_SCATTER_REQUESTS) {
status = QDF_STATUS_E_NOMEM;
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("failed to alloc scatter resources !\n"));
goto end;
}
/* set scatter function pointers */
info->allocate_req_func = alloc_scatter_req;
info->free_req_func = free_scatter_req;
info->read_write_scatter_func = hif_read_write_scatter;
info->max_scatter_entries = MAX_SCATTER_ENTRIES_PER_REQ;
info->max_tx_size_per_scatter_req =
MAX_SCATTER_REQ_TRANSFER_SIZE;
status = QDF_STATUS_SUCCESS;
end:
if (QDF_IS_STATUS_ERROR(status))
cleanup_hif_scatter_resources(device);
return status;
}
/**
* cleanup_hif_scatter_resources() - cleanup HIF scatter resources
* scatter request.
* @device: hif device context
*
*
* Return: none
*/
void cleanup_hif_scatter_resources(struct hif_sdio_dev *device)
{
struct HIF_SCATTER_REQ_PRIV *req_priv;
struct _HIF_SCATTER_REQ *req;
/* empty the free list */
while (true) {
req = alloc_scatter_req(device);
if (NULL == req)
break;
req_priv = (struct HIF_SCATTER_REQ_PRIV *)req->hif_private[0];
A_ASSERT(req_priv != NULL);
if (req_priv->busrequest != NULL) {
req_priv->busrequest->scatter_req = NULL;
/* free bus request */
hif_free_bus_request(device, req_priv->busrequest);
req_priv->busrequest = NULL;
}
if (req_priv->hif_scatter_req != NULL) {
qdf_mem_free(req_priv->hif_scatter_req);
req_priv->hif_scatter_req = NULL;
}
qdf_mem_free(req_priv);
}
}
#endif /* HIF_LINUX_MMC_SCATTER_SUPPORT */

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/*
* Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#include "bmi_msg.h"
#include "cepci.h"
#define MISSING 0
#include "regtable_sdio.h"
#include "targaddrs.h"
#include "if_sdio.h"
#include "ar9888def.h"
#include "ar6320def.h"
#include "ar6320v2def.h"
void target_register_tbl_attach(struct hif_softc *scn, u32 target_type)
{
switch (target_type) {
case TARGET_TYPE_AR9888:
scn->targetdef = &ar9888_targetdef;
break;
case TARGET_TYPE_AR6320:
scn->targetdef = &ar6320_targetdef;
break;
case TARGET_TYPE_AR6320V2:
scn->targetdef = &ar6320v2_targetdef;
break;
default:
break;
}
}
void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type)
{
if (NULL == scn) {
QDF_TRACE(QDF_MODULE_ID_HIF, QDF_TRACE_LEVEL_ERROR,
"%s: sc is NULL", __func__);
return;
}
switch (hif_type) {
case HIF_TYPE_AR9888:
scn->hostdef = &ar9888_hostdef;
break;
case HIF_TYPE_AR6320:
scn->hostdef = &ar6320_hostdef;
break;
case HIF_TYPE_AR6320V2:
scn->hostdef = &ar6320v2_hostdef;
break;
default:
break;
}
}

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hif/src/sdio/regtable_sdio.h Normal file
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/*
* Copyright (c) 2013-2016 The Linux Foundation. All rights reserved.
*
* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
*
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
/*
* This file was originally distributed by Qualcomm Atheros, Inc.
* under proprietary terms before Copyright ownership was assigned
* to the Linux Foundation.
*/
#ifndef _REGTABLE_SDIO_H_
#define _REGTABLE_SDIO_H_
#define MISSING 0
extern struct hif_sdio_softc *scn;
struct targetdef_s {
uint32_t d_RTC_SOC_BASE_ADDRESS;
uint32_t d_RTC_WMAC_BASE_ADDRESS;
uint32_t d_SYSTEM_SLEEP_OFFSET;
uint32_t d_WLAN_SYSTEM_SLEEP_OFFSET;
uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_LSB;
uint32_t d_WLAN_SYSTEM_SLEEP_DISABLE_MASK;
uint32_t d_CLOCK_CONTROL_OFFSET;
uint32_t d_CLOCK_CONTROL_SI0_CLK_MASK;
uint32_t d_RESET_CONTROL_OFFSET;
uint32_t d_RESET_CONTROL_MBOX_RST_MASK;
uint32_t d_RESET_CONTROL_SI0_RST_MASK;
uint32_t d_WLAN_RESET_CONTROL_OFFSET;
uint32_t d_WLAN_RESET_CONTROL_COLD_RST_MASK;
uint32_t d_WLAN_RESET_CONTROL_WARM_RST_MASK;
uint32_t d_GPIO_BASE_ADDRESS;
uint32_t d_GPIO_PIN0_OFFSET;
uint32_t d_GPIO_PIN1_OFFSET;
uint32_t d_GPIO_PIN0_CONFIG_MASK;
uint32_t d_GPIO_PIN1_CONFIG_MASK;
uint32_t d_SI_CONFIG_BIDIR_OD_DATA_LSB;
uint32_t d_SI_CONFIG_BIDIR_OD_DATA_MASK;
uint32_t d_SI_CONFIG_I2C_LSB;
uint32_t d_SI_CONFIG_I2C_MASK;
uint32_t d_SI_CONFIG_POS_SAMPLE_LSB;
uint32_t d_SI_CONFIG_POS_SAMPLE_MASK;
uint32_t d_SI_CONFIG_INACTIVE_CLK_LSB;
uint32_t d_SI_CONFIG_INACTIVE_CLK_MASK;
uint32_t d_SI_CONFIG_INACTIVE_DATA_LSB;
uint32_t d_SI_CONFIG_INACTIVE_DATA_MASK;
uint32_t d_SI_CONFIG_DIVIDER_LSB;
uint32_t d_SI_CONFIG_DIVIDER_MASK;
uint32_t d_SI_BASE_ADDRESS;
uint32_t d_SI_CONFIG_OFFSET;
uint32_t d_SI_TX_DATA0_OFFSET;
uint32_t d_SI_TX_DATA1_OFFSET;
uint32_t d_SI_RX_DATA0_OFFSET;
uint32_t d_SI_RX_DATA1_OFFSET;
uint32_t d_SI_CS_OFFSET;
uint32_t d_SI_CS_DONE_ERR_MASK;
uint32_t d_SI_CS_DONE_INT_MASK;
uint32_t d_SI_CS_START_LSB;
uint32_t d_SI_CS_START_MASK;
uint32_t d_SI_CS_RX_CNT_LSB;
uint32_t d_SI_CS_RX_CNT_MASK;
uint32_t d_SI_CS_TX_CNT_LSB;
uint32_t d_SI_CS_TX_CNT_MASK;
uint32_t d_BOARD_DATA_SZ;
uint32_t d_BOARD_EXT_DATA_SZ;
uint32_t d_MBOX_BASE_ADDRESS;
uint32_t d_LOCAL_SCRATCH_OFFSET;
uint32_t d_CPU_CLOCK_OFFSET;
uint32_t d_LPO_CAL_OFFSET;
uint32_t d_GPIO_PIN10_OFFSET;
uint32_t d_GPIO_PIN11_OFFSET;
uint32_t d_GPIO_PIN12_OFFSET;
uint32_t d_GPIO_PIN13_OFFSET;
uint32_t d_CLOCK_GPIO_OFFSET;
uint32_t d_CPU_CLOCK_STANDARD_LSB;
uint32_t d_CPU_CLOCK_STANDARD_MASK;
uint32_t d_LPO_CAL_ENABLE_LSB;
uint32_t d_LPO_CAL_ENABLE_MASK;
uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB;
uint32_t d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK;
uint32_t d_ANALOG_INTF_BASE_ADDRESS;
uint32_t d_WLAN_MAC_BASE_ADDRESS;
uint32_t d_FW_INDICATOR_ADDRESS;
uint32_t d_DRAM_BASE_ADDRESS;
uint32_t d_SOC_CORE_BASE_ADDRESS;
uint32_t d_CORE_CTRL_ADDRESS;
uint32_t d_MSI_NUM_REQUEST;
uint32_t d_MSI_ASSIGN_FW;
uint32_t d_CORE_CTRL_CPU_INTR_MASK;
uint32_t d_SR_WR_INDEX_ADDRESS;
uint32_t d_DST_WATERMARK_ADDRESS;
/* htt_rx.c */
uint32_t d_RX_MSDU_END_4_FIRST_MSDU_MASK;
uint32_t d_RX_MSDU_END_4_FIRST_MSDU_LSB;
uint32_t d_RX_MPDU_START_0_RETRY_LSB;
uint32_t d_RX_MPDU_START_0_RETRY_MASK;
uint32_t d_RX_MPDU_START_0_SEQ_NUM_MASK;
uint32_t d_RX_MPDU_START_0_SEQ_NUM_LSB;
uint32_t d_RX_MPDU_START_2_PN_47_32_LSB;
uint32_t d_RX_MPDU_START_2_PN_47_32_MASK;
uint32_t d_RX_MPDU_START_2_TID_LSB;
uint32_t d_RX_MPDU_START_2_TID_MASK;
uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK;
uint32_t d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB;
uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_MASK;
uint32_t d_RX_MSDU_END_1_KEY_ID_OCT_LSB;
uint32_t d_RX_MSDU_END_4_LAST_MSDU_MASK;
uint32_t d_RX_MSDU_END_4_LAST_MSDU_LSB;
uint32_t d_RX_ATTENTION_0_MCAST_BCAST_MASK;
uint32_t d_RX_ATTENTION_0_MCAST_BCAST_LSB;
uint32_t d_RX_ATTENTION_0_FRAGMENT_MASK;
uint32_t d_RX_ATTENTION_0_FRAGMENT_LSB;
uint32_t d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK;
uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK;
uint32_t d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB;
uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_MASK;
uint32_t d_RX_MSDU_START_0_MSDU_LENGTH_LSB;
uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET;
uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_MASK;
uint32_t d_RX_MSDU_START_2_DECAP_FORMAT_LSB;
uint32_t d_RX_MPDU_START_0_ENCRYPTED_MASK;
uint32_t d_RX_MPDU_START_0_ENCRYPTED_LSB;
uint32_t d_RX_ATTENTION_0_MORE_DATA_MASK;
uint32_t d_RX_ATTENTION_0_MSDU_DONE_MASK;
uint32_t d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK;
/* end */
/* PLL start */
uint32_t d_EFUSE_OFFSET;
uint32_t d_EFUSE_XTAL_SEL_MSB;
uint32_t d_EFUSE_XTAL_SEL_LSB;
uint32_t d_EFUSE_XTAL_SEL_MASK;
uint32_t d_BB_PLL_CONFIG_OFFSET;
uint32_t d_BB_PLL_CONFIG_OUTDIV_MSB;
uint32_t d_BB_PLL_CONFIG_OUTDIV_LSB;
uint32_t d_BB_PLL_CONFIG_OUTDIV_MASK;
uint32_t d_BB_PLL_CONFIG_FRAC_MSB;
uint32_t d_BB_PLL_CONFIG_FRAC_LSB;
uint32_t d_BB_PLL_CONFIG_FRAC_MASK;
uint32_t d_WLAN_PLL_SETTLE_TIME_MSB;
uint32_t d_WLAN_PLL_SETTLE_TIME_LSB;
uint32_t d_WLAN_PLL_SETTLE_TIME_MASK;
uint32_t d_WLAN_PLL_SETTLE_OFFSET;
uint32_t d_WLAN_PLL_SETTLE_SW_MASK;
uint32_t d_WLAN_PLL_SETTLE_RSTMASK;
uint32_t d_WLAN_PLL_SETTLE_RESET;
uint32_t d_WLAN_PLL_CONTROL_NOPWD_MSB;
uint32_t d_WLAN_PLL_CONTROL_NOPWD_LSB;
uint32_t d_WLAN_PLL_CONTROL_NOPWD_MASK;
uint32_t d_WLAN_PLL_CONTROL_BYPASS_MSB;
uint32_t d_WLAN_PLL_CONTROL_BYPASS_LSB;
uint32_t d_WLAN_PLL_CONTROL_BYPASS_MASK;
uint32_t d_WLAN_PLL_CONTROL_BYPASS_RESET;
uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MSB;
uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_LSB;
uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_MASK;
uint32_t d_WLAN_PLL_CONTROL_CLK_SEL_RESET;
uint32_t d_WLAN_PLL_CONTROL_REFDIV_MSB;
uint32_t d_WLAN_PLL_CONTROL_REFDIV_LSB;
uint32_t d_WLAN_PLL_CONTROL_REFDIV_MASK;
uint32_t d_WLAN_PLL_CONTROL_REFDIV_RESET;
uint32_t d_WLAN_PLL_CONTROL_DIV_MSB;
uint32_t d_WLAN_PLL_CONTROL_DIV_LSB;
uint32_t d_WLAN_PLL_CONTROL_DIV_MASK;
uint32_t d_WLAN_PLL_CONTROL_DIV_RESET;
uint32_t d_WLAN_PLL_CONTROL_OFFSET;
uint32_t d_WLAN_PLL_CONTROL_SW_MASK;
uint32_t d_WLAN_PLL_CONTROL_RSTMASK;
uint32_t d_WLAN_PLL_CONTROL_RESET;
uint32_t d_SOC_CORE_CLK_CTRL_OFFSET;
uint32_t d_SOC_CORE_CLK_CTRL_DIV_MSB;
uint32_t d_SOC_CORE_CLK_CTRL_DIV_LSB;
uint32_t d_SOC_CORE_CLK_CTRL_DIV_MASK;
uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MSB;
uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_LSB;
uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_MASK;
uint32_t d_RTC_SYNC_STATUS_PLL_CHANGING_RESET;
uint32_t d_RTC_SYNC_STATUS_OFFSET;
uint32_t d_SOC_CPU_CLOCK_OFFSET;
uint32_t d_SOC_CPU_CLOCK_STANDARD_MSB;
uint32_t d_SOC_CPU_CLOCK_STANDARD_LSB;
uint32_t d_SOC_CPU_CLOCK_STANDARD_MASK;
/* PLL end */
uint32_t d_SOC_POWER_REG_OFFSET;
uint32_t d_SOC_RESET_CONTROL_ADDRESS;
uint32_t d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK;
uint32_t d_CPU_INTR_ADDRESS;
uint32_t d_SOC_LF_TIMER_CONTROL0_ADDRESS;
uint32_t d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK;
/* chip id start */
uint32_t d_SOC_CHIP_ID_ADDRESS;
uint32_t d_SOC_CHIP_ID_VERSION_MASK;
uint32_t d_SOC_CHIP_ID_VERSION_LSB;
uint32_t d_SOC_CHIP_ID_REVISION_MASK;
uint32_t d_SOC_CHIP_ID_REVISION_LSB;
/* chip id end */
uint32_t d_A_SOC_CORE_SCRATCH_0_ADDRESS;
uint32_t d_A_SOC_CORE_SCRATCH_1_ADDRESS;
uint32_t d_A_SOC_CORE_SCRATCH_2_ADDRESS;
uint32_t d_A_SOC_CORE_SCRATCH_3_ADDRESS;
uint32_t d_A_SOC_CORE_SCRATCH_4_ADDRESS;
uint32_t d_A_SOC_CORE_SCRATCH_5_ADDRESS;
uint32_t d_A_SOC_CORE_SCRATCH_6_ADDRESS;
uint32_t d_A_SOC_CORE_SCRATCH_7_ADDRESS;
uint32_t d_A_SOC_CORE_SPARE_0_REGISTER;
uint32_t d_A_SOC_CORE_SPARE_1_REGISTER;
uint32_t d_WLAN_DEBUG_INPUT_SEL_OFFSET;
uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MSB;
uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_LSB;
uint32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MASK;
uint32_t d_WLAN_DEBUG_CONTROL_OFFSET;
uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MSB;
uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_LSB;
uint32_t d_WLAN_DEBUG_CONTROL_ENABLE_MASK;
uint32_t d_WLAN_DEBUG_OUT_OFFSET;
uint32_t d_WLAN_DEBUG_OUT_DATA_MSB;
uint32_t d_WLAN_DEBUG_OUT_DATA_LSB;
uint32_t d_WLAN_DEBUG_OUT_DATA_MASK;
uint32_t d_AMBA_DEBUG_BUS_OFFSET;
uint32_t d_AMBA_DEBUG_BUS_SEL_MSB;
uint32_t d_AMBA_DEBUG_BUS_SEL_LSB;
uint32_t d_AMBA_DEBUG_BUS_SEL_MASK;
#ifdef QCA_WIFI_3_0_ADRASTEA
uint32_t d_Q6_ENABLE_REGISTER_0;
uint32_t d_Q6_ENABLE_REGISTER_1;
uint32_t d_Q6_CAUSE_REGISTER_0;
uint32_t d_Q6_CAUSE_REGISTER_1;
uint32_t d_Q6_CLEAR_REGISTER_0;
uint32_t d_Q6_CLEAR_REGISTER_1;
#endif
};
#define A_SOC_CORE_SPARE_0_REGISTER \
(scn->targetdef->d_A_SOC_CORE_SPARE_0_REGISTER)
#define A_SOC_CORE_SCRATCH_0_ADDRESS \
(scn->targetdef->d_A_SOC_CORE_SCRATCH_0_ADDRESS)
#define A_SOC_CORE_SCRATCH_1_ADDRESS \
(scn->targetdef->d_A_SOC_CORE_SCRATCH_1_ADDRESS)
#define A_SOC_CORE_SCRATCH_2_ADDRESS \
(scn->targetdef->d_A_SOC_CORE_SCRATCH_2_ADDRESS)
#define A_SOC_CORE_SCRATCH_3_ADDRESS \
(scn->targetdef->d_A_SOC_CORE_SCRATCH_3_ADDRESS)
#define A_SOC_CORE_SCRATCH_4_ADDRESS \
(scn->targetdef->d_A_SOC_CORE_SCRATCH_4_ADDRESS)
#define A_SOC_CORE_SCRATCH_5_ADDRESS \
(scn->targetdef->d_A_SOC_CORE_SCRATCH_5_ADDRESS)
#define A_SOC_CORE_SCRATCH_6_ADDRESS \
(scn->targetdef->d_A_SOC_CORE_SCRATCH_6_ADDRESS)
#define A_SOC_CORE_SCRATCH_7_ADDRESS \
(scn->targetdef->d_A_SOC_CORE_SCRATCH_7_ADDRESS)
#define RTC_SOC_BASE_ADDRESS (scn->targetdef->d_RTC_SOC_BASE_ADDRESS)
#define RTC_WMAC_BASE_ADDRESS (scn->targetdef->d_RTC_WMAC_BASE_ADDRESS)
#define SYSTEM_SLEEP_OFFSET (scn->targetdef->d_SYSTEM_SLEEP_OFFSET)
#define WLAN_SYSTEM_SLEEP_OFFSET \
(scn->targetdef->d_WLAN_SYSTEM_SLEEP_OFFSET)
#define WLAN_SYSTEM_SLEEP_DISABLE_LSB \
(scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_LSB)
#define WLAN_SYSTEM_SLEEP_DISABLE_MASK \
(scn->targetdef->d_WLAN_SYSTEM_SLEEP_DISABLE_MASK)
#define CLOCK_CONTROL_OFFSET (scn->targetdef->d_CLOCK_CONTROL_OFFSET)
#define CLOCK_CONTROL_SI0_CLK_MASK \
(scn->targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK)
#define RESET_CONTROL_OFFSET (scn->targetdef->d_RESET_CONTROL_OFFSET)
#define RESET_CONTROL_MBOX_RST_MASK \
(scn->targetdef->d_RESET_CONTROL_MBOX_RST_MASK)
#define RESET_CONTROL_SI0_RST_MASK \
(scn->targetdef->d_RESET_CONTROL_SI0_RST_MASK)
#define WLAN_RESET_CONTROL_OFFSET \
(scn->targetdef->d_WLAN_RESET_CONTROL_OFFSET)
#define WLAN_RESET_CONTROL_COLD_RST_MASK \
(scn->targetdef->d_WLAN_RESET_CONTROL_COLD_RST_MASK)
#define WLAN_RESET_CONTROL_WARM_RST_MASK \
(scn->targetdef->d_WLAN_RESET_CONTROL_WARM_RST_MASK)
#define GPIO_BASE_ADDRESS (scn->targetdef->d_GPIO_BASE_ADDRESS)
#define GPIO_PIN0_OFFSET (scn->targetdef->d_GPIO_PIN0_OFFSET)
#define GPIO_PIN1_OFFSET (scn->targetdef->d_GPIO_PIN1_OFFSET)
#define GPIO_PIN0_CONFIG_MASK (scn->targetdef->d_GPIO_PIN0_CONFIG_MASK)
#define GPIO_PIN1_CONFIG_MASK (scn->targetdef->d_GPIO_PIN1_CONFIG_MASK)
#define A_SOC_CORE_SCRATCH_0 (scn->targetdef->d_A_SOC_CORE_SCRATCH_0)
#define SI_CONFIG_BIDIR_OD_DATA_LSB \
(scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB)
#define SI_CONFIG_BIDIR_OD_DATA_MASK \
(scn->targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK)
#define SI_CONFIG_I2C_LSB (scn->targetdef->d_SI_CONFIG_I2C_LSB)
#define SI_CONFIG_I2C_MASK \
(scn->targetdef->d_SI_CONFIG_I2C_MASK)
#define SI_CONFIG_POS_SAMPLE_LSB \
(scn->targetdef->d_SI_CONFIG_POS_SAMPLE_LSB)
#define SI_CONFIG_POS_SAMPLE_MASK \
(scn->targetdef->d_SI_CONFIG_POS_SAMPLE_MASK)
#define SI_CONFIG_INACTIVE_CLK_LSB \
(scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB)
#define SI_CONFIG_INACTIVE_CLK_MASK \
(scn->targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK)
#define SI_CONFIG_INACTIVE_DATA_LSB \
(scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB)
#define SI_CONFIG_INACTIVE_DATA_MASK \
(scn->targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK)
#define SI_CONFIG_DIVIDER_LSB (scn->targetdef->d_SI_CONFIG_DIVIDER_LSB)
#define SI_CONFIG_DIVIDER_MASK (scn->targetdef->d_SI_CONFIG_DIVIDER_MASK)
#define SI_BASE_ADDRESS (scn->targetdef->d_SI_BASE_ADDRESS)
#define SI_CONFIG_OFFSET (scn->targetdef->d_SI_CONFIG_OFFSET)
#define SI_TX_DATA0_OFFSET (scn->targetdef->d_SI_TX_DATA0_OFFSET)
#define SI_TX_DATA1_OFFSET (scn->targetdef->d_SI_TX_DATA1_OFFSET)
#define SI_RX_DATA0_OFFSET (scn->targetdef->d_SI_RX_DATA0_OFFSET)
#define SI_RX_DATA1_OFFSET (scn->targetdef->d_SI_RX_DATA1_OFFSET)
#define SI_CS_OFFSET (scn->targetdef->d_SI_CS_OFFSET)
#define SI_CS_DONE_ERR_MASK (scn->targetdef->d_SI_CS_DONE_ERR_MASK)
#define SI_CS_DONE_INT_MASK (scn->targetdef->d_SI_CS_DONE_INT_MASK)
#define SI_CS_START_LSB (scn->targetdef->d_SI_CS_START_LSB)
#define SI_CS_START_MASK (scn->targetdef->d_SI_CS_START_MASK)
#define SI_CS_RX_CNT_LSB (scn->targetdef->d_SI_CS_RX_CNT_LSB)
#define SI_CS_RX_CNT_MASK (scn->targetdef->d_SI_CS_RX_CNT_MASK)
#define SI_CS_TX_CNT_LSB (scn->targetdef->d_SI_CS_TX_CNT_LSB)
#define SI_CS_TX_CNT_MASK (scn->targetdef->d_SI_CS_TX_CNT_MASK)
#define EEPROM_SZ (scn->targetdef->d_BOARD_DATA_SZ)
#define EEPROM_EXT_SZ (scn->targetdef->d_BOARD_EXT_DATA_SZ)
#define MBOX_BASE_ADDRESS (scn->targetdef->d_MBOX_BASE_ADDRESS)
#define LOCAL_SCRATCH_OFFSET (scn->targetdef->d_LOCAL_SCRATCH_OFFSET)
#define CPU_CLOCK_OFFSET (scn->targetdef->d_CPU_CLOCK_OFFSET)
#define LPO_CAL_OFFSET (scn->targetdef->d_LPO_CAL_OFFSET)
#define GPIO_PIN10_OFFSET (scn->targetdef->d_GPIO_PIN10_OFFSET)
#define GPIO_PIN11_OFFSET (scn->targetdef->d_GPIO_PIN11_OFFSET)
#define GPIO_PIN12_OFFSET (scn->targetdef->d_GPIO_PIN12_OFFSET)
#define GPIO_PIN13_OFFSET (scn->targetdef->d_GPIO_PIN13_OFFSET)
#define CLOCK_GPIO_OFFSET (scn->targetdef->d_CLOCK_GPIO_OFFSET)
#define CPU_CLOCK_STANDARD_LSB (scn->targetdef->d_CPU_CLOCK_STANDARD_LSB)
#define CPU_CLOCK_STANDARD_MASK (scn->targetdef->d_CPU_CLOCK_STANDARD_MASK)
#define LPO_CAL_ENABLE_LSB (scn->targetdef->d_LPO_CAL_ENABLE_LSB)
#define LPO_CAL_ENABLE_MASK (scn->targetdef->d_LPO_CAL_ENABLE_MASK)
#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB \
(scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_LSB)
#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK \
(scn->targetdef->d_CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
#define ANALOG_INTF_BASE_ADDRESS (scn->targetdef->d_ANALOG_INTF_BASE_ADDRESS)
#define WLAN_MAC_BASE_ADDRESS (scn->targetdef->d_WLAN_MAC_BASE_ADDRESS)
#define FW_INDICATOR_ADDRESS (scn->targetdef->d_FW_INDICATOR_ADDRESS)
#define DRAM_BASE_ADDRESS (scn->targetdef->d_DRAM_BASE_ADDRESS)
#define SOC_CORE_BASE_ADDRESS (scn->targetdef->d_SOC_CORE_BASE_ADDRESS)
#define CORE_CTRL_ADDRESS (scn->targetdef->d_CORE_CTRL_ADDRESS)
#define CORE_CTRL_CPU_INTR_MASK (scn->targetdef->d_CORE_CTRL_CPU_INTR_MASK)
#define SOC_RESET_CONTROL_ADDRESS (scn->targetdef->d_SOC_RESET_CONTROL_ADDRESS)
#define SOC_RESET_CONTROL_CPU_WARM_RST_MASK \
(scn->targetdef->d_SOC_RESET_CONTROL_CPU_WARM_RST_MASK)
#define CPU_INTR_ADDRESS (scn->targetdef->d_CPU_INTR_ADDRESS)
#define SOC_LF_TIMER_CONTROL0_ADDRESS \
(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ADDRESS)
#define SOC_LF_TIMER_CONTROL0_ENABLE_MASK \
(scn->targetdef->d_SOC_LF_TIMER_CONTROL0_ENABLE_MASK)
#define CHIP_ID_ADDRESS (scn->targetdef->d_SOC_CHIP_ID_ADDRESS)
#define SOC_CHIP_ID_REVISION_MASK (scn->targetdef->d_SOC_CHIP_ID_REVISION_MASK)
#define SOC_CHIP_ID_REVISION_LSB (scn->targetdef->d_SOC_CHIP_ID_REVISION_LSB)
#define SOC_CHIP_ID_VERSION_MASK (scn->targetdef->d_SOC_CHIP_ID_VERSION_MASK)
#define SOC_CHIP_ID_VERSION_LSB (scn->targetdef->d_SOC_CHIP_ID_VERSION_LSB)
#define CHIP_ID_REVISION_GET(x) \
(((x) & SOC_CHIP_ID_REVISION_MASK) >> SOC_CHIP_ID_REVISION_LSB)
#define CHIP_ID_VERSION_GET(x) \
(((x) & SOC_CHIP_ID_VERSION_MASK) >> SOC_CHIP_ID_VERSION_LSB)
/* misc */
#define SR_WR_INDEX_ADDRESS (scn->targetdef->d_SR_WR_INDEX_ADDRESS)
#define DST_WATERMARK_ADDRESS (scn->targetdef->d_DST_WATERMARK_ADDRESS)
#define SOC_POWER_REG_OFFSET (scn->targetdef->d_SOC_POWER_REG_OFFSET)
/* end */
/* htt_rx.c */
#define RX_MSDU_END_4_FIRST_MSDU_MASK \
(pdev->targetdef->d_RX_MSDU_END_4_FIRST_MSDU_MASK)
#define RX_MSDU_END_4_FIRST_MSDU_LSB \
(pdev->targetdef->d_RX_MSDU_END_4_FIRST_MSDU_LSB)
#define RX_MPDU_START_0_RETRY_LSB \
(pdev->targetdef->d_RX_MPDU_START_0_RETRY_LSB)
#define RX_MPDU_START_0_RETRY_MASK \
(pdev->targetdef->d_RX_MPDU_START_0_RETRY_MASK)
#define RX_MPDU_START_0_SEQ_NUM_MASK \
(pdev->targetdef->d_RX_MPDU_START_0_SEQ_NUM_MASK)
#define RX_MPDU_START_0_SEQ_NUM_LSB \
(pdev->targetdef->d_RX_MPDU_START_0_SEQ_NUM_LSB)
#define RX_MPDU_START_2_PN_47_32_LSB \
(pdev->targetdef->d_RX_MPDU_START_2_PN_47_32_LSB)
#define RX_MPDU_START_2_PN_47_32_MASK \
(pdev->targetdef->d_RX_MPDU_START_2_PN_47_32_MASK)
#define RX_MPDU_START_2_TID_LSB \
(pdev->targetdef->d_RX_MPDU_START_2_TID_LSB)
#define RX_MPDU_START_2_TID_MASK \
(pdev->targetdef->d_RX_MPDU_START_2_TID_MASK)
#define RX_MSDU_END_1_KEY_ID_OCT_MASK \
(pdev->targetdef->d_RX_MSDU_END_1_KEY_ID_OCT_MASK)
#define RX_MSDU_END_1_KEY_ID_OCT_LSB \
(pdev->targetdef->d_RX_MSDU_END_1_KEY_ID_OCT_LSB)
#define RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK \
(pdev->targetdef->d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_MASK)
#define RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB \
(pdev->targetdef->d_RX_MSDU_END_1_EXT_WAPI_PN_63_48_LSB)
#define RX_MSDU_END_4_LAST_MSDU_MASK \
(pdev->targetdef->d_RX_MSDU_END_4_LAST_MSDU_MASK)
#define RX_MSDU_END_4_LAST_MSDU_LSB \
(pdev->targetdef->d_RX_MSDU_END_4_LAST_MSDU_LSB)
#define RX_ATTENTION_0_MCAST_BCAST_MASK \
(pdev->targetdef->d_RX_ATTENTION_0_MCAST_BCAST_MASK)
#define RX_ATTENTION_0_MCAST_BCAST_LSB \
(pdev->targetdef->d_RX_ATTENTION_0_MCAST_BCAST_LSB)
#define RX_ATTENTION_0_FRAGMENT_MASK \
(pdev->targetdef->d_RX_ATTENTION_0_FRAGMENT_MASK)
#define RX_ATTENTION_0_FRAGMENT_LSB \
(pdev->targetdef->d_RX_ATTENTION_0_FRAGMENT_LSB)
#define RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK \
(pdev->targetdef->d_RX_ATTENTION_0_MPDU_LENGTH_ERR_MASK)
#define RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK \
(pdev->targetdef->d_RX_FRAG_INFO_0_RING2_MORE_COUNT_MASK)
#define RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB \
(pdev->targetdef->d_RX_FRAG_INFO_0_RING2_MORE_COUNT_LSB)
#define RX_MSDU_START_0_MSDU_LENGTH_MASK \
(pdev->targetdef->d_RX_MSDU_START_0_MSDU_LENGTH_MASK)
#define RX_MSDU_START_0_MSDU_LENGTH_LSB \
(pdev->targetdef->d_RX_MSDU_START_0_MSDU_LENGTH_LSB)
#define RX_MSDU_START_2_DECAP_FORMAT_OFFSET \
(pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_OFFSET)
#define RX_MSDU_START_2_DECAP_FORMAT_MASK \
(pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_MASK)
#define RX_MSDU_START_2_DECAP_FORMAT_LSB \
(pdev->targetdef->d_RX_MSDU_START_2_DECAP_FORMAT_LSB)
#define RX_MPDU_START_0_ENCRYPTED_MASK \
(pdev->targetdef->d_RX_MPDU_START_0_ENCRYPTED_MASK)
#define RX_MPDU_START_0_ENCRYPTED_LSB \
(pdev->targetdef->d_RX_MPDU_START_0_ENCRYPTED_LSB)
#define RX_ATTENTION_0_MORE_DATA_MASK \
(pdev->targetdef->d_RX_ATTENTION_0_MORE_DATA_MASK)
#define RX_ATTENTION_0_MSDU_DONE_MASK \
(pdev->targetdef->d_RX_ATTENTION_0_MSDU_DONE_MASK)
#define RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK \
(pdev->targetdef->d_RX_ATTENTION_0_TCP_UDP_CHKSUM_FAIL_MASK)
/* end */
/* copy_engine.c */
/* end */
/* PLL start */
#define EFUSE_OFFSET (scn->targetdef->d_EFUSE_OFFSET)
#define EFUSE_XTAL_SEL_MSB (scn->targetdef->d_EFUSE_XTAL_SEL_MSB)
#define EFUSE_XTAL_SEL_LSB (scn->targetdef->d_EFUSE_XTAL_SEL_LSB)
#define EFUSE_XTAL_SEL_MASK (scn->targetdef->d_EFUSE_XTAL_SEL_MASK)
#define BB_PLL_CONFIG_OFFSET (scn->targetdef->d_BB_PLL_CONFIG_OFFSET)
#define BB_PLL_CONFIG_OUTDIV_MSB (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MSB)
#define BB_PLL_CONFIG_OUTDIV_LSB (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_LSB)
#define BB_PLL_CONFIG_OUTDIV_MASK (scn->targetdef->d_BB_PLL_CONFIG_OUTDIV_MASK)
#define BB_PLL_CONFIG_FRAC_MSB (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MSB)
#define BB_PLL_CONFIG_FRAC_LSB (scn->targetdef->d_BB_PLL_CONFIG_FRAC_LSB)
#define BB_PLL_CONFIG_FRAC_MASK (scn->targetdef->d_BB_PLL_CONFIG_FRAC_MASK)
#define WLAN_PLL_SETTLE_TIME_MSB (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MSB)
#define WLAN_PLL_SETTLE_TIME_LSB (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_LSB)
#define WLAN_PLL_SETTLE_TIME_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_TIME_MASK)
#define WLAN_PLL_SETTLE_OFFSET (scn->targetdef->d_WLAN_PLL_SETTLE_OFFSET)
#define WLAN_PLL_SETTLE_SW_MASK (scn->targetdef->d_WLAN_PLL_SETTLE_SW_MASK)
#define WLAN_PLL_SETTLE_RSTMASK (scn->targetdef->d_WLAN_PLL_SETTLE_RSTMASK)
#define WLAN_PLL_SETTLE_RESET (scn->targetdef->d_WLAN_PLL_SETTLE_RESET)
#define WLAN_PLL_CONTROL_NOPWD_MSB \
(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MSB)
#define WLAN_PLL_CONTROL_NOPWD_LSB \
(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_LSB)
#define WLAN_PLL_CONTROL_NOPWD_MASK \
(scn->targetdef->d_WLAN_PLL_CONTROL_NOPWD_MASK)
#define WLAN_PLL_CONTROL_BYPASS_MSB \
(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MSB)
#define WLAN_PLL_CONTROL_BYPASS_LSB \
(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_LSB)
#define WLAN_PLL_CONTROL_BYPASS_MASK \
(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_MASK)
#define WLAN_PLL_CONTROL_BYPASS_RESET \
(scn->targetdef->d_WLAN_PLL_CONTROL_BYPASS_RESET)
#define WLAN_PLL_CONTROL_CLK_SEL_MSB \
(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MSB)
#define WLAN_PLL_CONTROL_CLK_SEL_LSB \
(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_LSB)
#define WLAN_PLL_CONTROL_CLK_SEL_MASK \
(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_MASK)
#define WLAN_PLL_CONTROL_CLK_SEL_RESET \
(scn->targetdef->d_WLAN_PLL_CONTROL_CLK_SEL_RESET)
#define WLAN_PLL_CONTROL_REFDIV_MSB \
(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MSB)
#define WLAN_PLL_CONTROL_REFDIV_LSB \
(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_LSB)
#define WLAN_PLL_CONTROL_REFDIV_MASK \
(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_MASK)
#define WLAN_PLL_CONTROL_REFDIV_RESET \
(scn->targetdef->d_WLAN_PLL_CONTROL_REFDIV_RESET)
#define WLAN_PLL_CONTROL_DIV_MSB (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MSB)
#define WLAN_PLL_CONTROL_DIV_LSB (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_LSB)
#define WLAN_PLL_CONTROL_DIV_MASK (scn->targetdef->d_WLAN_PLL_CONTROL_DIV_MASK)
#define WLAN_PLL_CONTROL_DIV_RESET \
(scn->targetdef->d_WLAN_PLL_CONTROL_DIV_RESET)
#define WLAN_PLL_CONTROL_OFFSET (scn->targetdef->d_WLAN_PLL_CONTROL_OFFSET)
#define WLAN_PLL_CONTROL_SW_MASK (scn->targetdef->d_WLAN_PLL_CONTROL_SW_MASK)
#define WLAN_PLL_CONTROL_RSTMASK (scn->targetdef->d_WLAN_PLL_CONTROL_RSTMASK)
#define WLAN_PLL_CONTROL_RESET (scn->targetdef->d_WLAN_PLL_CONTROL_RESET)
#define SOC_CORE_CLK_CTRL_OFFSET (scn->targetdef->d_SOC_CORE_CLK_CTRL_OFFSET)
#define SOC_CORE_CLK_CTRL_DIV_MSB (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MSB)
#define SOC_CORE_CLK_CTRL_DIV_LSB (scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_LSB)
#define SOC_CORE_CLK_CTRL_DIV_MASK \
(scn->targetdef->d_SOC_CORE_CLK_CTRL_DIV_MASK)
#define RTC_SYNC_STATUS_PLL_CHANGING_MSB \
(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MSB)
#define RTC_SYNC_STATUS_PLL_CHANGING_LSB \
(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_LSB)
#define RTC_SYNC_STATUS_PLL_CHANGING_MASK \
(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_MASK)
#define RTC_SYNC_STATUS_PLL_CHANGING_RESET \
(scn->targetdef->d_RTC_SYNC_STATUS_PLL_CHANGING_RESET)
#define RTC_SYNC_STATUS_OFFSET (scn->targetdef->d_RTC_SYNC_STATUS_OFFSET)
#define SOC_CPU_CLOCK_OFFSET (scn->targetdef->d_SOC_CPU_CLOCK_OFFSET)
#define SOC_CPU_CLOCK_STANDARD_MSB \
(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MSB)
#define SOC_CPU_CLOCK_STANDARD_LSB \
(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_LSB)
#define SOC_CPU_CLOCK_STANDARD_MASK \
(scn->targetdef->d_SOC_CPU_CLOCK_STANDARD_MASK)
/* PLL end */
/* SET macros */
#define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) \
(((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & \
WLAN_SYSTEM_SLEEP_DISABLE_MASK)
#define SI_CONFIG_BIDIR_OD_DATA_SET(x) \
(((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
#define SI_CONFIG_POS_SAMPLE_SET(x) \
(((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
#define SI_CONFIG_INACTIVE_CLK_SET(x) \
(((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
#define SI_CONFIG_INACTIVE_DATA_SET(x) \
(((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
#define SI_CONFIG_DIVIDER_SET(x) \
(((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
#define LPO_CAL_ENABLE_SET(x) \
(((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK)
#define CPU_CLOCK_STANDARD_SET(x) \
(((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK)
#define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x) \
(((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
/* copy_engine.c */
/* end */
/* PLL start */
#define EFUSE_XTAL_SEL_GET(x) \
(((x) & EFUSE_XTAL_SEL_MASK) >> EFUSE_XTAL_SEL_LSB)
#define EFUSE_XTAL_SEL_SET(x) \
(((x) << EFUSE_XTAL_SEL_LSB) & EFUSE_XTAL_SEL_MASK)
#define BB_PLL_CONFIG_OUTDIV_GET(x) \
(((x) & BB_PLL_CONFIG_OUTDIV_MASK) >> BB_PLL_CONFIG_OUTDIV_LSB)
#define BB_PLL_CONFIG_OUTDIV_SET(x) \
(((x) << BB_PLL_CONFIG_OUTDIV_LSB) & BB_PLL_CONFIG_OUTDIV_MASK)
#define BB_PLL_CONFIG_FRAC_GET(x) \
(((x) & BB_PLL_CONFIG_FRAC_MASK) >> BB_PLL_CONFIG_FRAC_LSB)
#define BB_PLL_CONFIG_FRAC_SET(x) \
(((x) << BB_PLL_CONFIG_FRAC_LSB) & BB_PLL_CONFIG_FRAC_MASK)
#define WLAN_PLL_SETTLE_TIME_GET(x) \
(((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB)
#define WLAN_PLL_SETTLE_TIME_SET(x) \
(((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK)
#define WLAN_PLL_CONTROL_NOPWD_GET(x) \
(((x) & WLAN_PLL_CONTROL_NOPWD_MASK) >> WLAN_PLL_CONTROL_NOPWD_LSB)
#define WLAN_PLL_CONTROL_NOPWD_SET(x) \
(((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & WLAN_PLL_CONTROL_NOPWD_MASK)
#define WLAN_PLL_CONTROL_BYPASS_GET(x) \
(((x) & WLAN_PLL_CONTROL_BYPASS_MASK) >> WLAN_PLL_CONTROL_BYPASS_LSB)
#define WLAN_PLL_CONTROL_BYPASS_SET(x) \
(((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & WLAN_PLL_CONTROL_BYPASS_MASK)
#define WLAN_PLL_CONTROL_CLK_SEL_GET(x) \
(((x) & WLAN_PLL_CONTROL_CLK_SEL_MASK) >> WLAN_PLL_CONTROL_CLK_SEL_LSB)
#define WLAN_PLL_CONTROL_CLK_SEL_SET(x) \
(((x) << WLAN_PLL_CONTROL_CLK_SEL_LSB) & WLAN_PLL_CONTROL_CLK_SEL_MASK)
#define WLAN_PLL_CONTROL_REFDIV_GET(x) \
(((x) & WLAN_PLL_CONTROL_REFDIV_MASK) >> WLAN_PLL_CONTROL_REFDIV_LSB)
#define WLAN_PLL_CONTROL_REFDIV_SET(x) \
(((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & WLAN_PLL_CONTROL_REFDIV_MASK)
#define WLAN_PLL_CONTROL_DIV_GET(x) \
(((x) & WLAN_PLL_CONTROL_DIV_MASK) >> WLAN_PLL_CONTROL_DIV_LSB)
#define WLAN_PLL_CONTROL_DIV_SET(x) \
(((x) << WLAN_PLL_CONTROL_DIV_LSB) & WLAN_PLL_CONTROL_DIV_MASK)
#define SOC_CORE_CLK_CTRL_DIV_GET(x) \
(((x) & SOC_CORE_CLK_CTRL_DIV_MASK) >> SOC_CORE_CLK_CTRL_DIV_LSB)
#define SOC_CORE_CLK_CTRL_DIV_SET(x) \
(((x) << SOC_CORE_CLK_CTRL_DIV_LSB) & SOC_CORE_CLK_CTRL_DIV_MASK)
#define RTC_SYNC_STATUS_PLL_CHANGING_GET(x) \
(((x) & RTC_SYNC_STATUS_PLL_CHANGING_MASK) >> \
RTC_SYNC_STATUS_PLL_CHANGING_LSB)
#define RTC_SYNC_STATUS_PLL_CHANGING_SET(x) \
(((x) << RTC_SYNC_STATUS_PLL_CHANGING_LSB) & \
RTC_SYNC_STATUS_PLL_CHANGING_MASK)
#define SOC_CPU_CLOCK_STANDARD_GET(x) \
(((x) & SOC_CPU_CLOCK_STANDARD_MASK) >> SOC_CPU_CLOCK_STANDARD_LSB)
#define SOC_CPU_CLOCK_STANDARD_SET(x) \
(((x) << SOC_CPU_CLOCK_STANDARD_LSB) & SOC_CPU_CLOCK_STANDARD_MASK)
/* PLL end */
#ifdef QCA_WIFI_3_0_ADRASTEA
#define Q6_ENABLE_REGISTER_0 \
(scn->targetdef->d_Q6_ENABLE_REGISTER_0)
#define Q6_ENABLE_REGISTER_1 \
(scn->targetdef->d_Q6_ENABLE_REGISTER_1)
#define Q6_CAUSE_REGISTER_0 \
(scn->targetdef->d_Q6_CAUSE_REGISTER_0)
#define Q6_CAUSE_REGISTER_1 \
(scn->targetdef->d_Q6_CAUSE_REGISTER_1)
#define Q6_CLEAR_REGISTER_0 \
(scn->targetdef->d_Q6_CLEAR_REGISTER_0)
#define Q6_CLEAR_REGISTER_1 \
(scn->targetdef->d_Q6_CLEAR_REGISTER_1)
#endif
struct hostdef_s {
uint32_t d_INT_STATUS_ENABLE_ERROR_LSB;
uint32_t d_INT_STATUS_ENABLE_ERROR_MASK;
uint32_t d_INT_STATUS_ENABLE_CPU_LSB;
uint32_t d_INT_STATUS_ENABLE_CPU_MASK;
uint32_t d_INT_STATUS_ENABLE_COUNTER_LSB;
uint32_t d_INT_STATUS_ENABLE_COUNTER_MASK;
uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_LSB;
uint32_t d_INT_STATUS_ENABLE_MBOX_DATA_MASK;
uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB;
uint32_t d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK;
uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB;
uint32_t d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK;
uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_LSB;
uint32_t d_COUNTER_INT_STATUS_ENABLE_BIT_MASK;
uint32_t d_INT_STATUS_ENABLE_ADDRESS;
uint32_t d_CPU_INT_STATUS_ENABLE_BIT_LSB;
uint32_t d_CPU_INT_STATUS_ENABLE_BIT_MASK;
uint32_t d_HOST_INT_STATUS_ADDRESS;
uint32_t d_CPU_INT_STATUS_ADDRESS;
uint32_t d_ERROR_INT_STATUS_ADDRESS;
uint32_t d_ERROR_INT_STATUS_WAKEUP_MASK;
uint32_t d_ERROR_INT_STATUS_WAKEUP_LSB;
uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK;
uint32_t d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB;
uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_MASK;
uint32_t d_ERROR_INT_STATUS_TX_OVERFLOW_LSB;
uint32_t d_COUNT_DEC_ADDRESS;
uint32_t d_HOST_INT_STATUS_CPU_MASK;
uint32_t d_HOST_INT_STATUS_CPU_LSB;
uint32_t d_HOST_INT_STATUS_ERROR_MASK;
uint32_t d_HOST_INT_STATUS_ERROR_LSB;
uint32_t d_HOST_INT_STATUS_COUNTER_MASK;
uint32_t d_HOST_INT_STATUS_COUNTER_LSB;
uint32_t d_RX_LOOKAHEAD_VALID_ADDRESS;
uint32_t d_WINDOW_DATA_ADDRESS;
uint32_t d_WINDOW_READ_ADDR_ADDRESS;
uint32_t d_WINDOW_WRITE_ADDR_ADDRESS;
uint32_t d_SOC_GLOBAL_RESET_ADDRESS;
uint32_t d_RTC_STATE_ADDRESS;
uint32_t d_RTC_STATE_COLD_RESET_MASK;
uint32_t d_RTC_STATE_V_MASK;
uint32_t d_RTC_STATE_V_LSB;
uint32_t d_FW_IND_EVENT_PENDING;
uint32_t d_FW_IND_INITIALIZED;
uint32_t d_FW_IND_HELPER;
uint32_t d_RTC_STATE_V_ON;
#if defined(SDIO_3_0)
uint32_t d_HOST_INT_STATUS_MBOX_DATA_MASK;
uint32_t d_HOST_INT_STATUS_MBOX_DATA_LSB;
#endif
uint32_t d_MSI_MAGIC_ADR_ADDRESS;
uint32_t d_MSI_MAGIC_ADDRESS;
uint32_t d_ENABLE_MSI;
uint32_t d_MUX_ID_MASK;
uint32_t d_TRANSACTION_ID_MASK;
uint32_t d_DESC_DATA_FLAG_MASK;
};
#define DESC_DATA_FLAG_MASK (scn->hostdef->d_DESC_DATA_FLAG_MASK)
#define MUX_ID_MASK (scn->hostdef->d_MUX_ID_MASK)
#define TRANSACTION_ID_MASK (scn->hostdef->d_TRANSACTION_ID_MASK)
#define ENABLE_MSI (scn->hostdef->d_ENABLE_MSI)
#define INT_STATUS_ENABLE_ERROR_LSB \
(scn->hostdef->d_INT_STATUS_ENABLE_ERROR_LSB)
#define INT_STATUS_ENABLE_ERROR_MASK \
(scn->hostdef->d_INT_STATUS_ENABLE_ERROR_MASK)
#define INT_STATUS_ENABLE_CPU_LSB (scn->hostdef->d_INT_STATUS_ENABLE_CPU_LSB)
#define INT_STATUS_ENABLE_CPU_MASK (scn->hostdef->d_INT_STATUS_ENABLE_CPU_MASK)
#define INT_STATUS_ENABLE_COUNTER_LSB \
(scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_LSB)
#define INT_STATUS_ENABLE_COUNTER_MASK \
(scn->hostdef->d_INT_STATUS_ENABLE_COUNTER_MASK)
#define INT_STATUS_ENABLE_MBOX_DATA_LSB \
(scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_LSB)
#define INT_STATUS_ENABLE_MBOX_DATA_MASK \
(scn->hostdef->d_INT_STATUS_ENABLE_MBOX_DATA_MASK)
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB \
(scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK \
(scn->hostdef->d_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB \
(scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK \
(scn->hostdef->d_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
#define COUNTER_INT_STATUS_ENABLE_BIT_LSB \
(scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_LSB)
#define COUNTER_INT_STATUS_ENABLE_BIT_MASK \
(scn->hostdef->d_COUNTER_INT_STATUS_ENABLE_BIT_MASK)
#define INT_STATUS_ENABLE_ADDRESS \
(scn->hostdef->d_INT_STATUS_ENABLE_ADDRESS)
#define CPU_INT_STATUS_ENABLE_BIT_LSB \
(scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_LSB)
#define CPU_INT_STATUS_ENABLE_BIT_MASK \
(scn->hostdef->d_CPU_INT_STATUS_ENABLE_BIT_MASK)
#define HOST_INT_STATUS_ADDRESS (scn->hostdef->d_HOST_INT_STATUS_ADDRESS)
#define CPU_INT_STATUS_ADDRESS (scn->hostdef->d_CPU_INT_STATUS_ADDRESS)
#define ERROR_INT_STATUS_ADDRESS (scn->hostdef->d_ERROR_INT_STATUS_ADDRESS)
#define ERROR_INT_STATUS_WAKEUP_MASK \
(scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_MASK)
#define ERROR_INT_STATUS_WAKEUP_LSB \
(scn->hostdef->d_ERROR_INT_STATUS_WAKEUP_LSB)
#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK \
(scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB \
(scn->hostdef->d_ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
#define ERROR_INT_STATUS_TX_OVERFLOW_MASK \
(scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_MASK)
#define ERROR_INT_STATUS_TX_OVERFLOW_LSB \
(scn->hostdef->d_ERROR_INT_STATUS_TX_OVERFLOW_LSB)
#define COUNT_DEC_ADDRESS (scn->hostdef->d_COUNT_DEC_ADDRESS)
#define HOST_INT_STATUS_CPU_MASK (scn->hostdef->d_HOST_INT_STATUS_CPU_MASK)
#define HOST_INT_STATUS_CPU_LSB (scn->hostdef->d_HOST_INT_STATUS_CPU_LSB)
#define HOST_INT_STATUS_ERROR_MASK (scn->hostdef->d_HOST_INT_STATUS_ERROR_MASK)
#define HOST_INT_STATUS_ERROR_LSB (scn->hostdef->d_HOST_INT_STATUS_ERROR_LSB)
#define HOST_INT_STATUS_COUNTER_MASK \
(scn->hostdef->d_HOST_INT_STATUS_COUNTER_MASK)
#define HOST_INT_STATUS_COUNTER_LSB \
(scn->hostdef->d_HOST_INT_STATUS_COUNTER_LSB)
#define RX_LOOKAHEAD_VALID_ADDRESS (scn->hostdef->d_RX_LOOKAHEAD_VALID_ADDRESS)
#define WINDOW_DATA_ADDRESS (scn->hostdef->d_WINDOW_DATA_ADDRESS)
#define WINDOW_READ_ADDR_ADDRESS (scn->hostdef->d_WINDOW_READ_ADDR_ADDRESS)
#define WINDOW_WRITE_ADDR_ADDRESS (scn->hostdef->d_WINDOW_WRITE_ADDR_ADDRESS)
#define SOC_GLOBAL_RESET_ADDRESS (scn->hostdef->d_SOC_GLOBAL_RESET_ADDRESS)
#define RTC_STATE_ADDRESS (scn->hostdef->d_RTC_STATE_ADDRESS)
#define RTC_STATE_COLD_RESET_MASK (scn->hostdef->d_RTC_STATE_COLD_RESET_MASK)
#define RTC_STATE_V_MASK (scn->hostdef->d_RTC_STATE_V_MASK)
#define RTC_STATE_V_LSB (scn->hostdef->d_RTC_STATE_V_LSB)
#define FW_IND_EVENT_PENDING (scn->hostdef->d_FW_IND_EVENT_PENDING)
#define FW_IND_INITIALIZED (scn->hostdef->d_FW_IND_INITIALIZED)
#define FW_IND_HELPER (scn->hostdef->d_FW_IND_HELPER)
#define RTC_STATE_V_ON (scn->hostdef->d_RTC_STATE_V_ON)
#if defined(SDIO_3_0)
#define HOST_INT_STATUS_MBOX_DATA_MASK \
(scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_MASK)
#define HOST_INT_STATUS_MBOX_DATA_LSB \
(scn->hostdef->d_HOST_INT_STATUS_MBOX_DATA_LSB)
#endif
#if !defined(MSI_MAGIC_ADR_ADDRESS)
#define MSI_MAGIC_ADR_ADDRESS 0
#define MSI_MAGIC_ADDRESS 0
#endif
/* SET/GET macros */
#define INT_STATUS_ENABLE_ERROR_SET(x) \
(((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
#define INT_STATUS_ENABLE_CPU_SET(x) \
(((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
#define INT_STATUS_ENABLE_COUNTER_SET(x) \
(((x) << INT_STATUS_ENABLE_COUNTER_LSB) & \
INT_STATUS_ENABLE_COUNTER_MASK)
#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) \
(((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & \
INT_STATUS_ENABLE_MBOX_DATA_MASK)
#define CPU_INT_STATUS_ENABLE_BIT_SET(x) \
(((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & \
CPU_INT_STATUS_ENABLE_BIT_MASK)
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) \
(((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & \
ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) \
(((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & \
ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) \
(((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & \
COUNTER_INT_STATUS_ENABLE_BIT_MASK)
#define ERROR_INT_STATUS_WAKEUP_GET(x) \
(((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> \
ERROR_INT_STATUS_WAKEUP_LSB)
#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) \
(((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> \
ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) \
(((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> \
ERROR_INT_STATUS_TX_OVERFLOW_LSB)
#define HOST_INT_STATUS_CPU_GET(x) \
(((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
#define HOST_INT_STATUS_ERROR_GET(x) \
(((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
#define HOST_INT_STATUS_COUNTER_GET(x) \
(((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
#define RTC_STATE_V_GET(x) \
(((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
#if defined(SDIO_3_0)
#define HOST_INT_STATUS_MBOX_DATA_GET(x) \
(((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> \
HOST_INT_STATUS_MBOX_DATA_LSB)
#endif
#define INVALID_REG_LOC_DUMMY_DATA 0xAA
#define AR6320_CORE_CLK_DIV_ADDR 0x403fa8
#define AR6320_CPU_PLL_INIT_DONE_ADDR 0x403fd0
#define AR6320_CPU_SPEED_ADDR 0x403fa4
#define AR6320V2_CORE_CLK_DIV_ADDR 0x403fd8
#define AR6320V2_CPU_PLL_INIT_DONE_ADDR 0x403fd0
#define AR6320V2_CPU_SPEED_ADDR 0x403fd4
#define AR6320V3_CORE_CLK_DIV_ADDR 0x404028
#define AR6320V3_CPU_PLL_INIT_DONE_ADDR 0x404020
#define AR6320V3_CPU_SPEED_ADDR 0x404024
typedef enum {
SOC_REFCLK_UNKNOWN = -1, /* Unsupported ref clock -- use PLL Bypass */
SOC_REFCLK_48_MHZ = 0,
SOC_REFCLK_19_2_MHZ = 1,
SOC_REFCLK_24_MHZ = 2,
SOC_REFCLK_26_MHZ = 3,
SOC_REFCLK_37_4_MHZ = 4,
SOC_REFCLK_38_4_MHZ = 5,
SOC_REFCLK_40_MHZ = 6,
SOC_REFCLK_52_MHZ = 7,
} A_refclk_speed_t;
#define A_REFCLK_UNKNOWN SOC_REFCLK_UNKNOWN
#define A_REFCLK_48_MHZ SOC_REFCLK_48_MHZ
#define A_REFCLK_19_2_MHZ SOC_REFCLK_19_2_MHZ
#define A_REFCLK_24_MHZ SOC_REFCLK_24_MHZ
#define A_REFCLK_26_MHZ SOC_REFCLK_26_MHZ
#define A_REFCLK_37_4_MHZ SOC_REFCLK_37_4_MHZ
#define A_REFCLK_38_4_MHZ SOC_REFCLK_38_4_MHZ
#define A_REFCLK_40_MHZ SOC_REFCLK_40_MHZ
#define A_REFCLK_52_MHZ SOC_REFCLK_52_MHZ
#define TARGET_CPU_FREQ 176000000
struct wlan_pll_s {
uint32_t refdiv;
uint32_t div;
uint32_t rnfrac;
uint32_t outdiv;
};
struct cmnos_clock_s {
A_refclk_speed_t refclk_speed;
uint32_t refclk_hz;
uint32_t pll_settling_time; /* 50us */
struct wlan_pll_s wlan_pll;
};
typedef struct TGT_REG_SECTION {
uint32_t start_addr;
uint32_t end_addr;
} tgt_reg_section;
typedef struct TGT_REG_TABLE {
tgt_reg_section *section;
uint32_t section_size;
} tgt_reg_table;
#endif /* _REGTABLE_SDIO_H_ */

4
qdf/inc/qdf_status.h
Wyświetl plik

@@ -60,8 +60,10 @@
* @QDF_STATUS_E_ENXIO: No such device or address
* @QDF_STATUS_E_NETDOWN: network is down
* @QDF_STATUS_E_IO: I/O Error
* @QDF_STATUS_E_PENDING: pending status
* @QDF_STATUS_E_NETRESET: Network dropped connection because of reset
* @QDF_STATUS_E_SIG: Exit due to received SIGINT
* @QDF_STATUS_E_PROTO: protocol error
* @QDF_STATUS_NOT_INITIALIZED: resource not initialized
* @QDF_STATUS_E_NULL_VALUE: request is null
* @QDF_STATUS_PMC_PENDING: request pendign in pmc
@@ -103,8 +105,10 @@ typedef enum {
QDF_STATUS_E_ENXIO,
QDF_STATUS_E_NETDOWN,
QDF_STATUS_E_IO,
QDF_STATUS_E_PENDING,
QDF_STATUS_E_NETRESET,
QDF_STATUS_E_SIG,
QDF_STATUS_E_PROTO,
QDF_STATUS_NOT_INITIALIZED,
QDF_STATUS_E_NULL_VALUE,
QDF_STATUS_PMC_PENDING,

3
qdf/linux/src/i_qdf_types.h
Wyświetl plik

@@ -160,7 +160,8 @@ enum qdf_bus_type {
QDF_BUS_TYPE_PCI = 0,
QDF_BUS_TYPE_AHB,
QDF_BUS_TYPE_SNOC,
QDF_BUS_TYPE_SIM
QDF_BUS_TYPE_SIM,
QDF_BUS_TYPE_SDIO
};
/**