From 4bafb26a4c497f70272746c21506c401ba956cd0 Mon Sep 17 00:00:00 2001 From: Manikanta Pubbisetty Date: Wed, 8 Nov 2023 14:55:22 +0530 Subject: [PATCH] qcacmn: Fix batch interrupt threshold logic for WCN6450 Unlike lithium family, batch interrupt thresholds for Rhine targets are not based on the entry size (descriptor size in dwords); Instead the configuration should be a simple integer value. If interrupt has to be raised after every copy transaction then batch counter threshold shall be set to 1, so on and so forth. Change-Id: Ic51f361c5f079d48668ec9b46dd79f04bcb43b14 CRs-Fixed: 3659426 --- hif/src/ce/ce_service_legacy.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hif/src/ce/ce_service_legacy.c b/hif/src/ce/ce_service_legacy.c index c955eec5f5..c9b649dae1 100644 --- a/hif/src/ce/ce_service_legacy.c +++ b/hif/src/ce/ce_service_legacy.c @@ -1418,9 +1418,8 @@ static void ce_legacy_src_ring_setup(struct hif_softc *scn, uint32_t ce_id, if (!(CE_ATTR_DISABLE_INTR & attr->flags)) { /* In 8us units */ timer_thrs = CE_SRC_BATCH_TIMER_THRESHOLD >> 3; - /* Batch counter threshold 1 in Dwrod units */ - count_thrs = (CE_SRC_BATCH_COUNTER_THRESHOLD * - (sizeof(struct CE_src_desc) >> 2)); + count_thrs = CE_SRC_BATCH_COUNTER_THRESHOLD; + ce_legacy_msi_param_setup(scn, ctrl_addr, ce_id, attr); ce_legacy_src_intr_thres_setup(scn, ctrl_addr, attr, timer_thrs, count_thrs); @@ -1470,7 +1469,6 @@ static void ce_legacy_dest_ring_setup(struct hif_softc *scn, uint32_t ce_id, if (!(CE_ATTR_DISABLE_INTR & attr->flags)) { /* In 8us units */ timer_thrs = CE_DST_BATCH_TIMER_THRESHOLD >> 3; - /* Batch counter threshold 1 in Dwrod units */ count_thrs = CE_DST_BATCH_COUNTER_THRESHOLD; ce_legacy_msi_param_setup(scn, ctrl_addr, ce_id, attr);