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msm: camera: isp: CSID Driver Refactoring

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Due to major hw changes in latest CSID680 IP block, refactoring of
CSID kernel driver is required.
To support the hw speciific driver, version based files
are added. One common file to support the common functionality
and common utilities has also been added.

CRs-Fixed: 2830502
Change-Id: If1e2a0835ce285f968f154d2da5595e882ae6ccd
Signed-off-by: Gaurav Jindal <gjindal@codeaurora.org>
This commit is contained in:
Gaurav Jindal
2020-11-16 19:30:37 +05:30
parent 5418bcb5d6
commit 4b58880f6f
36 changed files with 16482 additions and 9513 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/Makefile
View File

@@ -64,9 +64,11 @@ camera-$(CONFIG_SPECTRA_ISP) += \
cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.o \ cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.o \
cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_dev.o \ cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_dev.o \
cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_soc.o \ cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_soc.o \
cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.o \ cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.o \
cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid17x.o \ cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver1.o \
cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite17x.o \ cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.o \
cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_mod.o \
cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite_mod.o \
cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.o \ cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_soc.o \
cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_dev.o \ cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_dev.o \
cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.o \ cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.o \
@@ -219,7 +221,6 @@ camera-$(CONFIG_SPECTRA_TFE) += \
cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.o \ cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid530.o \
cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.o cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.o
camera-y += camera_main.o camera-y += camera_main.o
obj-$(CONFIG_SPECTRA_CAMERA) += camera.o obj-$(CONFIG_SPECTRA_CAMERA) += camera.o

456
drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/cam_custom_csid480.h
View File

@@ -6,253 +6,269 @@
#ifndef _CAM_CUSTOM_CSID_480_H_ #ifndef _CAM_CUSTOM_CSID_480_H_
#define _CAM_CUSTOM_CSID_480_H_ #define _CAM_CUSTOM_CSID_480_H_
#include "cam_ife_csid_core.h" #include "cam_ife_csid_common.h"
#include "cam_ife_csid_hw_ver1.h"
#define CAM_CSID_VERSION_V480 0x40080000 #define CAM_CSID_VERSION_V480 0x40080000
static struct cam_ife_csid_udi_reg_offset static struct cam_ife_csid_ver1_path_reg_info
cam_custom_csid_480_udi_0_reg_offset = { cam_custom_csid_480_udi_0_reg_offset = {
.csid_udi_irq_status_addr = 0x30, .irq_status_addr = 0x30,
.csid_udi_irq_mask_addr = 0x34, .irq_mask_addr = 0x34,
.csid_udi_irq_clear_addr = 0x38, .irq_clear_addr = 0x38,
.csid_udi_irq_set_addr = 0x3c, .irq_set_addr = 0x3c,
.csid_udi_cfg0_addr = 0x200, .cfg0_addr = 0x200,
.csid_udi_cfg1_addr = 0x204, .cfg1_addr = 0x204,
.csid_udi_ctrl_addr = 0x208, .ctrl_addr = 0x208,
.csid_udi_frm_drop_pattern_addr = 0x20c, .frm_drop_pattern_addr = 0x20c,
.csid_udi_frm_drop_period_addr = 0x210, .frm_drop_period_addr = 0x210,
.csid_udi_irq_subsample_pattern_addr = 0x214, .irq_subsample_pattern_addr = 0x214,
.csid_udi_irq_subsample_period_addr = 0x218, .irq_subsample_period_addr = 0x218,
.csid_udi_rpp_hcrop_addr = 0x21c, .hcrop_addr = 0x21c,
.csid_udi_rpp_vcrop_addr = 0x220, .vcrop_addr = 0x220,
.csid_udi_rpp_pix_drop_pattern_addr = 0x224, .pix_drop_pattern_addr = 0x224,
.csid_udi_rpp_pix_drop_period_addr = 0x228, .pix_drop_period_addr = 0x228,
.csid_udi_rpp_line_drop_pattern_addr = 0x22c, .line_drop_pattern_addr = 0x22c,
.csid_udi_rpp_line_drop_period_addr = 0x230, .line_drop_period_addr = 0x230,
.csid_udi_rst_strobes_addr = 0x240, .rst_strobes_addr = 0x240,
.csid_udi_status_addr = 0x250, .status_addr = 0x250,
.csid_udi_misr_val0_addr = 0x254, .misr_val0_addr = 0x254,
.csid_udi_misr_val1_addr = 0x258, .misr_val1_addr = 0x258,
.csid_udi_misr_val2_addr = 0x25c, .misr_val2_addr = 0x25c,
.csid_udi_misr_val3_addr = 0x260, .misr_val3_addr = 0x260,
.csid_udi_format_measure_cfg0_addr = 0x270, .format_measure_cfg0_addr = 0x270,
.csid_udi_format_measure_cfg1_addr = 0x274, .format_measure_cfg1_addr = 0x274,
.csid_udi_format_measure0_addr = 0x278, .format_measure0_addr = 0x278,
.csid_udi_format_measure1_addr = 0x27c, .format_measure1_addr = 0x27c,
.csid_udi_format_measure2_addr = 0x280, .format_measure2_addr = 0x280,
.csid_udi_timestamp_curr0_sof_addr = 0x290, .timestamp_curr0_sof_addr = 0x290,
.csid_udi_timestamp_curr1_sof_addr = 0x294, .timestamp_curr1_sof_addr = 0x294,
.csid_udi_timestamp_prev0_sof_addr = 0x298, .timestamp_prev0_sof_addr = 0x298,
.csid_udi_timestamp_prev1_sof_addr = 0x29c, .timestamp_prev1_sof_addr = 0x29c,
.csid_udi_timestamp_curr0_eof_addr = 0x2a0, .timestamp_curr0_eof_addr = 0x2a0,
.csid_udi_timestamp_curr1_eof_addr = 0x2a4, .timestamp_curr1_eof_addr = 0x2a4,
.csid_udi_timestamp_prev0_eof_addr = 0x2a8, .timestamp_prev0_eof_addr = 0x2a8,
.csid_udi_timestamp_prev1_eof_addr = 0x2ac, .timestamp_prev1_eof_addr = 0x2ac,
.csid_udi_err_recovery_cfg0_addr = 0x2b0, .err_recovery_cfg0_addr = 0x2b0,
.csid_udi_err_recovery_cfg1_addr = 0x2b4, .err_recovery_cfg1_addr = 0x2b4,
.csid_udi_err_recovery_cfg2_addr = 0x2b8, .err_recovery_cfg2_addr = 0x2b8,
.csid_udi_multi_vcdt_cfg0_addr = 0x2bc, .multi_vcdt_cfg0_addr = 0x2bc,
.csid_udi_byte_cntr_ping_addr = 0x2e0, .byte_cntr_ping_addr = 0x2e0,
.csid_udi_byte_cntr_pong_addr = 0x2e4, .byte_cntr_pong_addr = 0x2e4,
/* configurations */ /* configurations */
.ccif_violation_en = 1, .plain_fmt_shift_val = 10,
.overflow_ctrl_en = 0, .crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.ccif_violation_en = 1,
.overflow_ctrl_en = 0,
}; };
static struct cam_ife_csid_udi_reg_offset static struct cam_ife_csid_ver1_path_reg_info
cam_custom_csid_480_udi_1_reg_offset = { cam_custom_csid_480_udi_1_reg_offset = {
.csid_udi_irq_status_addr = 0x40, .irq_status_addr = 0x40,
.csid_udi_irq_mask_addr = 0x44, .irq_mask_addr = 0x44,
.csid_udi_irq_clear_addr = 0x48, .irq_clear_addr = 0x48,
.csid_udi_irq_set_addr = 0x4c, .irq_set_addr = 0x4c,
.csid_udi_cfg0_addr = 0x300, .cfg0_addr = 0x300,
.csid_udi_cfg1_addr = 0x304, .cfg1_addr = 0x304,
.csid_udi_ctrl_addr = 0x308, .ctrl_addr = 0x308,
.csid_udi_frm_drop_pattern_addr = 0x30c, .frm_drop_pattern_addr = 0x30c,
.csid_udi_frm_drop_period_addr = 0x310, .frm_drop_period_addr = 0x310,
.csid_udi_irq_subsample_pattern_addr = 0x314, .irq_subsample_pattern_addr = 0x314,
.csid_udi_irq_subsample_period_addr = 0x318, .irq_subsample_period_addr = 0x318,
.csid_udi_rpp_hcrop_addr = 0x31c, .hcrop_addr = 0x31c,
.csid_udi_rpp_vcrop_addr = 0x320, .vcrop_addr = 0x320,
.csid_udi_rpp_pix_drop_pattern_addr = 0x324, .pix_drop_pattern_addr = 0x324,
.csid_udi_rpp_pix_drop_period_addr = 0x328, .pix_drop_period_addr = 0x328,
.csid_udi_rpp_line_drop_pattern_addr = 0x32c, .line_drop_pattern_addr = 0x32c,
.csid_udi_rpp_line_drop_period_addr = 0x330, .line_drop_period_addr = 0x330,
.csid_udi_rst_strobes_addr = 0x340, .rst_strobes_addr = 0x340,
.csid_udi_status_addr = 0x350, .status_addr = 0x350,
.csid_udi_misr_val0_addr = 0x354, .misr_val0_addr = 0x354,
.csid_udi_misr_val1_addr = 0x358, .misr_val1_addr = 0x358,
.csid_udi_misr_val2_addr = 0x35c, .misr_val2_addr = 0x35c,
.csid_udi_misr_val3_addr = 0x360, .misr_val3_addr = 0x360,
.csid_udi_format_measure_cfg0_addr = 0x370, .format_measure_cfg0_addr = 0x370,
.csid_udi_format_measure_cfg1_addr = 0x374, .format_measure_cfg1_addr = 0x374,
.csid_udi_format_measure0_addr = 0x378, .format_measure0_addr = 0x378,
.csid_udi_format_measure1_addr = 0x37c, .format_measure1_addr = 0x37c,
.csid_udi_format_measure2_addr = 0x380, .format_measure2_addr = 0x380,
.csid_udi_timestamp_curr0_sof_addr = 0x390, .timestamp_curr0_sof_addr = 0x390,
.csid_udi_timestamp_curr1_sof_addr = 0x394, .timestamp_curr1_sof_addr = 0x394,
.csid_udi_timestamp_prev0_sof_addr = 0x398, .timestamp_prev0_sof_addr = 0x398,
.csid_udi_timestamp_prev1_sof_addr = 0x39c, .timestamp_prev1_sof_addr = 0x39c,
.csid_udi_timestamp_curr0_eof_addr = 0x3a0, .timestamp_curr0_eof_addr = 0x3a0,
.csid_udi_timestamp_curr1_eof_addr = 0x3a4, .timestamp_curr1_eof_addr = 0x3a4,
.csid_udi_timestamp_prev0_eof_addr = 0x3a8, .timestamp_prev0_eof_addr = 0x3a8,
.csid_udi_timestamp_prev1_eof_addr = 0x3ac, .timestamp_prev1_eof_addr = 0x3ac,
.csid_udi_err_recovery_cfg0_addr = 0x3b0, .err_recovery_cfg0_addr = 0x3b0,
.csid_udi_err_recovery_cfg1_addr = 0x3b4, .err_recovery_cfg1_addr = 0x3b4,
.csid_udi_err_recovery_cfg2_addr = 0x3b8, .err_recovery_cfg2_addr = 0x3b8,
.csid_udi_multi_vcdt_cfg0_addr = 0x3bc, .multi_vcdt_cfg0_addr = 0x3bc,
.csid_udi_byte_cntr_ping_addr = 0x3e0, .byte_cntr_ping_addr = 0x3e0,
.csid_udi_byte_cntr_pong_addr = 0x3e4, .byte_cntr_pong_addr = 0x3e4,
/* configurations */ /* configurations */
.ccif_violation_en = 1, .mipi_pack_supported = 1,
.overflow_ctrl_en = 0, .packing_fmt_shift_val = 30,
.plain_fmt_shift_val = 10,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.drop_v_en_shift_val = 4,
.drop_h_en_shift_val = 3,
.timestamp_en_shift_val = 2,
.ccif_violation_en = 1,
.format_measure_en_shift_val = 1,
.overflow_ctrl_en = 0,
.non_fatal_err_mask = 0x28000,
.non_fatal_err_mask = 0x4,
.overflow_ctrl_mode_val = 0x8,
}; };
static struct cam_ife_csid_udi_reg_offset static struct cam_ife_csid_ver1_path_reg_info
cam_custom_csid_480_udi_2_reg_offset = { cam_custom_csid_480_udi_2_reg_offset = {
.csid_udi_irq_status_addr = 0x50, .irq_status_addr = 0x50,
.csid_udi_irq_mask_addr = 0x54, .irq_mask_addr = 0x54,
.csid_udi_irq_clear_addr = 0x58, .irq_clear_addr = 0x58,
.csid_udi_irq_set_addr = 0x5c, .irq_set_addr = 0x5c,
.csid_udi_cfg0_addr = 0x400, .cfg0_addr = 0x400,
.csid_udi_cfg1_addr = 0x404, .cfg1_addr = 0x404,
.csid_udi_ctrl_addr = 0x408, .ctrl_addr = 0x408,
.csid_udi_frm_drop_pattern_addr = 0x40c, .frm_drop_pattern_addr = 0x40c,
.csid_udi_frm_drop_period_addr = 0x410, .frm_drop_period_addr = 0x410,
.csid_udi_irq_subsample_pattern_addr = 0x414, .irq_subsample_pattern_addr = 0x414,
.csid_udi_irq_subsample_period_addr = 0x418, .irq_subsample_period_addr = 0x418,
.csid_udi_rpp_hcrop_addr = 0x41c, .hcrop_addr = 0x41c,
.csid_udi_rpp_vcrop_addr = 0x420, .vcrop_addr = 0x420,
.csid_udi_rpp_pix_drop_pattern_addr = 0x424, .pix_drop_pattern_addr = 0x424,
.csid_udi_rpp_pix_drop_period_addr = 0x428, .pix_drop_period_addr = 0x428,
.csid_udi_rpp_line_drop_pattern_addr = 0x42c, .line_drop_pattern_addr = 0x42c,
.csid_udi_rpp_line_drop_period_addr = 0x430, .line_drop_period_addr = 0x430,
.csid_udi_yuv_chroma_conversion_addr = 0x434, .yuv_chroma_conversion_addr = 0x434,
.csid_udi_rst_strobes_addr = 0x440, .rst_strobes_addr = 0x440,
.csid_udi_status_addr = 0x450, .status_addr = 0x450,
.csid_udi_misr_val0_addr = 0x454, .misr_val0_addr = 0x454,
.csid_udi_misr_val1_addr = 0x458, .misr_val1_addr = 0x458,
.csid_udi_misr_val2_addr = 0x45c, .misr_val2_addr = 0x45c,
.csid_udi_misr_val3_addr = 0x460, .misr_val3_addr = 0x460,
.csid_udi_format_measure_cfg0_addr = 0x470, .format_measure_cfg0_addr = 0x470,
.csid_udi_format_measure_cfg1_addr = 0x474, .format_measure_cfg1_addr = 0x474,
.csid_udi_format_measure0_addr = 0x478, .format_measure0_addr = 0x478,
.csid_udi_format_measure1_addr = 0x47c, .format_measure1_addr = 0x47c,
.csid_udi_format_measure2_addr = 0x480, .format_measure2_addr = 0x480,
.csid_udi_timestamp_curr0_sof_addr = 0x490, .timestamp_curr0_sof_addr = 0x490,
.csid_udi_timestamp_curr1_sof_addr = 0x494, .timestamp_curr1_sof_addr = 0x494,
.csid_udi_timestamp_prev0_sof_addr = 0x498, .timestamp_prev0_sof_addr = 0x498,
.csid_udi_timestamp_prev1_sof_addr = 0x49c, .timestamp_prev1_sof_addr = 0x49c,
.csid_udi_timestamp_curr0_eof_addr = 0x4a0, .timestamp_curr0_eof_addr = 0x4a0,
.csid_udi_timestamp_curr1_eof_addr = 0x4a4, .timestamp_curr1_eof_addr = 0x4a4,
.csid_udi_timestamp_prev0_eof_addr = 0x4a8, .timestamp_prev0_eof_addr = 0x4a8,
.csid_udi_timestamp_prev1_eof_addr = 0x4ac, .timestamp_prev1_eof_addr = 0x4ac,
.csid_udi_err_recovery_cfg0_addr = 0x4b0, .err_recovery_cfg0_addr = 0x4b0,
.csid_udi_err_recovery_cfg1_addr = 0x4b4, .err_recovery_cfg1_addr = 0x4b4,
.csid_udi_err_recovery_cfg2_addr = 0x4b8, .err_recovery_cfg2_addr = 0x4b8,
.csid_udi_multi_vcdt_cfg0_addr = 0x4bc, .multi_vcdt_cfg0_addr = 0x4bc,
.csid_udi_byte_cntr_ping_addr = 0x4e0, .byte_cntr_ping_addr = 0x4e0,
.csid_udi_byte_cntr_pong_addr = 0x4e4, .byte_cntr_pong_addr = 0x4e4,
/* configurations */ /* configurations */
.ccif_violation_en = 1, .plain_fmt_shift_val = 10,
.overflow_ctrl_en = 0, .crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.ccif_violation_en = 1,
.overflow_ctrl_en = 0,
}; };
static struct cam_ife_csid_csi2_rx_reg_offset static struct cam_ife_csid_csi2_rx_reg_info
cam_custom_csid_480_csi2_reg_offset = { cam_custom_csid_480_csi2_reg_info = {
.csid_csi2_rx_irq_status_addr = 0x20, .irq_status_addr = 0x20,
.csid_csi2_rx_irq_mask_addr = 0x24, .irq_mask_addr = 0x24,
.csid_csi2_rx_irq_clear_addr = 0x28, .irq_clear_addr = 0x28,
.csid_csi2_rx_irq_set_addr = 0x2c, .irq_set_addr = 0x2c,
/*CSI2 rx control */ /*CSI2 rx control */
.csid_csi2_rx_cfg0_addr = 0x100, .cfg0_addr = 0x100,
.csid_csi2_rx_cfg1_addr = 0x104, .cfg1_addr = 0x104,
.csid_csi2_rx_capture_ctrl_addr = 0x108, .capture_ctrl_addr = 0x108,
.csid_csi2_rx_rst_strobes_addr = 0x110, .rst_strobes_addr = 0x110,
.csid_csi2_rx_de_scramble_cfg0_addr = 0x114, .de_scramble_cfg0_addr = 0x114,
.csid_csi2_rx_de_scramble_cfg1_addr = 0x118, .de_scramble_cfg1_addr = 0x118,
.csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr = 0x120, .cap_unmap_long_pkt_hdr_0_addr = 0x120,
.csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr = 0x124, .cap_unmap_long_pkt_hdr_1_addr = 0x124,
.csid_csi2_rx_captured_short_pkt_0_addr = 0x128, .captured_short_pkt_0_addr = 0x128,
.csid_csi2_rx_captured_short_pkt_1_addr = 0x12c, .captured_short_pkt_1_addr = 0x12c,
.csid_csi2_rx_captured_long_pkt_0_addr = 0x130, .captured_long_pkt_0_addr = 0x130,
.csid_csi2_rx_captured_long_pkt_1_addr = 0x134, .captured_long_pkt_1_addr = 0x134,
.csid_csi2_rx_captured_long_pkt_ftr_addr = 0x138, .captured_long_pkt_ftr_addr = 0x138,
.csid_csi2_rx_captured_cphy_pkt_hdr_addr = 0x13c, .captured_cphy_pkt_hdr_addr = 0x13c,
.csid_csi2_rx_lane0_misr_addr = 0x150, .lane0_misr_addr = 0x150,
.csid_csi2_rx_lane1_misr_addr = 0x154, .lane1_misr_addr = 0x154,
.csid_csi2_rx_lane2_misr_addr = 0x158, .lane2_misr_addr = 0x158,
.csid_csi2_rx_lane3_misr_addr = 0x15c, .lane3_misr_addr = 0x15c,
.csid_csi2_rx_total_pkts_rcvd_addr = 0x160, .total_pkts_rcvd_addr = 0x160,
.csid_csi2_rx_stats_ecc_addr = 0x164, .stats_ecc_addr = 0x164,
.csid_csi2_rx_total_crc_err_addr = 0x168, .total_crc_err_addr = 0x168,
.csi2_rst_srb_all = 0x3FFF, .rst_srb_all = 0x3FFF,
.csi2_rst_done_shift_val = 27, .rst_done_shift_val = 27,
.csi2_irq_mask_all = 0xFFFFFFF, .irq_mask_all = 0xFFFFFFF,
.csi2_misr_enable_shift_val = 6, .misr_enable_shift_val = 6,
.csi2_vc_mode_shift_val = 2, .vc_mode_shift_val = 2,
.csi2_capture_long_pkt_en_shift = 0, .capture_long_pkt_en_shift = 0,
.csi2_capture_short_pkt_en_shift = 1, .capture_short_pkt_en_shift = 1,
.csi2_capture_cphy_pkt_en_shift = 2, .capture_cphy_pkt_en_shift = 2,
.csi2_capture_long_pkt_dt_shift = 4, .capture_long_pkt_dt_shift = 4,
.csi2_capture_long_pkt_vc_shift = 10, .capture_long_pkt_vc_shift = 10,
.csi2_capture_short_pkt_vc_shift = 15, .capture_short_pkt_vc_shift = 15,
.csi2_capture_cphy_pkt_dt_shift = 20, .capture_cphy_pkt_dt_shift = 20,
.csi2_capture_cphy_pkt_vc_shift = 26, .capture_cphy_pkt_vc_shift = 26,
.csi2_rx_phy_num_mask = 0x3, .phy_num_mask = 0x3,
.fatal_err_mask = 0x78000,
.part_fatal_err_mask = 0x1801800,
}; };
static struct cam_ife_csid_common_reg_offset static struct cam_ife_csid_ver1_common_reg_info
cam_custom_csid_480_cmn_reg_offset = { cam_custom_csid_480_cmn_reg_offset = {
.csid_hw_version_addr = 0x0, .hw_version_addr = 0x0,
.csid_cfg0_addr = 0x4, .cfg0_addr = 0x4,
.csid_ctrl_addr = 0x8, .ctrl_addr = 0x8,
.csid_reset_addr = 0xc, .reset_addr = 0xc,
.csid_rst_strobes_addr = 0x10, .rst_strobes_addr = 0x10,
.csid_test_bus_ctrl_addr = 0x14, .test_bus_ctrl_addr = 0x14,
.csid_top_irq_status_addr = 0x70, .top_irq_status_addr = 0x70,
.csid_top_irq_mask_addr = 0x74, .top_irq_mask_addr = 0x74,
.csid_top_irq_clear_addr = 0x78, .top_irq_clear_addr = 0x78,
.csid_top_irq_set_addr = 0x7c, .top_irq_set_addr = 0x7c,
.csid_irq_cmd_addr = 0x80, .irq_cmd_addr = 0x80,
/*configurations */ /*configurations */
.major_version = 1, .major_version = 1,
.minor_version = 7, .minor_version = 7,
.version_incr = 0, .version_incr = 0,
.num_udis = 3, .num_udis = 3,
.num_rdis = 0, .num_rdis = 0,
.num_pix = 0, .num_pix = 0,
.num_ppp = 0, .num_ppp = 0,
.csid_reg_rst_stb = 1, .rst_sw_reg_stb = 1,
.csid_rst_stb = 0x1e, .rst_hw_reg_stb = 0x1e,
.csid_rst_stb_sw_all = 0x1f, .rst_sw_hw_reg_stb = 0x1f,
.path_rst_stb_all = 0x7f, .path_rst_stb_all = 0x7f,
.path_rst_done_shift_val = 1, .rst_done_shift_val = 1,
.path_en_shift_val = 31, .path_en_shift_val = 31,
.dt_id_shift_val = 27, .dt_id_shift_val = 27,
.vc_shift_val = 22, .vc_shift_val = 22,
.dt_shift_val = 16, .dt_shift_val = 16,
.fmt_shift_val = 12, .fmt_shift_val = 12,
.plain_fmt_shit_val = 10, .ipp_irq_mask_all = 0,
.crop_v_en_shift_val = 6, .rdi_irq_mask_all = 0,
.crop_h_en_shift_val = 5, .ppp_irq_mask_all = 0,
.crop_shift = 16, .udi_irq_mask_all = 0x7FFF,
.ipp_irq_mask_all = 0, .measure_en_hbi_vbi_cnt_mask = 0xC,
.rdi_irq_mask_all = 0, .num_bytes_out_shift_val = 3,
.ppp_irq_mask_all = 0,
.udi_irq_mask_all = 0x7FFF,
.measure_en_hbi_vbi_cnt_mask = 0xC,
.format_measure_en_val = 1,
.num_bytes_out_shift_val = 3,
}; };
static struct cam_ife_csid_reg_offset cam_custom_csid_480_reg_offset = { static struct cam_ife_csid_ver1_reg_info cam_custom_csid_480_reg_offset = {
.cmn_reg = &cam_custom_csid_480_cmn_reg_offset, .cmn_reg = &cam_custom_csid_480_cmn_reg_offset,
.csi2_reg = &cam_custom_csid_480_csi2_reg_offset, .csi2_reg = &cam_custom_csid_480_csi2_reg_info,
.ipp_reg = NULL, .ipp_reg = NULL,
.ppp_reg = NULL, .ppp_reg = NULL,
.rdi_reg = { .rdi_reg = {

66
drivers/cam_cust/cam_custom_hw_mgr/cam_custom_csid/cam_custom_csid_dev.c
View File

@@ -9,7 +9,7 @@
#include <linux/of_device.h> #include <linux/of_device.h>
#include "linux/module.h" #include "linux/module.h"
#include "cam_custom_csid_dev.h" #include "cam_custom_csid_dev.h"
#include "cam_ife_csid_core.h" #include "cam_ife_csid_common.h"
#include "cam_hw.h" #include "cam_hw.h"
#include "cam_hw_intf.h" #include "cam_hw_intf.h"
#include "cam_custom_csid480.h" #include "cam_custom_csid480.h"
@@ -23,20 +23,18 @@ static struct cam_hw_intf *cam_custom_csid_hw_list[CAM_IFE_CSID_HW_NUM_MAX] = {
static char csid_dev_name[16]; static char csid_dev_name[16];
static struct cam_ife_csid_hw_info cam_custom_csid480_hw_info = { static struct cam_ife_csid_core_info cam_custom_csid480_hw_info = {
.csid_reg = &cam_custom_csid_480_reg_offset, .csid_reg = &cam_custom_csid_480_reg_offset,
.hw_dts_version = CAM_CSID_VERSION_V480, .sw_version = CAM_IFE_CSID_VER_1_0,
}; };
static int cam_custom_csid_component_bind(struct device *dev, static int cam_custom_csid_component_bind(struct device *dev,
struct device *master_dev, void *data) struct device *master_dev, void *data)
{ {
struct cam_hw_intf *csid_hw_intf; struct cam_hw_intf *csid_hw_intf;
struct cam_hw_info *csid_hw_info; struct cam_hw_info *csid_hw_info;
struct cam_ife_csid_hw *csid_dev = NULL;
const struct of_device_id *match_dev = NULL; const struct of_device_id *match_dev = NULL;
struct cam_ife_csid_hw_info *csid_hw_data = NULL; struct cam_ife_csid_core_info *csid_core_info = NULL;
uint32_t csid_dev_idx; uint32_t csid_dev_idx;
int rc = 0; int rc = 0;
struct platform_device *pdev = to_platform_device(dev); struct platform_device *pdev = to_platform_device(dev);
@@ -48,17 +46,12 @@ static int cam_custom_csid_component_bind(struct device *dev,
} }
csid_hw_info = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); csid_hw_info = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL);
if (!csid_hw_info) { if (!csid_hw_info) {
rc = -ENOMEM; rc = -ENOMEM;
goto free_hw_intf; goto free_hw_intf;
} }
csid_dev = kzalloc(sizeof(struct cam_ife_csid_hw), GFP_KERNEL);
if (!csid_dev) {
rc = -ENOMEM;
goto free_hw_info;
}
/* get custom csid hw index */ /* get custom csid hw index */
of_property_read_u32(pdev->dev.of_node, "cell-index", &csid_dev_idx); of_property_read_u32(pdev->dev.of_node, "cell-index", &csid_dev_idx);
/* get custom csid hw information */ /* get custom csid hw information */
@@ -68,7 +61,7 @@ static int cam_custom_csid_component_bind(struct device *dev,
CAM_ERR(CAM_CUSTOM, CAM_ERR(CAM_CUSTOM,
"No matching table for the CUSTOM CSID HW!"); "No matching table for the CUSTOM CSID HW!");
rc = -EINVAL; rc = -EINVAL;
goto free_dev; goto free_hw_info;
} }
memset(csid_dev_name, 0, sizeof(csid_dev_name)); memset(csid_dev_name, 0, sizeof(csid_dev_name));
@@ -79,33 +72,36 @@ static int cam_custom_csid_component_bind(struct device *dev,
csid_hw_intf->hw_type = CAM_ISP_HW_TYPE_IFE_CSID; csid_hw_intf->hw_type = CAM_ISP_HW_TYPE_IFE_CSID;
csid_hw_intf->hw_priv = csid_hw_info; csid_hw_intf->hw_priv = csid_hw_info;
csid_hw_info->core_info = csid_dev;
csid_hw_info->soc_info.pdev = pdev; csid_hw_info->soc_info.pdev = pdev;
csid_hw_info->soc_info.dev = &pdev->dev; csid_hw_info->soc_info.dev = &pdev->dev;
csid_hw_info->soc_info.dev_name = csid_dev_name; csid_hw_info->soc_info.dev_name = csid_dev_name;
csid_hw_info->soc_info.index = csid_dev_idx; csid_hw_info->soc_info.index = csid_dev_idx;
csid_hw_data = (struct cam_ife_csid_hw_info *)match_dev->data; csid_core_info = (struct cam_ife_csid_core_info *)match_dev->data;
csid_dev->csid_info = csid_hw_data;
rc = cam_ife_csid_hw_probe_init(csid_hw_intf, csid_dev_idx, true); /* call the driver init and fill csid_hw_info->core_info */
if (rc) rc = cam_ife_csid_hw_probe_init(csid_hw_intf, csid_core_info, true);
goto free_dev;
platform_set_drvdata(pdev, csid_dev); if (rc) {
CAM_ERR(CAM_ISP, "CSID[%d] probe init failed",
csid_dev_idx);
goto free_hw_info;
}
platform_set_drvdata(pdev, csid_hw_intf);
CAM_DBG(CAM_ISP, "CSID:%d component bound successfully",
csid_hw_intf->hw_idx);
if (csid_hw_intf->hw_idx < CAM_IFE_CSID_HW_NUM_MAX) if (csid_hw_intf->hw_idx < CAM_IFE_CSID_HW_NUM_MAX)
cam_custom_csid_hw_list[csid_hw_intf->hw_idx] = csid_hw_intf; cam_custom_csid_hw_list[csid_hw_intf->hw_idx] = csid_hw_intf;
else else
goto free_dev; goto free_hw_info;
CAM_DBG(CAM_CUSTOM, "CSID:%d component bound successfully", CAM_DBG(CAM_CUSTOM, "CSID:%d component bound successfully",
csid_hw_intf->hw_idx); csid_hw_intf->hw_idx);
return 0; return 0;
free_dev:
kfree(csid_dev);
free_hw_info: free_hw_info:
kfree(csid_hw_info); kfree(csid_hw_info);
free_hw_intf: free_hw_intf:
@@ -117,22 +113,30 @@ err:
static void cam_custom_csid_component_unbind(struct device *dev, static void cam_custom_csid_component_unbind(struct device *dev,
struct device *master_dev, void *data) struct device *master_dev, void *data)
{ {
struct cam_ife_csid_hw *csid_dev = NULL;
struct cam_hw_intf *csid_hw_intf; struct cam_hw_intf *csid_hw_intf;
struct cam_hw_info *csid_hw_info; struct cam_hw_info *csid_hw_info;
struct cam_ife_csid_core_info *core_info = NULL;
struct platform_device *pdev = to_platform_device(dev); struct platform_device *pdev = to_platform_device(dev);
const struct of_device_id *match_dev = NULL;
csid_dev = (struct cam_ife_csid_hw *)platform_get_drvdata(pdev); csid_hw_intf = (struct cam_hw_intf *)platform_get_drvdata(pdev);
csid_hw_intf = csid_dev->hw_intf; csid_hw_info = csid_hw_intf->hw_priv;
csid_hw_info = csid_dev->hw_info;
CAM_DBG(CAM_CUSTOM, "CSID:%d component unbind", CAM_DBG(CAM_CUSTOM, "CSID:%d component unbind",
csid_dev->hw_intf->hw_idx); csid_hw_intf->hw_idx);
cam_ife_csid_hw_deinit(csid_dev); match_dev = of_match_device(pdev->dev.driver->of_match_table,
&pdev->dev);
if (!match_dev) {
CAM_ERR(CAM_ISP, "No matching table for the IFE CSID HW!");
goto free_mem;
}
cam_ife_csid_hw_deinit(csid_hw_intf, core_info);
free_mem:
/*release the csid device memory */ /*release the csid device memory */
kfree(csid_dev);
kfree(csid_hw_info); kfree(csid_hw_info);
kfree(csid_hw_intf); kfree(csid_hw_intf);
} }
@@ -169,7 +173,7 @@ static const struct of_device_id cam_custom_csid_dt_match[] = {
.compatible = "qcom,csid-custom580", .compatible = "qcom,csid-custom580",
.data = &cam_custom_csid480_hw_info .data = &cam_custom_csid480_hw_info
}, },
{} {},
}; };
MODULE_DEVICE_TABLE(of, cam_custom_csid_dt_match); MODULE_DEVICE_TABLE(of, cam_custom_csid_dt_match);

1
drivers/cam_cust/cam_custom_hw_mgr/cam_custom_hw_mgr.c
View File

@@ -777,7 +777,6 @@ static int cam_custom_hw_mgr_acquire_csid_res(
memset(&custom_csid_acquire, 0, sizeof(custom_csid_acquire)); memset(&custom_csid_acquire, 0, sizeof(custom_csid_acquire));
custom_csid_acquire.res_id = path_res_id; custom_csid_acquire.res_id = path_res_id;
custom_csid_acquire.res_type = CAM_ISP_RESOURCE_PIX_PATH; custom_csid_acquire.res_type = CAM_ISP_RESOURCE_PIX_PATH;
custom_csid_acquire.cid = cid_rsrc_node->res_id;
custom_csid_acquire.in_port = in_port_info; custom_csid_acquire.in_port = in_port_info;
custom_csid_acquire.out_port = out_port; custom_csid_acquire.out_port = out_port;
custom_csid_acquire.sync_mode = 0; custom_csid_acquire.sync_mode = 0;

966
drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c
View File

File diff suppressed because it is too large Load Diff

12
drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h
View File

@@ -42,8 +42,8 @@ struct cam_ife_hw_mgr_debug {
struct dentry *dentry; struct dentry *dentry;
uint64_t csid_debug; uint64_t csid_debug;
uint32_t enable_recovery; uint32_t enable_recovery;
uint32_t enable_csid_recovery;
uint32_t camif_debug; uint32_t camif_debug;
uint32_t enable_csid_recovery;
bool enable_req_dump; bool enable_req_dump;
bool per_req_reg_dump; bool per_req_reg_dump;
bool disable_ubwc_comp; bool disable_ubwc_comp;
@@ -105,6 +105,9 @@ struct cam_ife_hw_mgr_debug {
* @hw_enabled Array to indicate active HW * @hw_enabled Array to indicate active HW
* @internal_cdm Indicate whether context uses internal CDM * @internal_cdm Indicate whether context uses internal CDM
* @pf_mid_found in page fault, mid found for this ctx. * @pf_mid_found in page fault, mid found for this ctx.
* @buf_done_controller Buf done controller.
* @need_csid_top_cfg Flag to indicate if CSID top cfg is needed.
*
*/ */
struct cam_ife_hw_mgr_ctx { struct cam_ife_hw_mgr_ctx {
struct list_head list; struct list_head list;
@@ -118,7 +121,6 @@ struct cam_ife_hw_mgr_ctx {
struct cam_isp_hw_mgr_res res_list_ife_in; struct cam_isp_hw_mgr_res res_list_ife_in;
struct cam_isp_hw_mgr_res res_list_tpg; struct cam_isp_hw_mgr_res res_list_tpg;
struct list_head res_list_ife_cid;
struct list_head res_list_ife_csid; struct list_head res_list_ife_csid;
struct list_head res_list_ife_src; struct list_head res_list_ife_src;
struct list_head res_list_ife_in_rd; struct list_head res_list_ife_in_rd;
@@ -160,6 +162,8 @@ struct cam_ife_hw_mgr_ctx {
bool dsp_enabled; bool dsp_enabled;
bool internal_cdm; bool internal_cdm;
bool pf_mid_found; bool pf_mid_found;
bool need_csid_top_cfg;
void *buf_done_controller;
}; };
/** /**
@@ -182,6 +186,8 @@ struct cam_ife_hw_mgr_ctx {
* @support_consumed_addr indicate whether hw supports last consumed address * @support_consumed_addr indicate whether hw supports last consumed address
* @hw_pid_support hw pid support for this target * @hw_pid_support hw pid support for this target
* @max_vfe_out_res_type max ife out res type value from hw * @max_vfe_out_res_type max ife out res type value from hw
* @csid_rup_en Reg update at CSID side
* @csid_global_reset_en CSID global reset enable
*/ */
struct cam_ife_hw_mgr { struct cam_ife_hw_mgr {
struct cam_isp_hw_mgr mgr_common; struct cam_isp_hw_mgr mgr_common;
@@ -205,6 +211,8 @@ struct cam_ife_hw_mgr {
bool support_consumed_addr; bool support_consumed_addr;
bool hw_pid_support; bool hw_pid_support;
uint32_t max_vfe_out_res_type; uint32_t max_vfe_out_res_type;
bool csid_rup_en;
bool csid_global_reset_en;
}; };
/** /**

109
drivers/cam_isp/isp_hw_mgr/hw_utils/cam_isp_packet_parser.c
View File

@@ -1304,3 +1304,112 @@ int cam_isp_add_wait_trigger(
return rc; return rc;
} }
int cam_isp_add_csid_reg_update(
struct cam_hw_prepare_update_args *prepare,
struct list_head *res_list,
uint32_t base_idx,
struct cam_kmd_buf_info *kmd_buf_info)
{
int rc = 0;
struct cam_isp_hw_mgr_res *hw_mgr_res;
struct cam_isp_resource_node *res;
uint32_t kmd_buf_remain_size, num_ent, i, reg_update_size, hw_idx;
struct cam_ife_csid_reg_update_args
rup_args[CAM_IFE_CSID_HW_NUM_MAX] = {0};
if (prepare->num_hw_update_entries + 1 >=
prepare->max_hw_update_entries) {
CAM_ERR(CAM_ISP, "Insufficient HW entries :%d %d",
prepare->num_hw_update_entries,
prepare->max_hw_update_entries);
return -EINVAL;
}
reg_update_size = 0;
list_for_each_entry(hw_mgr_res, res_list, list) {
if (hw_mgr_res->res_type == CAM_ISP_RESOURCE_UNINT)
continue;
for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) {
if (!hw_mgr_res->hw_res[i])
continue;
if (i == CAM_ISP_HW_SPLIT_RIGHT)
continue;
res = hw_mgr_res->hw_res[i];
if (res->hw_intf->hw_idx != base_idx)
continue;
hw_idx = res->hw_intf->hw_idx;
rup_args[hw_idx].res[rup_args[hw_idx].num_res] = res;
rup_args[hw_idx].num_res++;
CAM_DBG(CAM_ISP,
"Reg update added for res %d hw_id %d cdm_idx %d",
res->res_id, res->hw_intf->hw_idx, base_idx);
}
}
for (i = 0; i < CAM_IFE_CSID_HW_NUM_MAX; i++) {
if (!rup_args[i].num_res)
continue;
if (kmd_buf_info->size > (kmd_buf_info->used_bytes +
reg_update_size)) {
kmd_buf_remain_size = kmd_buf_info->size -
(kmd_buf_info->used_bytes +
reg_update_size);
} else {
CAM_ERR(CAM_ISP, "no free mem %d %d %d",
base_idx, kmd_buf_info->size,
kmd_buf_info->used_bytes +
reg_update_size);
rc = -EINVAL;
return rc;
}
rup_args[i].cmd.cmd_buf_addr = kmd_buf_info->cpu_addr +
kmd_buf_info->used_bytes/4 +
reg_update_size/4;
rup_args[i].cmd.size = kmd_buf_remain_size;
res = rup_args[i].res[0];
rc = res->hw_intf->hw_ops.process_cmd(
res->hw_intf->hw_priv,
CAM_ISP_HW_CMD_GET_REG_UPDATE, &rup_args[i],
sizeof(struct cam_ife_csid_reg_update_args));
if (rc)
return rc;
CAM_DBG(CAM_ISP,
"Reg update added for res %d hw_id %d cdm_idx %d",
res->res_id, res->hw_intf->hw_idx, base_idx);
reg_update_size += rup_args[i].cmd.used_bytes;
}
if (reg_update_size) {
/* Update the HW entries */
num_ent = prepare->num_hw_update_entries;
prepare->hw_update_entries[num_ent].handle =
kmd_buf_info->handle;
prepare->hw_update_entries[num_ent].len = reg_update_size;
prepare->hw_update_entries[num_ent].offset =
kmd_buf_info->offset;
/* Marking reg update as IOCFG to reapply on bubble */
prepare->hw_update_entries[num_ent].flags = CAM_ISP_IOCFG_BL;
CAM_DBG(CAM_ISP,
"num_ent=%d handle=0x%x, len=%u, offset=%u",
num_ent,
prepare->hw_update_entries[num_ent].handle,
prepare->hw_update_entries[num_ent].len,
prepare->hw_update_entries[num_ent].offset);
num_ent++;
kmd_buf_info->used_bytes += reg_update_size;
kmd_buf_info->offset += reg_update_size;
prepare->num_hw_update_entries = num_ent;
/* reg update is success return status 0 */
rc = 0;
}
return rc;
}

18
drivers/cam_isp/isp_hw_mgr/hw_utils/include/cam_isp_packet_parser.h
View File

@@ -249,4 +249,22 @@ int cam_isp_add_go_cmd(
uint32_t base_idx, uint32_t base_idx,
struct cam_kmd_buf_info *kmd_buf_info); struct cam_kmd_buf_info *kmd_buf_info);
/* cam_isp_csid_add_reg_update()
*
* @brief Add csid reg update in the hw entries list
* processe the isp source list get the reg update from
* ISP HW instance
*
* @prepare: Contain the packet and HW update variables
* @res_list_isp_src: Resource list for IFE/VFE source
* @base_idx: Base or dev index of the IFE/VFE HW instance
* @kmd_buf_info: Kmd buffer to store the change base command
* @return: 0 for success
* -EINVAL for Fail
*/
int cam_isp_add_csid_reg_update(
struct cam_hw_prepare_update_args *prepare,
struct list_head *res_list,
uint32_t base_idx,
struct cam_kmd_buf_info *kmd_buf_info);
#endif /*_CAM_ISP_HW_PARSER_H */ #endif /*_CAM_ISP_HW_PARSER_H */

638
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid170.h
View File

@@ -2,308 +2,404 @@
/* /*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
*/ */
#ifndef _CAM_IFE_CSID_170_H_ #ifndef _CAM_IFE_CSID_170_H_
#define _CAM_IFE_CSID_170_H_ #define _CAM_IFE_CSID_170_H_
#include "cam_ife_csid_core.h" #include <linux/module.h>
#include "cam_ife_csid_common.h"
#include "cam_ife_csid_hw_ver1.h"
#include "cam_ife_csid_dev.h"
#include "camera_main.h"
static struct cam_ife_csid_pxl_reg_offset cam_ife_csid_170_ipp_reg_offset = { #define CAM_CSID_VERSION_V170 0x10070000
.csid_pxl_irq_status_addr = 0x30,
.csid_pxl_irq_mask_addr = 0x34,
.csid_pxl_irq_clear_addr = 0x38,
.csid_pxl_irq_set_addr = 0x3c,
.csid_pxl_cfg0_addr = 0x200, static struct cam_ife_csid_ver1_path_reg_info
.csid_pxl_cfg1_addr = 0x204, cam_ife_csid_170_ipp_reg_info = {
.csid_pxl_ctrl_addr = 0x208, .irq_status_addr = 0x30,
.csid_pxl_frm_drop_pattern_addr = 0x20c, .irq_mask_addr = 0x34,
.csid_pxl_frm_drop_period_addr = 0x210, .irq_clear_addr = 0x38,
.csid_pxl_irq_subsample_pattern_addr = 0x214, .irq_set_addr = 0x3c,
.csid_pxl_irq_subsample_period_addr = 0x218, .cfg0_addr = 0x200,
.csid_pxl_hcrop_addr = 0x21c, .cfg1_addr = 0x204,
.csid_pxl_vcrop_addr = 0x220, .ctrl_addr = 0x208,
.csid_pxl_pix_drop_pattern_addr = 0x224, .frm_drop_pattern_addr = 0x20c,
.csid_pxl_pix_drop_period_addr = 0x228, .frm_drop_period_addr = 0x210,
.csid_pxl_line_drop_pattern_addr = 0x22c, .irq_subsample_pattern_addr = 0x214,
.csid_pxl_line_drop_period_addr = 0x230, .irq_subsample_period_addr = 0x218,
.csid_pxl_rst_strobes_addr = 0x240, .hcrop_addr = 0x21c,
.csid_pxl_status_addr = 0x254, .vcrop_addr = 0x220,
.csid_pxl_misr_val_addr = 0x258, .pix_drop_pattern_addr = 0x224,
.csid_pxl_format_measure_cfg0_addr = 0x270, .pix_drop_period_addr = 0x228,
.csid_pxl_format_measure_cfg1_addr = 0x274, .line_drop_pattern_addr = 0x22c,
.csid_pxl_format_measure0_addr = 0x278, .line_drop_period_addr = 0x230,
.csid_pxl_format_measure1_addr = 0x27c, .rst_strobes_addr = 0x240,
.csid_pxl_format_measure2_addr = 0x280, .status_addr = 0x254,
.csid_pxl_timestamp_curr0_sof_addr = 0x290, .misr_val_addr = 0x258,
.csid_pxl_timestamp_curr1_sof_addr = 0x294, .format_measure_cfg0_addr = 0x270,
.csid_pxl_timestamp_perv0_sof_addr = 0x298, .format_measure_cfg1_addr = 0x274,
.csid_pxl_timestamp_perv1_sof_addr = 0x29c, .format_measure0_addr = 0x278,
.csid_pxl_timestamp_curr0_eof_addr = 0x2a0, .format_measure1_addr = 0x27c,
.csid_pxl_timestamp_curr1_eof_addr = 0x2a4, .format_measure2_addr = 0x280,
.csid_pxl_timestamp_perv0_eof_addr = 0x2a8, .timestamp_curr0_sof_addr = 0x290,
.csid_pxl_timestamp_perv1_eof_addr = 0x2ac, .timestamp_curr1_sof_addr = 0x294,
.timestamp_prev0_sof_addr = 0x298,
.timestamp_prev1_sof_addr = 0x29c,
.timestamp_curr0_eof_addr = 0x2a0,
.timestamp_curr1_eof_addr = 0x2a4,
.timestamp_prev0_eof_addr = 0x2a8,
.timestamp_prev1_eof_addr = 0x2ac,
/* configurations */ /* configurations */
.pix_store_en_shift_val = 7, .crop_v_en_shift_val = 6,
.early_eof_en_shift_val = 29, .crop_h_en_shift_val = 5,
.pix_store_en_shift_val = 7,
.halt_master_sel_master_val = 0,
.halt_master_sel_shift = 4,
.halt_mode_internal = 0,
.halt_mode_global = 1,
.halt_mode_master = 2,
.halt_mode_slave = 3,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.early_eof_en_shift_val = 29,
.timestamp_en_shift_val = 2,
.format_measure_en_shift_val = 0,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x8000,
}; };
static struct cam_ife_csid_rdi_reg_offset cam_ife_csid_170_rdi_0_reg_offset = { static struct cam_ife_csid_ver1_path_reg_info
.csid_rdi_irq_status_addr = 0x40, cam_ife_csid_170_rdi_0_reg_info = {
.csid_rdi_irq_mask_addr = 0x44, .irq_status_addr = 0x40,
.csid_rdi_irq_clear_addr = 0x48, .irq_mask_addr = 0x44,
.csid_rdi_irq_set_addr = 0x4c, .irq_clear_addr = 0x48,
.csid_rdi_cfg0_addr = 0x300, .irq_set_addr = 0x4c,
.csid_rdi_cfg1_addr = 0x304, .cfg0_addr = 0x300,
.csid_rdi_ctrl_addr = 0x308, .cfg1_addr = 0x304,
.csid_rdi_frm_drop_pattern_addr = 0x30c, .ctrl_addr = 0x308,
.csid_rdi_frm_drop_period_addr = 0x310, .frm_drop_pattern_addr = 0x30c,
.csid_rdi_irq_subsample_pattern_addr = 0x314, .frm_drop_period_addr = 0x310,
.csid_rdi_irq_subsample_period_addr = 0x318, .irq_subsample_pattern_addr = 0x314,
.csid_rdi_rpp_hcrop_addr = 0x31c, .irq_subsample_period_addr = 0x318,
.csid_rdi_rpp_vcrop_addr = 0x320, .hcrop_addr = 0x31c,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x324, .vcrop_addr = 0x320,
.csid_rdi_rpp_pix_drop_period_addr = 0x328, .pix_drop_pattern_addr = 0x324,
.csid_rdi_rpp_line_drop_pattern_addr = 0x32c, .pix_drop_period_addr = 0x328,
.csid_rdi_rpp_line_drop_period_addr = 0x330, .line_drop_pattern_addr = 0x32c,
.csid_rdi_rst_strobes_addr = 0x340, .line_drop_period_addr = 0x330,
.csid_rdi_status_addr = 0x350, .rst_strobes_addr = 0x340,
.csid_rdi_misr_val0_addr = 0x354, .status_addr = 0x350,
.csid_rdi_misr_val1_addr = 0x358, .misr_val0_addr = 0x354,
.csid_rdi_misr_val2_addr = 0x35c, .misr_val1_addr = 0x358,
.csid_rdi_misr_val3_addr = 0x360, .misr_val2_addr = 0x35c,
.csid_rdi_format_measure_cfg0_addr = 0x370, .misr_val3_addr = 0x360,
.csid_rdi_format_measure_cfg1_addr = 0x374, .format_measure_cfg0_addr = 0x370,
.csid_rdi_format_measure0_addr = 0x378, .format_measure_cfg1_addr = 0x374,
.csid_rdi_format_measure1_addr = 0x37c, .format_measure0_addr = 0x378,
.csid_rdi_format_measure2_addr = 0x380, .format_measure1_addr = 0x37c,
.csid_rdi_timestamp_curr0_sof_addr = 0x390, .format_measure2_addr = 0x380,
.csid_rdi_timestamp_curr1_sof_addr = 0x394, .timestamp_curr0_sof_addr = 0x390,
.csid_rdi_timestamp_prev0_sof_addr = 0x398, .timestamp_curr1_sof_addr = 0x394,
.csid_rdi_timestamp_prev1_sof_addr = 0x39c, .timestamp_prev0_sof_addr = 0x398,
.csid_rdi_timestamp_curr0_eof_addr = 0x3a0, .timestamp_prev1_sof_addr = 0x39c,
.csid_rdi_timestamp_curr1_eof_addr = 0x3a4, .timestamp_curr0_eof_addr = 0x3a0,
.csid_rdi_timestamp_prev0_eof_addr = 0x3a8, .timestamp_curr1_eof_addr = 0x3a4,
.csid_rdi_timestamp_prev1_eof_addr = 0x3ac, .timestamp_prev0_eof_addr = 0x3a8,
.csid_rdi_byte_cntr_ping_addr = 0x3e0, .timestamp_prev1_eof_addr = 0x3ac,
.csid_rdi_byte_cntr_pong_addr = 0x3e4, .byte_cntr_ping_addr = 0x3e0,
.byte_cntr_pong_addr = 0x3e4,
.halt_mode_internal = 0,
.halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.plain_fmt_shift_val = 10,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.timestamp_en_shift_val = 1,
.format_measure_en_shift_val = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x8000,
}; };
static struct cam_ife_csid_rdi_reg_offset cam_ife_csid_170_rdi_1_reg_offset = { static struct cam_ife_csid_ver1_path_reg_info
.csid_rdi_irq_status_addr = 0x50, cam_ife_csid_170_rdi_1_reg_info = {
.csid_rdi_irq_mask_addr = 0x54, .irq_status_addr = 0x50,
.csid_rdi_irq_clear_addr = 0x58, .irq_mask_addr = 0x54,
.csid_rdi_irq_set_addr = 0x5c, .irq_clear_addr = 0x58,
.csid_rdi_cfg0_addr = 0x400, .irq_set_addr = 0x5c,
.csid_rdi_cfg1_addr = 0x404, .cfg0_addr = 0x400,
.csid_rdi_ctrl_addr = 0x408, .cfg1_addr = 0x404,
.csid_rdi_frm_drop_pattern_addr = 0x40c, .ctrl_addr = 0x408,
.csid_rdi_frm_drop_period_addr = 0x410, .frm_drop_pattern_addr = 0x40c,
.csid_rdi_irq_subsample_pattern_addr = 0x414, .frm_drop_period_addr = 0x410,
.csid_rdi_irq_subsample_period_addr = 0x418, .irq_subsample_pattern_addr = 0x414,
.csid_rdi_rpp_hcrop_addr = 0x41c, .irq_subsample_period_addr = 0x418,
.csid_rdi_rpp_vcrop_addr = 0x420, .hcrop_addr = 0x41c,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x424, .vcrop_addr = 0x420,
.csid_rdi_rpp_pix_drop_period_addr = 0x428, .pix_drop_pattern_addr = 0x424,
.csid_rdi_rpp_line_drop_pattern_addr = 0x42c, .pix_drop_period_addr = 0x428,
.csid_rdi_rpp_line_drop_period_addr = 0x430, .line_drop_pattern_addr = 0x42c,
.csid_rdi_rst_strobes_addr = 0x440, .line_drop_period_addr = 0x430,
.csid_rdi_status_addr = 0x450, .rst_strobes_addr = 0x440,
.csid_rdi_misr_val0_addr = 0x454, .status_addr = 0x450,
.csid_rdi_misr_val1_addr = 0x458, .misr_val0_addr = 0x454,
.csid_rdi_misr_val2_addr = 0x45c, .misr_val1_addr = 0x458,
.csid_rdi_misr_val3_addr = 0x460, .misr_val2_addr = 0x45c,
.csid_rdi_format_measure_cfg0_addr = 0x470, .misr_val3_addr = 0x460,
.csid_rdi_format_measure_cfg1_addr = 0x474, .format_measure_cfg0_addr = 0x470,
.csid_rdi_format_measure0_addr = 0x478, .format_measure_cfg1_addr = 0x474,
.csid_rdi_format_measure1_addr = 0x47c, .format_measure0_addr = 0x478,
.csid_rdi_format_measure2_addr = 0x480, .format_measure1_addr = 0x47c,
.csid_rdi_timestamp_curr0_sof_addr = 0x490, .format_measure2_addr = 0x480,
.csid_rdi_timestamp_curr1_sof_addr = 0x494, .timestamp_curr0_sof_addr = 0x490,
.csid_rdi_timestamp_prev0_sof_addr = 0x498, .timestamp_curr1_sof_addr = 0x494,
.csid_rdi_timestamp_prev1_sof_addr = 0x49c, .timestamp_prev0_sof_addr = 0x498,
.csid_rdi_timestamp_curr0_eof_addr = 0x4a0, .timestamp_prev1_sof_addr = 0x49c,
.csid_rdi_timestamp_curr1_eof_addr = 0x4a4, .timestamp_curr0_eof_addr = 0x4a0,
.csid_rdi_timestamp_prev0_eof_addr = 0x4a8, .timestamp_curr1_eof_addr = 0x4a4,
.csid_rdi_timestamp_prev1_eof_addr = 0x4ac, .timestamp_prev0_eof_addr = 0x4a8,
.csid_rdi_byte_cntr_ping_addr = 0x4e0, .timestamp_prev1_eof_addr = 0x4ac,
.csid_rdi_byte_cntr_pong_addr = 0x4e4, .byte_cntr_ping_addr = 0x4e0,
.byte_cntr_pong_addr = 0x4e4,
.halt_mode_internal = 0,
.halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.plain_fmt_shift_val = 10,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.timestamp_en_shift_val = 1,
.format_measure_en_shift_val = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x8000,
}; };
static struct cam_ife_csid_rdi_reg_offset cam_ife_csid_170_rdi_2_reg_offset = { static struct cam_ife_csid_ver1_path_reg_info
.csid_rdi_irq_status_addr = 0x60, cam_ife_csid_170_rdi_2_reg_info = {
.csid_rdi_irq_mask_addr = 0x64, .irq_status_addr = 0x60,
.csid_rdi_irq_clear_addr = 0x68, .irq_mask_addr = 0x64,
.csid_rdi_irq_set_addr = 0x6c, .irq_clear_addr = 0x68,
.csid_rdi_cfg0_addr = 0x500, .irq_set_addr = 0x6c,
.csid_rdi_cfg1_addr = 0x504, .cfg0_addr = 0x500,
.csid_rdi_ctrl_addr = 0x508, .cfg1_addr = 0x504,
.csid_rdi_frm_drop_pattern_addr = 0x50c, .ctrl_addr = 0x508,
.csid_rdi_frm_drop_period_addr = 0x510, .frm_drop_pattern_addr = 0x50c,
.csid_rdi_irq_subsample_pattern_addr = 0x514, .frm_drop_period_addr = 0x510,
.csid_rdi_irq_subsample_period_addr = 0x518, .irq_subsample_pattern_addr = 0x514,
.csid_rdi_rpp_hcrop_addr = 0x51c, .irq_subsample_period_addr = 0x518,
.csid_rdi_rpp_vcrop_addr = 0x520, .hcrop_addr = 0x51c,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x524, .vcrop_addr = 0x520,
.csid_rdi_rpp_pix_drop_period_addr = 0x528, .pix_drop_pattern_addr = 0x524,
.csid_rdi_rpp_line_drop_pattern_addr = 0x52c, .pix_drop_period_addr = 0x528,
.csid_rdi_rpp_line_drop_period_addr = 0x530, .line_drop_pattern_addr = 0x52c,
.csid_rdi_yuv_chroma_conversion_addr = 0x534, .line_drop_period_addr = 0x530,
.csid_rdi_rst_strobes_addr = 0x540, .yuv_chroma_conversion_addr = 0x534,
.csid_rdi_status_addr = 0x550, .rst_strobes_addr = 0x540,
.csid_rdi_misr_val0_addr = 0x554, .status_addr = 0x550,
.csid_rdi_misr_val1_addr = 0x558, .misr_val0_addr = 0x554,
.csid_rdi_misr_val2_addr = 0x55c, .misr_val1_addr = 0x558,
.csid_rdi_misr_val3_addr = 0x560, .misr_val2_addr = 0x55c,
.csid_rdi_format_measure_cfg0_addr = 0x570, .misr_val3_addr = 0x560,
.csid_rdi_format_measure_cfg1_addr = 0x574, .format_measure_cfg0_addr = 0x570,
.csid_rdi_format_measure0_addr = 0x578, .format_measure_cfg1_addr = 0x574,
.csid_rdi_format_measure1_addr = 0x57c, .format_measure0_addr = 0x578,
.csid_rdi_format_measure2_addr = 0x580, .format_measure1_addr = 0x57c,
.csid_rdi_timestamp_curr0_sof_addr = 0x590, .format_measure2_addr = 0x580,
.csid_rdi_timestamp_curr1_sof_addr = 0x594, .timestamp_curr0_sof_addr = 0x590,
.csid_rdi_timestamp_prev0_sof_addr = 0x598, .timestamp_curr1_sof_addr = 0x594,
.csid_rdi_timestamp_prev1_sof_addr = 0x59c, .timestamp_prev0_sof_addr = 0x598,
.csid_rdi_timestamp_curr0_eof_addr = 0x5a0, .timestamp_prev1_sof_addr = 0x59c,
.csid_rdi_timestamp_curr1_eof_addr = 0x5a4, .timestamp_curr0_eof_addr = 0x5a0,
.csid_rdi_timestamp_prev0_eof_addr = 0x5a8, .timestamp_curr1_eof_addr = 0x5a4,
.csid_rdi_timestamp_prev1_eof_addr = 0x5ac, .timestamp_prev0_eof_addr = 0x5a8,
.csid_rdi_byte_cntr_ping_addr = 0x5e0, .timestamp_prev1_eof_addr = 0x5ac,
.csid_rdi_byte_cntr_pong_addr = 0x5e4, .byte_cntr_ping_addr = 0x5e0,
.byte_cntr_pong_addr = 0x5e4,
.halt_mode_internal = 0,
.halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.plain_fmt_shift_val = 10,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.timestamp_en_shift_val = 1,
.format_measure_en_shift_val = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x8000,
}; };
static struct cam_ife_csid_csi2_rx_reg_offset static struct cam_ife_csid_csi2_rx_reg_info
cam_ife_csid_170_csi2_reg_offset = { cam_ife_csid_170_csi2_reg_info = {
.csid_csi2_rx_irq_status_addr = 0x20, .irq_status_addr = 0x20,
.csid_csi2_rx_irq_mask_addr = 0x24, .irq_mask_addr = 0x24,
.csid_csi2_rx_irq_clear_addr = 0x28, .irq_clear_addr = 0x28,
.csid_csi2_rx_irq_set_addr = 0x2c, .irq_set_addr = 0x2c,
/*CSI2 rx control */ /*CSI2 rx control */
.csid_csi2_rx_cfg0_addr = 0x100, .cfg0_addr = 0x100,
.csid_csi2_rx_cfg1_addr = 0x104, .cfg1_addr = 0x104,
.csid_csi2_rx_capture_ctrl_addr = 0x108, .capture_ctrl_addr = 0x108,
.csid_csi2_rx_rst_strobes_addr = 0x110, .rst_strobes_addr = 0x110,
.csid_csi2_rx_de_scramble_cfg0_addr = 0x114, .de_scramble_cfg0_addr = 0x114,
.csid_csi2_rx_de_scramble_cfg1_addr = 0x118, .de_scramble_cfg1_addr = 0x118,
.csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr = 0x120, .cap_unmap_long_pkt_hdr_0_addr = 0x120,
.csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr = 0x124, .cap_unmap_long_pkt_hdr_1_addr = 0x124,
.csid_csi2_rx_captured_short_pkt_0_addr = 0x128, .captured_short_pkt_0_addr = 0x128,
.csid_csi2_rx_captured_short_pkt_1_addr = 0x12c, .captured_short_pkt_1_addr = 0x12c,
.csid_csi2_rx_captured_long_pkt_0_addr = 0x130, .captured_long_pkt_0_addr = 0x130,
.csid_csi2_rx_captured_long_pkt_1_addr = 0x134, .captured_long_pkt_1_addr = 0x134,
.csid_csi2_rx_captured_long_pkt_ftr_addr = 0x138, .captured_long_pkt_ftr_addr = 0x138,
.csid_csi2_rx_captured_cphy_pkt_hdr_addr = 0x13c, .captured_cphy_pkt_hdr_addr = 0x13c,
.csid_csi2_rx_lane0_misr_addr = 0x150, .lane0_misr_addr = 0x150,
.csid_csi2_rx_lane1_misr_addr = 0x154, .lane1_misr_addr = 0x154,
.csid_csi2_rx_lane2_misr_addr = 0x158, .lane2_misr_addr = 0x158,
.csid_csi2_rx_lane3_misr_addr = 0x15c, .lane3_misr_addr = 0x15c,
.csid_csi2_rx_total_pkts_rcvd_addr = 0x160, .total_pkts_rcvd_addr = 0x160,
.csid_csi2_rx_stats_ecc_addr = 0x164, .stats_ecc_addr = 0x164,
.csid_csi2_rx_total_crc_err_addr = 0x168, .total_crc_err_addr = 0x168,
.csi2_rst_srb_all = 0x3FFF, .rst_srb_all = 0x3FFF,
.csi2_rst_done_shift_val = 27, .rst_done_shift_val = 27,
.csi2_irq_mask_all = 0xFFFFFFF, .irq_mask_all = 0xFFFFFFF,
.csi2_misr_enable_shift_val = 6, .misr_enable_shift_val = 6,
.csi2_vc_mode_shift_val = 2, .vc_mode_shift_val = 2,
.csi2_capture_long_pkt_en_shift = 0, .capture_long_pkt_en_shift = 0,
.csi2_capture_short_pkt_en_shift = 1, .capture_short_pkt_en_shift = 1,
.csi2_capture_cphy_pkt_en_shift = 2, .capture_cphy_pkt_en_shift = 2,
.csi2_capture_long_pkt_dt_shift = 4, .capture_long_pkt_dt_shift = 4,
.csi2_capture_long_pkt_vc_shift = 10, .capture_long_pkt_vc_shift = 10,
.csi2_capture_short_pkt_vc_shift = 15, .capture_short_pkt_vc_shift = 15,
.csi2_capture_cphy_pkt_dt_shift = 20, .capture_cphy_pkt_dt_shift = 20,
.csi2_capture_cphy_pkt_vc_shift = 26, .capture_cphy_pkt_vc_shift = 26,
.csi2_rx_phy_num_mask = 0x3, .phy_num_mask = 0x3,
.vc_mask = 0x7C00000,
.dt_mask = 0x3f0000,
.wc_mask = 0xffff0000,
.calc_crc_mask = 0xffff,
.expected_crc_mask = 0xffff,
.ecc_correction_shift_en = 0,
.lane_num_shift = 0,
.lane_cfg_shift = 4,
.phy_type_shift = 24,
.phy_num_shift = 20,
.fatal_err_mask = 0x78000,
.part_fatal_err_mask = 0x1801800,
.non_fatal_err_mask = 0x380000,
}; };
static struct cam_ife_csid_csi2_tpg_reg_offset static struct cam_ife_csid_ver1_tpg_reg_info
cam_ife_csid_170_tpg_reg_offset = { cam_ife_csid_170_tpg_reg_info = {
/*CSID TPG control */ /*CSID TPG control */
.csid_tpg_ctrl_addr = 0x600, .ctrl_addr = 0x600,
.csid_tpg_vc_cfg0_addr = 0x604, .vc_cfg0_addr = 0x604,
.csid_tpg_vc_cfg1_addr = 0x608, .vc_cfg1_addr = 0x608,
.csid_tpg_lfsr_seed_addr = 0x60c, .lfsr_seed_addr = 0x60c,
.csid_tpg_dt_n_cfg_0_addr = 0x610, .dt_n_cfg_0_addr = 0x610,
.csid_tpg_dt_n_cfg_1_addr = 0x614, .dt_n_cfg_1_addr = 0x614,
.csid_tpg_dt_n_cfg_2_addr = 0x618, .dt_n_cfg_2_addr = 0x618,
.csid_tpg_color_bars_cfg_addr = 0x640, .color_bars_cfg_addr = 0x640,
.csid_tpg_color_box_cfg_addr = 0x644, .color_box_cfg_addr = 0x644,
.csid_tpg_common_gen_cfg_addr = 0x648, .common_gen_cfg_addr = 0x648,
.csid_tpg_cgen_n_cfg_addr = 0x650, .cgen_n_cfg_addr = 0x650,
.csid_tpg_cgen_n_x0_addr = 0x654, .cgen_n_x0_addr = 0x654,
.csid_tpg_cgen_n_x1_addr = 0x658, .cgen_n_x1_addr = 0x658,
.csid_tpg_cgen_n_x2_addr = 0x65c, .cgen_n_x2_addr = 0x65c,
.csid_tpg_cgen_n_xy_addr = 0x660, .cgen_n_xy_addr = 0x660,
.csid_tpg_cgen_n_y1_addr = 0x664, .cgen_n_y1_addr = 0x664,
.csid_tpg_cgen_n_y2_addr = 0x668, .cgen_n_y2_addr = 0x668,
/* configurations */ /* configurations */
.tpg_dtn_cfg_offset = 0xc, .dtn_cfg_offset = 0xc,
.tpg_cgen_cfg_offset = 0x20, .cgen_cfg_offset = 0x20,
.tpg_cpas_ife_reg_offset = 0x28, .cpas_ife_reg_offset = 0x28,
.hbi = 0x740,
.vbi = 0x3FF,
.lfsr_seed = 0x12345678,
.ctrl_cfg = 0x408007,
.line_interleave_mode = 0x1,
.color_bar = 1,
.num_frames = 0,
.num_active_dt = 0,
.payload_mode = 0x8,
.num_active_lanes_mask = 0x30,
.fmt_shift = 16,
.num_frame_shift = 16,
.width_shift = 16,
.vbi_shift = 12,
.line_interleave_shift = 10,
.num_active_dt_shift = 8,
.color_bar_shift = 5,
.height_shift = 0,
.hbi_shift = 0,
}; };
static struct cam_ife_csid_common_reg_offset static struct cam_ife_csid_ver1_common_reg_info
cam_ife_csid_170_cmn_reg_offset = { cam_ife_csid_170_cmn_reg_info = {
.csid_hw_version_addr = 0x0, .hw_version_addr = 0x0,
.csid_cfg0_addr = 0x4, .cfg0_addr = 0x4,
.csid_ctrl_addr = 0x8, .ctrl_addr = 0x8,
.csid_reset_addr = 0xc, .reset_addr = 0xc,
.csid_rst_strobes_addr = 0x10, .rst_strobes_addr = 0x10,
.csid_test_bus_ctrl_addr = 0x14, .test_bus_ctrl_addr = 0x14,
.csid_top_irq_status_addr = 0x70, .top_irq_status_addr = 0x70,
.csid_top_irq_mask_addr = 0x74, .top_irq_mask_addr = 0x74,
.csid_top_irq_clear_addr = 0x78, .top_irq_clear_addr = 0x78,
.csid_top_irq_set_addr = 0x7c, .top_irq_set_addr = 0x7c,
.csid_irq_cmd_addr = 0x80, .irq_cmd_addr = 0x80,
/*configurations */ /*configurations */
.major_version = 1, .major_version = 1,
.minor_version = 7, .minor_version = 7,
.version_incr = 0, .version_incr = 0,
.num_rdis = 3, .num_rdis = 3,
.num_pix = 1, .num_pix = 1,
.num_ppp = 0, .num_ppp = 0,
.csid_reg_rst_stb = 1, .rst_sw_reg_stb = 1,
.csid_rst_stb = 0x1e, .rst_hw_reg_stb = 0x1e,
.csid_rst_stb_sw_all = 0x1f, .rst_sw_hw_reg_stb = 0x1f,
.path_rst_stb_all = 0x7f, .path_rst_stb_all = 0x7f,
.path_rst_done_shift_val = 1, .rst_done_shift_val = 1,
.path_en_shift_val = 31, .path_en_shift_val = 31,
.dt_id_shift_val = 27, .dt_id_shift_val = 27,
.vc_shift_val = 22, .vc_shift_val = 22,
.dt_shift_val = 16, .dt_shift_val = 16,
.fmt_shift_val = 12, .fmt_shift_val = 12,
.plain_fmt_shit_val = 10, .crop_shift_val = 16,
.crop_v_en_shift_val = 6, .decode_format_shift_val = 12,
.crop_h_en_shift_val = 5, .crop_pix_start_mask = 0x3fff,
.crop_shift = 16, .crop_pix_end_mask = 0xffff,
.ipp_irq_mask_all = 0x7FFF, .crop_line_start_mask = 0x3fff,
.rdi_irq_mask_all = 0x7FFF, .crop_line_end_mask = 0xffff,
.ppp_irq_mask_all = 0x0, .ipp_irq_mask_all = 0x7FFF,
.measure_en_hbi_vbi_cnt_mask = 0xC, .rdi_irq_mask_all = 0x7FFF,
.format_measure_en_val = 1, .ppp_irq_mask_all = 0x0,
.format_measure_height_mask_val = 0xFFFF, .measure_en_hbi_vbi_cnt_mask = 0xC,
.format_measure_height_shift_val = 0x10, .timestamp_strobe_val = 0x2,
.format_measure_width_mask_val = 0xFFFF, .timestamp_stb_sel_shift_val = 0,
.format_measure_width_shift_val = 0x0,
}; };
static struct cam_ife_csid_reg_offset cam_ife_csid_170_reg_offset = { static struct cam_ife_csid_ver1_reg_info cam_ife_csid_170_reg_info = {
.cmn_reg = &cam_ife_csid_170_cmn_reg_offset, .cmn_reg = &cam_ife_csid_170_cmn_reg_info,
.csi2_reg = &cam_ife_csid_170_csi2_reg_offset, .csi2_reg = &cam_ife_csid_170_csi2_reg_info,
.ipp_reg = &cam_ife_csid_170_ipp_reg_offset, .ipp_reg = &cam_ife_csid_170_ipp_reg_info,
.ppp_reg = NULL, .ppp_reg = NULL,
.rdi_reg = { .rdi_reg = {
&cam_ife_csid_170_rdi_0_reg_offset, &cam_ife_csid_170_rdi_0_reg_info,
&cam_ife_csid_170_rdi_1_reg_offset, &cam_ife_csid_170_rdi_1_reg_info,
&cam_ife_csid_170_rdi_2_reg_offset, &cam_ife_csid_170_rdi_2_reg_info,
NULL, NULL,
}, },
.tpg_reg = &cam_ife_csid_170_tpg_reg_offset, .tpg_reg = &cam_ife_csid_170_tpg_reg_info,
}; };
#endif /*_CAM_IFE_CSID_170_H_ */ #endif /*_CAM_IFE_CSID_170_H_ */

777
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid170_200.h
View File

@@ -6,367 +6,480 @@
#ifndef _CAM_IFE_CSID_170_200_H_ #ifndef _CAM_IFE_CSID_170_200_H_
#define _CAM_IFE_CSID_170_200_H_ #define _CAM_IFE_CSID_170_200_H_
#include "cam_ife_csid_core.h" #include <linux/module.h>
#include "camera_main.h"
#include "cam_ife_csid_dev.h"
#include "cam_ife_csid_common.h"
#include "cam_ife_csid_hw_ver1.h"
static struct cam_ife_csid_pxl_reg_offset #define CAM_CSID_VERSION_V170 0x10070000
cam_ife_csid_170_200_ipp_reg_offset = {
.csid_pxl_irq_status_addr = 0x30,
.csid_pxl_irq_mask_addr = 0x34,
.csid_pxl_irq_clear_addr = 0x38,
.csid_pxl_irq_set_addr = 0x3c,
.csid_pxl_cfg0_addr = 0x200, static struct cam_ife_csid_ver1_path_reg_info
.csid_pxl_cfg1_addr = 0x204, cam_ife_csid_170_200_ipp_reg_info = {
.csid_pxl_ctrl_addr = 0x208, .irq_status_addr = 0x30,
.csid_pxl_frm_drop_pattern_addr = 0x20c, .irq_mask_addr = 0x34,
.csid_pxl_frm_drop_period_addr = 0x210, .irq_clear_addr = 0x38,
.csid_pxl_irq_subsample_pattern_addr = 0x214, .irq_set_addr = 0x3c,
.csid_pxl_irq_subsample_period_addr = 0x218, .cfg0_addr = 0x200,
.csid_pxl_hcrop_addr = 0x21c, .cfg1_addr = 0x204,
.csid_pxl_vcrop_addr = 0x220, .ctrl_addr = 0x208,
.csid_pxl_pix_drop_pattern_addr = 0x224, .frm_drop_pattern_addr = 0x20c,
.csid_pxl_pix_drop_period_addr = 0x228, .frm_drop_period_addr = 0x210,
.csid_pxl_line_drop_pattern_addr = 0x22c, .irq_subsample_pattern_addr = 0x214,
.csid_pxl_line_drop_period_addr = 0x230, .irq_subsample_period_addr = 0x218,
.csid_pxl_rst_strobes_addr = 0x240, .hcrop_addr = 0x21c,
.csid_pxl_status_addr = 0x254, .vcrop_addr = 0x220,
.csid_pxl_misr_val_addr = 0x258, .pix_drop_pattern_addr = 0x224,
.csid_pxl_format_measure_cfg0_addr = 0x270, .pix_drop_period_addr = 0x228,
.csid_pxl_format_measure_cfg1_addr = 0x274, .line_drop_pattern_addr = 0x22c,
.csid_pxl_format_measure0_addr = 0x278, .line_drop_period_addr = 0x230,
.csid_pxl_format_measure1_addr = 0x27c, .rst_strobes_addr = 0x240,
.csid_pxl_format_measure2_addr = 0x280, .status_addr = 0x254,
.csid_pxl_timestamp_curr0_sof_addr = 0x290, .misr_val_addr = 0x258,
.csid_pxl_timestamp_curr1_sof_addr = 0x294, .format_measure_cfg0_addr = 0x270,
.csid_pxl_timestamp_perv0_sof_addr = 0x298, .format_measure_cfg1_addr = 0x274,
.csid_pxl_timestamp_perv1_sof_addr = 0x29c, .format_measure0_addr = 0x278,
.csid_pxl_timestamp_curr0_eof_addr = 0x2a0, .format_measure1_addr = 0x27c,
.csid_pxl_timestamp_curr1_eof_addr = 0x2a4, .format_measure2_addr = 0x280,
.csid_pxl_timestamp_perv0_eof_addr = 0x2a8, .timestamp_curr0_sof_addr = 0x290,
.csid_pxl_timestamp_perv1_eof_addr = 0x2ac, .timestamp_curr1_sof_addr = 0x294,
.timestamp_prev0_sof_addr = 0x298,
.timestamp_prev1_sof_addr = 0x29c,
.timestamp_curr0_eof_addr = 0x2a0,
.timestamp_curr1_eof_addr = 0x2a4,
.timestamp_prev0_eof_addr = 0x2a8,
.timestamp_prev1_eof_addr = 0x2ac,
/* configurations */ /* configurations */
.pix_store_en_shift_val = 7, .pix_store_en_shift_val = 7,
.early_eof_en_shift_val = 29, .early_eof_en_shift_val = 29,
.quad_cfa_bin_en_shift_val = 30, .bin_qcfa_en_shift_val = 30,
.ccif_violation_en = 1, .bin_h_en_shift_val = 2,
.halt_master_sel_en = 1, .bin_en_shift_val = 2,
.halt_sel_internal_master_val = 3, .binning_supported = 0x3,
.halt_master_sel_master_val = 0,
.halt_master_sel_shift = 4,
.halt_mode_internal = 0,
.halt_mode_global = 1,
.halt_mode_master = 2,
.halt_mode_slave = 3,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.drop_v_en_shift_val = 4,
.drop_h_en_shift_val = 3,
.timestamp_en_shift_val = 2,
.format_measure_en_shift_val = 0,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x8000,
}; };
static struct cam_ife_csid_pxl_reg_offset static struct cam_ife_csid_ver1_path_reg_info
cam_ife_csid_170_200_ppp_reg_offset = { cam_ife_csid_170_200_ppp_reg_info = {
.csid_pxl_irq_status_addr = 0xa0, .irq_status_addr = 0xa0,
.csid_pxl_irq_mask_addr = 0xa4, .irq_mask_addr = 0xa4,
.csid_pxl_irq_clear_addr = 0xa8, .irq_clear_addr = 0xa8,
.csid_pxl_irq_set_addr = 0xac, .irq_set_addr = 0xac,
.cfg0_addr = 0x700,
.csid_pxl_cfg0_addr = 0x700, .cfg1_addr = 0x704,
.csid_pxl_cfg1_addr = 0x704, .ctrl_addr = 0x708,
.csid_pxl_ctrl_addr = 0x708, .frm_drop_pattern_addr = 0x70c,
.csid_pxl_frm_drop_pattern_addr = 0x70c, .frm_drop_period_addr = 0x710,
.csid_pxl_frm_drop_period_addr = 0x710, .irq_subsample_pattern_addr = 0x714,
.csid_pxl_irq_subsample_pattern_addr = 0x714, .irq_subsample_period_addr = 0x718,
.csid_pxl_irq_subsample_period_addr = 0x718, .hcrop_addr = 0x71c,
.csid_pxl_hcrop_addr = 0x71c, .vcrop_addr = 0x720,
.csid_pxl_vcrop_addr = 0x720, .pix_drop_pattern_addr = 0x724,
.csid_pxl_pix_drop_pattern_addr = 0x724, .pix_drop_period_addr = 0x728,
.csid_pxl_pix_drop_period_addr = 0x728, .line_drop_pattern_addr = 0x72c,
.csid_pxl_line_drop_pattern_addr = 0x72c, .line_drop_period_addr = 0x730,
.csid_pxl_line_drop_period_addr = 0x730, .rst_strobes_addr = 0x740,
.csid_pxl_rst_strobes_addr = 0x740, .status_addr = 0x754,
.csid_pxl_status_addr = 0x754, .misr_val_addr = 0x758,
.csid_pxl_misr_val_addr = 0x758, .format_measure_cfg0_addr = 0x770,
.csid_pxl_format_measure_cfg0_addr = 0x770, .format_measure_cfg1_addr = 0x774,
.csid_pxl_format_measure_cfg1_addr = 0x774, .format_measure0_addr = 0x778,
.csid_pxl_format_measure0_addr = 0x778, .format_measure1_addr = 0x77c,
.csid_pxl_format_measure1_addr = 0x77c, .format_measure2_addr = 0x780,
.csid_pxl_format_measure2_addr = 0x780, .timestamp_curr0_sof_addr = 0x790,
.csid_pxl_timestamp_curr0_sof_addr = 0x790, .timestamp_curr1_sof_addr = 0x794,
.csid_pxl_timestamp_curr1_sof_addr = 0x794, .timestamp_prev0_sof_addr = 0x798,
.csid_pxl_timestamp_perv0_sof_addr = 0x798, .timestamp_prev1_sof_addr = 0x79c,
.csid_pxl_timestamp_perv1_sof_addr = 0x79c, .timestamp_curr0_eof_addr = 0x7a0,
.csid_pxl_timestamp_curr0_eof_addr = 0x7a0, .timestamp_curr1_eof_addr = 0x7a4,
.csid_pxl_timestamp_curr1_eof_addr = 0x7a4, .timestamp_prev0_eof_addr = 0x7a8,
.csid_pxl_timestamp_perv0_eof_addr = 0x7a8, .timestamp_prev1_eof_addr = 0x7ac,
.csid_pxl_timestamp_perv1_eof_addr = 0x7ac,
/* configurations */ /* configurations */
.pix_store_en_shift_val = 7, .halt_master_sel_master_val = 3,
.early_eof_en_shift_val = 29, .halt_master_sel_shift = 4,
.ccif_violation_en = 1, .halt_mode_internal = 0,
.halt_master_sel_en = 1, .halt_mode_global = 1,
.halt_sel_internal_master_val = 3, .halt_mode_master = 2,
.halt_mode_slave = 3,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.pix_store_en_shift_val = 7,
.early_eof_en_shift_val = 29,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.drop_v_en_shift_val = 4,
.drop_h_en_shift_val = 3,
.timestamp_en_shift_val = 2,
.format_measure_en_shift_val = 0,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x8000,
}; };
static struct cam_ife_csid_ver1_path_reg_info
static struct cam_ife_csid_rdi_reg_offset cam_ife_csid_170_200_rdi_0_reg_info = {
cam_ife_csid_170_200_rdi_0_reg_offset = { .irq_status_addr = 0x40,
.csid_rdi_irq_status_addr = 0x40, .irq_mask_addr = 0x44,
.csid_rdi_irq_mask_addr = 0x44, .irq_clear_addr = 0x48,
.csid_rdi_irq_clear_addr = 0x48, .irq_set_addr = 0x4c,
.csid_rdi_irq_set_addr = 0x4c, .cfg0_addr = 0x300,
.csid_rdi_cfg0_addr = 0x300, .cfg1_addr = 0x304,
.csid_rdi_cfg1_addr = 0x304, .ctrl_addr = 0x308,
.csid_rdi_ctrl_addr = 0x308, .frm_drop_pattern_addr = 0x30c,
.csid_rdi_frm_drop_pattern_addr = 0x30c, .frm_drop_period_addr = 0x310,
.csid_rdi_frm_drop_period_addr = 0x310, .irq_subsample_pattern_addr = 0x314,
.csid_rdi_irq_subsample_pattern_addr = 0x314, .irq_subsample_period_addr = 0x318,
.csid_rdi_irq_subsample_period_addr = 0x318, .hcrop_addr = 0x31c,
.csid_rdi_rpp_hcrop_addr = 0x31c, .vcrop_addr = 0x320,
.csid_rdi_rpp_vcrop_addr = 0x320, .pix_drop_pattern_addr = 0x324,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x324, .pix_drop_period_addr = 0x328,
.csid_rdi_rpp_pix_drop_period_addr = 0x328, .line_drop_pattern_addr = 0x32c,
.csid_rdi_rpp_line_drop_pattern_addr = 0x32c, .line_drop_period_addr = 0x330,
.csid_rdi_rpp_line_drop_period_addr = 0x330, .rst_strobes_addr = 0x340,
.csid_rdi_rst_strobes_addr = 0x340, .status_addr = 0x350,
.csid_rdi_status_addr = 0x350, .misr_val0_addr = 0x354,
.csid_rdi_misr_val0_addr = 0x354, .misr_val1_addr = 0x358,
.csid_rdi_misr_val1_addr = 0x358, .misr_val2_addr = 0x35c,
.csid_rdi_misr_val2_addr = 0x35c, .misr_val3_addr = 0x360,
.csid_rdi_misr_val3_addr = 0x360, .format_measure_cfg0_addr = 0x370,
.csid_rdi_format_measure_cfg0_addr = 0x370, .format_measure_cfg1_addr = 0x374,
.csid_rdi_format_measure_cfg1_addr = 0x374, .format_measure0_addr = 0x378,
.csid_rdi_format_measure0_addr = 0x378, .format_measure1_addr = 0x37c,
.csid_rdi_format_measure1_addr = 0x37c, .format_measure2_addr = 0x380,
.csid_rdi_format_measure2_addr = 0x380, .timestamp_curr0_sof_addr = 0x390,
.csid_rdi_timestamp_curr0_sof_addr = 0x390, .timestamp_curr1_sof_addr = 0x394,
.csid_rdi_timestamp_curr1_sof_addr = 0x394, .timestamp_prev0_sof_addr = 0x398,
.csid_rdi_timestamp_prev0_sof_addr = 0x398, .timestamp_prev1_sof_addr = 0x39c,
.csid_rdi_timestamp_prev1_sof_addr = 0x39c, .timestamp_curr0_eof_addr = 0x3a0,
.csid_rdi_timestamp_curr0_eof_addr = 0x3a0, .timestamp_curr1_eof_addr = 0x3a4,
.csid_rdi_timestamp_curr1_eof_addr = 0x3a4, .timestamp_prev0_eof_addr = 0x3a8,
.csid_rdi_timestamp_prev0_eof_addr = 0x3a8, .timestamp_prev1_eof_addr = 0x3ac,
.csid_rdi_timestamp_prev1_eof_addr = 0x3ac, .byte_cntr_ping_addr = 0x3e0,
.csid_rdi_byte_cntr_ping_addr = 0x3e0, .byte_cntr_pong_addr = 0x3e4,
.csid_rdi_byte_cntr_pong_addr = 0x3e4, .halt_mode_internal = 0,
.ccif_violation_en = 1, .halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.ccif_violation_en = 1,
.plain_fmt_shift_val = 10,
.mipi_pack_supported = 1,
.packing_fmt_shift_val = 30,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.timestamp_en_shift_val = 1,
.format_measure_en_shift_val = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x8000,
}; };
static struct cam_ife_csid_rdi_reg_offset static struct cam_ife_csid_ver1_path_reg_info
cam_ife_csid_170_200_rdi_1_reg_offset = { cam_ife_csid_170_200_rdi_1_reg_info = {
.csid_rdi_irq_status_addr = 0x50, .irq_status_addr = 0x50,
.csid_rdi_irq_mask_addr = 0x54, .irq_mask_addr = 0x54,
.csid_rdi_irq_clear_addr = 0x58, .irq_clear_addr = 0x58,
.csid_rdi_irq_set_addr = 0x5c, .irq_set_addr = 0x5c,
.csid_rdi_cfg0_addr = 0x400, .cfg0_addr = 0x400,
.csid_rdi_cfg1_addr = 0x404, .cfg1_addr = 0x404,
.csid_rdi_ctrl_addr = 0x408, .ctrl_addr = 0x408,
.csid_rdi_frm_drop_pattern_addr = 0x40c, .frm_drop_pattern_addr = 0x40c,
.csid_rdi_frm_drop_period_addr = 0x410, .frm_drop_period_addr = 0x410,
.csid_rdi_irq_subsample_pattern_addr = 0x414, .irq_subsample_pattern_addr = 0x414,
.csid_rdi_irq_subsample_period_addr = 0x418, .irq_subsample_period_addr = 0x418,
.csid_rdi_rpp_hcrop_addr = 0x41c, .hcrop_addr = 0x41c,
.csid_rdi_rpp_vcrop_addr = 0x420, .vcrop_addr = 0x420,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x424, .pix_drop_pattern_addr = 0x424,
.csid_rdi_rpp_pix_drop_period_addr = 0x428, .pix_drop_period_addr = 0x428,
.csid_rdi_rpp_line_drop_pattern_addr = 0x42c, .line_drop_pattern_addr = 0x42c,
.csid_rdi_rpp_line_drop_period_addr = 0x430, .line_drop_period_addr = 0x430,
.csid_rdi_rst_strobes_addr = 0x440, .rst_strobes_addr = 0x440,
.csid_rdi_status_addr = 0x450, .status_addr = 0x450,
.csid_rdi_misr_val0_addr = 0x454, .misr_val0_addr = 0x454,
.csid_rdi_misr_val1_addr = 0x458, .misr_val1_addr = 0x458,
.csid_rdi_misr_val2_addr = 0x45c, .misr_val2_addr = 0x45c,
.csid_rdi_misr_val3_addr = 0x460, .misr_val3_addr = 0x460,
.csid_rdi_format_measure_cfg0_addr = 0x470, .format_measure_cfg0_addr = 0x470,
.csid_rdi_format_measure_cfg1_addr = 0x474, .format_measure_cfg1_addr = 0x474,
.csid_rdi_format_measure0_addr = 0x478, .format_measure0_addr = 0x478,
.csid_rdi_format_measure1_addr = 0x47c, .format_measure1_addr = 0x47c,
.csid_rdi_format_measure2_addr = 0x480, .format_measure2_addr = 0x480,
.csid_rdi_timestamp_curr0_sof_addr = 0x490, .timestamp_curr0_sof_addr = 0x490,
.csid_rdi_timestamp_curr1_sof_addr = 0x494, .timestamp_curr1_sof_addr = 0x494,
.csid_rdi_timestamp_prev0_sof_addr = 0x498, .timestamp_prev0_sof_addr = 0x498,
.csid_rdi_timestamp_prev1_sof_addr = 0x49c, .timestamp_prev1_sof_addr = 0x49c,
.csid_rdi_timestamp_curr0_eof_addr = 0x4a0, .timestamp_curr0_eof_addr = 0x4a0,
.csid_rdi_timestamp_curr1_eof_addr = 0x4a4, .timestamp_curr1_eof_addr = 0x4a4,
.csid_rdi_timestamp_prev0_eof_addr = 0x4a8, .timestamp_prev0_eof_addr = 0x4a8,
.csid_rdi_timestamp_prev1_eof_addr = 0x4ac, .timestamp_prev1_eof_addr = 0x4ac,
.csid_rdi_byte_cntr_ping_addr = 0x4e0, .byte_cntr_ping_addr = 0x4e0,
.csid_rdi_byte_cntr_pong_addr = 0x4e4, .byte_cntr_pong_addr = 0x4e4,
.ccif_violation_en = 1, .halt_mode_internal = 0,
.halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.ccif_violation_en = 1,
.plain_fmt_shift_val = 10,
.packing_fmt_shift_val = 30,
.mipi_pack_supported = 1,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.timestamp_en_shift_val = 1,
.format_measure_en_shift_val = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x8000,
}; };
static struct cam_ife_csid_rdi_reg_offset static struct cam_ife_csid_ver1_path_reg_info
cam_ife_csid_170_200_rdi_2_reg_offset = { cam_ife_csid_170_200_rdi_2_reg_info = {
.csid_rdi_irq_status_addr = 0x60, .irq_status_addr = 0x60,
.csid_rdi_irq_mask_addr = 0x64, .irq_mask_addr = 0x64,
.csid_rdi_irq_clear_addr = 0x68, .irq_clear_addr = 0x68,
.csid_rdi_irq_set_addr = 0x6c, .irq_set_addr = 0x6c,
.csid_rdi_cfg0_addr = 0x500, .cfg0_addr = 0x500,
.csid_rdi_cfg1_addr = 0x504, .cfg1_addr = 0x504,
.csid_rdi_ctrl_addr = 0x508, .ctrl_addr = 0x508,
.csid_rdi_frm_drop_pattern_addr = 0x50c, .frm_drop_pattern_addr = 0x50c,
.csid_rdi_frm_drop_period_addr = 0x510, .frm_drop_period_addr = 0x510,
.csid_rdi_irq_subsample_pattern_addr = 0x514, .irq_subsample_pattern_addr = 0x514,
.csid_rdi_irq_subsample_period_addr = 0x518, .irq_subsample_period_addr = 0x518,
.csid_rdi_rpp_hcrop_addr = 0x51c, .hcrop_addr = 0x51c,
.csid_rdi_rpp_vcrop_addr = 0x520, .vcrop_addr = 0x520,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x524, .pix_drop_pattern_addr = 0x524,
.csid_rdi_rpp_pix_drop_period_addr = 0x528, .pix_drop_period_addr = 0x528,
.csid_rdi_rpp_line_drop_pattern_addr = 0x52c, .line_drop_pattern_addr = 0x52c,
.csid_rdi_rpp_line_drop_period_addr = 0x530, .line_drop_period_addr = 0x530,
.csid_rdi_yuv_chroma_conversion_addr = 0x534, .yuv_chroma_conversion_addr = 0x534,
.csid_rdi_rst_strobes_addr = 0x540, .rst_strobes_addr = 0x540,
.csid_rdi_status_addr = 0x550, .status_addr = 0x550,
.csid_rdi_misr_val0_addr = 0x554, .misr_val0_addr = 0x554,
.csid_rdi_misr_val1_addr = 0x558, .misr_val1_addr = 0x558,
.csid_rdi_misr_val2_addr = 0x55c, .misr_val2_addr = 0x55c,
.csid_rdi_misr_val3_addr = 0x560, .misr_val3_addr = 0x560,
.csid_rdi_format_measure_cfg0_addr = 0x570, .format_measure_cfg0_addr = 0x570,
.csid_rdi_format_measure_cfg1_addr = 0x574, .format_measure_cfg1_addr = 0x574,
.csid_rdi_format_measure0_addr = 0x578, .format_measure0_addr = 0x578,
.csid_rdi_format_measure1_addr = 0x57c, .format_measure1_addr = 0x57c,
.csid_rdi_format_measure2_addr = 0x580, .format_measure2_addr = 0x580,
.csid_rdi_timestamp_curr0_sof_addr = 0x590, .timestamp_curr0_sof_addr = 0x590,
.csid_rdi_timestamp_curr1_sof_addr = 0x594, .timestamp_curr1_sof_addr = 0x594,
.csid_rdi_timestamp_prev0_sof_addr = 0x598, .timestamp_prev0_sof_addr = 0x598,
.csid_rdi_timestamp_prev1_sof_addr = 0x59c, .timestamp_prev1_sof_addr = 0x59c,
.csid_rdi_timestamp_curr0_eof_addr = 0x5a0, .timestamp_curr0_eof_addr = 0x5a0,
.csid_rdi_timestamp_curr1_eof_addr = 0x5a4, .timestamp_curr1_eof_addr = 0x5a4,
.csid_rdi_timestamp_prev0_eof_addr = 0x5a8, .timestamp_prev0_eof_addr = 0x5a8,
.csid_rdi_timestamp_prev1_eof_addr = 0x5ac, .timestamp_prev1_eof_addr = 0x5ac,
.csid_rdi_byte_cntr_ping_addr = 0x5e0, .byte_cntr_ping_addr = 0x5e0,
.csid_rdi_byte_cntr_pong_addr = 0x5e4, .byte_cntr_pong_addr = 0x5e4,
.ccif_violation_en = 1, .halt_mode_internal = 0,
.halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.ccif_violation_en = 1,
.plain_fmt_shift_val = 10,
.packing_fmt_shift_val = 30,
.mipi_pack_supported = 1,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.timestamp_en_shift_val = 1,
.format_measure_en_shift_val = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x8000,
}; };
static struct cam_ife_csid_csi2_rx_reg_offset static struct cam_ife_csid_csi2_rx_reg_info
cam_ife_csid_170_200_csi2_reg_offset = { cam_ife_csid_170_200_csi2_reg_info = {
.csid_csi2_rx_irq_status_addr = 0x20, .irq_status_addr = 0x20,
.csid_csi2_rx_irq_mask_addr = 0x24, .irq_mask_addr = 0x24,
.csid_csi2_rx_irq_clear_addr = 0x28, .irq_clear_addr = 0x28,
.csid_csi2_rx_irq_set_addr = 0x2c, .irq_set_addr = 0x2c,
/*CSI2 rx control */ /*CSI2 rx control */
.csid_csi2_rx_cfg0_addr = 0x100, .cfg0_addr = 0x100,
.csid_csi2_rx_cfg1_addr = 0x104, .cfg1_addr = 0x104,
.csid_csi2_rx_capture_ctrl_addr = 0x108, .capture_ctrl_addr = 0x108,
.csid_csi2_rx_rst_strobes_addr = 0x110, .rst_strobes_addr = 0x110,
.csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr = 0x120, .cap_unmap_long_pkt_hdr_0_addr = 0x120,
.csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr = 0x124, .cap_unmap_long_pkt_hdr_1_addr = 0x124,
.csid_csi2_rx_captured_short_pkt_0_addr = 0x128, .captured_short_pkt_0_addr = 0x128,
.csid_csi2_rx_captured_short_pkt_1_addr = 0x12c, .captured_short_pkt_1_addr = 0x12c,
.csid_csi2_rx_captured_long_pkt_0_addr = 0x130, .captured_long_pkt_0_addr = 0x130,
.csid_csi2_rx_captured_long_pkt_1_addr = 0x134, .captured_long_pkt_1_addr = 0x134,
.csid_csi2_rx_captured_long_pkt_ftr_addr = 0x138, .captured_long_pkt_ftr_addr = 0x138,
.csid_csi2_rx_captured_cphy_pkt_hdr_addr = 0x13c, .captured_cphy_pkt_hdr_addr = 0x13c,
.csid_csi2_rx_lane0_misr_addr = 0x150, .lane0_misr_addr = 0x150,
.csid_csi2_rx_lane1_misr_addr = 0x154, .lane1_misr_addr = 0x154,
.csid_csi2_rx_lane2_misr_addr = 0x158, .lane2_misr_addr = 0x158,
.csid_csi2_rx_lane3_misr_addr = 0x15c, .lane3_misr_addr = 0x15c,
.csid_csi2_rx_total_pkts_rcvd_addr = 0x160, .total_pkts_rcvd_addr = 0x160,
.csid_csi2_rx_stats_ecc_addr = 0x164, .stats_ecc_addr = 0x164,
.csid_csi2_rx_total_crc_err_addr = 0x168, .total_crc_err_addr = 0x168,
.csid_csi2_rx_de_scramble_type3_cfg0_addr = 0x170, .de_scramble_type3_cfg0_addr = 0x170,
.csid_csi2_rx_de_scramble_type3_cfg1_addr = 0x174, .de_scramble_type3_cfg1_addr = 0x174,
.csid_csi2_rx_de_scramble_type2_cfg0_addr = 0x178, .de_scramble_type2_cfg0_addr = 0x178,
.csid_csi2_rx_de_scramble_type2_cfg1_addr = 0x17c, .de_scramble_type2_cfg1_addr = 0x17c,
.csid_csi2_rx_de_scramble_type1_cfg0_addr = 0x180, .de_scramble_type1_cfg0_addr = 0x180,
.csid_csi2_rx_de_scramble_type1_cfg1_addr = 0x184, .de_scramble_type1_cfg1_addr = 0x184,
.csid_csi2_rx_de_scramble_type0_cfg0_addr = 0x188, .de_scramble_type0_cfg0_addr = 0x188,
.csid_csi2_rx_de_scramble_type0_cfg1_addr = 0x18c, .de_scramble_type0_cfg1_addr = 0x18c,
.csi2_rst_srb_all = 0x3FFF, .rst_srb_all = 0x3FFF,
.csi2_rst_done_shift_val = 27, .rst_done_shift_val = 27,
.csi2_irq_mask_all = 0xFFFFFFF, .irq_mask_all = 0xFFFFFFF,
.csi2_misr_enable_shift_val = 6, .misr_enable_shift_val = 6,
.csi2_vc_mode_shift_val = 2, .vc_mode_shift_val = 2,
.csi2_capture_long_pkt_en_shift = 0, .capture_long_pkt_en_shift = 0,
.csi2_capture_short_pkt_en_shift = 1, .capture_short_pkt_en_shift = 1,
.csi2_capture_cphy_pkt_en_shift = 2, .capture_cphy_pkt_en_shift = 2,
.csi2_capture_long_pkt_dt_shift = 4, .capture_long_pkt_dt_shift = 4,
.csi2_capture_long_pkt_vc_shift = 10, .capture_long_pkt_vc_shift = 10,
.csi2_capture_short_pkt_vc_shift = 15, .capture_short_pkt_vc_shift = 15,
.csi2_capture_cphy_pkt_dt_shift = 20, .capture_cphy_pkt_dt_shift = 20,
.csi2_capture_cphy_pkt_vc_shift = 26, .capture_cphy_pkt_vc_shift = 26,
.csi2_rx_phy_num_mask = 0x7, .phy_num_mask = 0x7,
.vc_mask = 0x7C00000,
.dt_mask = 0x3f0000,
.wc_mask = 0xffff0000,
.calc_crc_mask = 0xffff,
.expected_crc_mask = 0xffff,
.ecc_correction_shift_en = 0,
.lane_num_shift = 0,
.lane_cfg_shift = 4,
.phy_type_shift = 24,
.phy_num_shift = 20,
.fatal_err_mask = 0x78000,
.part_fatal_err_mask = 0x1801800,
.non_fatal_err_mask = 0x380000,
}; };
static struct cam_ife_csid_csi2_tpg_reg_offset static struct cam_ife_csid_ver1_tpg_reg_info
cam_ife_csid_170_200_tpg_reg_offset = { cam_ife_csid_170_200_tpg_reg_info = {
/*CSID TPG control */ /*CSID TPG control */
.csid_tpg_ctrl_addr = 0x600, .ctrl_addr = 0x600,
.csid_tpg_vc_cfg0_addr = 0x604, .vc_cfg0_addr = 0x604,
.csid_tpg_vc_cfg1_addr = 0x608, .vc_cfg1_addr = 0x608,
.csid_tpg_lfsr_seed_addr = 0x60c, .lfsr_seed_addr = 0x60c,
.csid_tpg_dt_n_cfg_0_addr = 0x610, .dt_n_cfg_0_addr = 0x610,
.csid_tpg_dt_n_cfg_1_addr = 0x614, .dt_n_cfg_1_addr = 0x614,
.csid_tpg_dt_n_cfg_2_addr = 0x618, .dt_n_cfg_2_addr = 0x618,
.csid_tpg_color_bars_cfg_addr = 0x640, .color_bars_cfg_addr = 0x640,
.csid_tpg_color_box_cfg_addr = 0x644, .color_box_cfg_addr = 0x644,
.csid_tpg_common_gen_cfg_addr = 0x648, .common_gen_cfg_addr = 0x648,
.csid_tpg_cgen_n_cfg_addr = 0x650, .cgen_n_cfg_addr = 0x650,
.csid_tpg_cgen_n_x0_addr = 0x654, .cgen_n_x0_addr = 0x654,
.csid_tpg_cgen_n_x1_addr = 0x658, .cgen_n_x1_addr = 0x658,
.csid_tpg_cgen_n_x2_addr = 0x65c, .cgen_n_x2_addr = 0x65c,
.csid_tpg_cgen_n_xy_addr = 0x660, .cgen_n_xy_addr = 0x660,
.csid_tpg_cgen_n_y1_addr = 0x664, .cgen_n_y1_addr = 0x664,
.csid_tpg_cgen_n_y2_addr = 0x668, .cgen_n_y2_addr = 0x668,
/* configurations */ /* configurations */
.tpg_dtn_cfg_offset = 0xc, .dtn_cfg_offset = 0xc,
.tpg_cgen_cfg_offset = 0x20, .cgen_cfg_offset = 0x20,
.tpg_cpas_ife_reg_offset = 0x28, .cpas_ife_reg_offset = 0x28,
.hbi = 0x740,
.vbi = 0x3FF,
.lfsr_seed = 0x12345678,
.ctrl_cfg = 0x408007,
.color_bar = 1,
.line_interleave_mode = 0x1,
.num_frames = 0,
.num_active_lanes_mask = 0x30,
.num_active_dt = 0,
.payload_mode = 0x8,
.fmt_shift = 16,
.num_frame_shift = 16,
.width_shift = 16,
.vbi_shift = 12,
.line_interleave_shift = 10,
.num_active_dt_shift = 8,
.color_bar_shift = 5,
.height_shift = 0,
.hbi_shift = 0,
}; };
static struct cam_ife_csid_common_reg_offset static struct cam_ife_csid_ver1_common_reg_info
cam_ife_csid_170_200_cmn_reg_offset = { cam_ife_csid_170_200_cmn_reg_info = {
.csid_hw_version_addr = 0x0, .hw_version_addr = 0x0,
.csid_cfg0_addr = 0x4, .cfg0_addr = 0x4,
.csid_ctrl_addr = 0x8, .ctrl_addr = 0x8,
.csid_reset_addr = 0xc, .reset_addr = 0xc,
.csid_rst_strobes_addr = 0x10, .rst_strobes_addr = 0x10,
.test_bus_ctrl_addr = 0x14,
.csid_test_bus_ctrl_addr = 0x14, .top_irq_status_addr = 0x70,
.csid_top_irq_status_addr = 0x70, .top_irq_mask_addr = 0x74,
.csid_top_irq_mask_addr = 0x74, .top_irq_clear_addr = 0x78,
.csid_top_irq_clear_addr = 0x78, .top_irq_set_addr = 0x7c,
.csid_top_irq_set_addr = 0x7c, .irq_cmd_addr = 0x80,
.csid_irq_cmd_addr = 0x80,
/*configurations */ /*configurations */
.major_version = 1, .major_version = 1,
.minor_version = 7, .minor_version = 7,
.version_incr = 0, .version_incr = 0,
.num_rdis = 3, .num_rdis = 3,
.num_pix = 1, .num_pix = 1,
.num_ppp = 1, .num_ppp = 1,
.csid_reg_rst_stb = 1, .rst_sw_reg_stb = 1,
.csid_rst_stb = 0x1e, .rst_hw_reg_stb = 0x1e,
.csid_rst_stb_sw_all = 0x1f, .rst_sw_hw_reg_stb = 0x1f,
.path_rst_stb_all = 0x7f, .path_rst_stb_all = 0x7f,
.path_rst_done_shift_val = 1, .rst_done_shift_val = 1,
.path_en_shift_val = 31, .path_en_shift_val = 31,
.packing_fmt_shift_val = 30, .dt_id_shift_val = 27,
.dt_id_shift_val = 27, .vc_shift_val = 22,
.vc_shift_val = 22, .dt_shift_val = 16,
.dt_shift_val = 16, .fmt_shift_val = 12,
.fmt_shift_val = 12, .crop_shift_val = 16,
.plain_fmt_shit_val = 10, .crop_pix_start_mask = 0x3fff,
.crop_v_en_shift_val = 6, .crop_pix_end_mask = 0xffff,
.crop_h_en_shift_val = 5, .crop_line_start_mask = 0x3fff,
.crop_shift = 16, .crop_line_end_mask = 0xffff,
.ipp_irq_mask_all = 0xFFFF, .decode_format_shift_val = 12,
.rdi_irq_mask_all = 0xFFFF, .ipp_irq_mask_all = 0xFFFF,
.ppp_irq_mask_all = 0xFFFF, .rdi_irq_mask_all = 0xFFFF,
.measure_en_hbi_vbi_cnt_mask = 0xC, .ppp_irq_mask_all = 0xFFFF,
.format_measure_en_val = 1, .measure_en_hbi_vbi_cnt_mask = 0xC,
.format_measure_height_mask_val = 0xFFFF, .timestamp_strobe_val = 0x2,
.format_measure_height_shift_val = 0x10, .timestamp_stb_sel_shift_val = 0,
.format_measure_width_mask_val = 0xFFFF,
.format_measure_width_shift_val = 0x0,
}; };
static struct cam_ife_csid_reg_offset cam_ife_csid_170_200_reg_offset = { static struct cam_ife_csid_ver1_reg_info cam_ife_csid_170_200_reg_info = {
.cmn_reg = &cam_ife_csid_170_200_cmn_reg_offset, .cmn_reg = &cam_ife_csid_170_200_cmn_reg_info,
.csi2_reg = &cam_ife_csid_170_200_csi2_reg_offset, .csi2_reg = &cam_ife_csid_170_200_csi2_reg_info,
.ipp_reg = &cam_ife_csid_170_200_ipp_reg_offset, .ipp_reg = &cam_ife_csid_170_200_ipp_reg_info,
.ppp_reg = &cam_ife_csid_170_200_ppp_reg_offset, .ppp_reg = &cam_ife_csid_170_200_ppp_reg_info,
.rdi_reg = { .rdi_reg = {
&cam_ife_csid_170_200_rdi_0_reg_offset, &cam_ife_csid_170_200_rdi_0_reg_info,
&cam_ife_csid_170_200_rdi_1_reg_offset, &cam_ife_csid_170_200_rdi_1_reg_info,
&cam_ife_csid_170_200_rdi_2_reg_offset, &cam_ife_csid_170_200_rdi_2_reg_info,
NULL, NULL,
}, },
.tpg_reg = &cam_ife_csid_170_200_tpg_reg_offset, .tpg_reg = &cam_ife_csid_170_200_tpg_reg_info,
}; };
#endif /*_CAM_IFE_CSID_170_200_H_ */ #endif /*_CAM_IFE_CSID_170_200_H_ */

738
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid175.h
View File

@@ -6,345 +6,463 @@
#ifndef _CAM_IFE_CSID_175_H_ #ifndef _CAM_IFE_CSID_175_H_
#define _CAM_IFE_CSID_175_H_ #define _CAM_IFE_CSID_175_H_
#include "cam_ife_csid_core.h" #include <linux/module.h>
#include "cam_ife_csid_common.h"
#include "cam_ife_csid_hw_ver1.h"
#include "cam_ife_csid_dev.h"
#include "camera_main.h"
static struct cam_ife_csid_pxl_reg_offset cam_ife_csid_175_ipp_reg_offset = { #define CAM_CSID_VERSION_V175 0x10070050
.csid_pxl_irq_status_addr = 0x30, static struct cam_ife_csid_ver1_path_reg_info
.csid_pxl_irq_mask_addr = 0x34, cam_ife_csid_175_ipp_reg_info = {
.csid_pxl_irq_clear_addr = 0x38, .irq_status_addr = 0x30,
.csid_pxl_irq_set_addr = 0x3c, .irq_mask_addr = 0x34,
.irq_clear_addr = 0x38,
.csid_pxl_cfg0_addr = 0x200, .irq_set_addr = 0x3c,
.csid_pxl_cfg1_addr = 0x204, .cfg0_addr = 0x200,
.csid_pxl_ctrl_addr = 0x208, .cfg1_addr = 0x204,
.csid_pxl_frm_drop_pattern_addr = 0x20c, .ctrl_addr = 0x208,
.csid_pxl_frm_drop_period_addr = 0x210, .frm_drop_pattern_addr = 0x20c,
.csid_pxl_irq_subsample_pattern_addr = 0x214, .frm_drop_period_addr = 0x210,
.csid_pxl_irq_subsample_period_addr = 0x218, .irq_subsample_pattern_addr = 0x214,
.csid_pxl_hcrop_addr = 0x21c, .irq_subsample_period_addr = 0x218,
.csid_pxl_vcrop_addr = 0x220, .hcrop_addr = 0x21c,
.csid_pxl_pix_drop_pattern_addr = 0x224, .vcrop_addr = 0x220,
.csid_pxl_pix_drop_period_addr = 0x228, .pix_drop_pattern_addr = 0x224,
.csid_pxl_line_drop_pattern_addr = 0x22c, .pix_drop_period_addr = 0x228,
.csid_pxl_line_drop_period_addr = 0x230, .line_drop_pattern_addr = 0x22c,
.csid_pxl_rst_strobes_addr = 0x240, .line_drop_period_addr = 0x230,
.csid_pxl_status_addr = 0x254, .rst_strobes_addr = 0x240,
.csid_pxl_misr_val_addr = 0x258, .status_addr = 0x254,
.csid_pxl_format_measure_cfg0_addr = 0x270, .misr_val_addr = 0x258,
.csid_pxl_format_measure_cfg1_addr = 0x274, .format_measure_cfg0_addr = 0x270,
.csid_pxl_format_measure0_addr = 0x278, .format_measure_cfg1_addr = 0x274,
.csid_pxl_format_measure1_addr = 0x27c, .format_measure0_addr = 0x278,
.csid_pxl_format_measure2_addr = 0x280, .format_measure1_addr = 0x27c,
.csid_pxl_timestamp_curr0_sof_addr = 0x290, .format_measure2_addr = 0x280,
.csid_pxl_timestamp_curr1_sof_addr = 0x294, .timestamp_curr0_sof_addr = 0x290,
.csid_pxl_timestamp_perv0_sof_addr = 0x298, .timestamp_curr1_sof_addr = 0x294,
.csid_pxl_timestamp_perv1_sof_addr = 0x29c, .timestamp_prev0_sof_addr = 0x298,
.csid_pxl_timestamp_curr0_eof_addr = 0x2a0, .timestamp_prev1_sof_addr = 0x29c,
.csid_pxl_timestamp_curr1_eof_addr = 0x2a4, .timestamp_curr0_eof_addr = 0x2a0,
.csid_pxl_timestamp_perv0_eof_addr = 0x2a8, .timestamp_curr1_eof_addr = 0x2a4,
.csid_pxl_timestamp_perv1_eof_addr = 0x2ac, .timestamp_prev0_eof_addr = 0x2a8,
.timestamp_prev1_eof_addr = 0x2ac,
/* configurations */ /* configurations */
.pix_store_en_shift_val = 7, .halt_master_sel_master_val = 0,
.early_eof_en_shift_val = 29, .halt_master_sel_shift = 4,
.halt_mode_internal = 0,
.halt_mode_global = 1,
.halt_mode_master = 2,
.halt_mode_slave = 3,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.pix_store_en_shift_val = 7,
.early_eof_en_shift_val = 29,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.drop_v_en_shift_val = 4,
.drop_h_en_shift_val = 3,
.timestamp_en_shift_val = 1,
.format_measure_en_shift_val = 0,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x8000,
}; };
static struct cam_ife_csid_pxl_reg_offset cam_ife_csid_175_ppp_reg_offset = { static struct cam_ife_csid_ver1_path_reg_info
.csid_pxl_irq_status_addr = 0xa0, cam_ife_csid_175_ppp_reg_info = {
.csid_pxl_irq_mask_addr = 0xa4, .irq_status_addr = 0xa0,
.csid_pxl_irq_clear_addr = 0xa8, .irq_mask_addr = 0xa4,
.csid_pxl_irq_set_addr = 0xac, .irq_clear_addr = 0xa8,
.irq_set_addr = 0xac,
.csid_pxl_cfg0_addr = 0x700, .cfg0_addr = 0x700,
.csid_pxl_cfg1_addr = 0x704, .cfg1_addr = 0x704,
.csid_pxl_ctrl_addr = 0x708, .ctrl_addr = 0x708,
.csid_pxl_frm_drop_pattern_addr = 0x70c, .frm_drop_pattern_addr = 0x70c,
.csid_pxl_frm_drop_period_addr = 0x710, .frm_drop_period_addr = 0x710,
.csid_pxl_irq_subsample_pattern_addr = 0x714, .irq_subsample_pattern_addr = 0x714,
.csid_pxl_irq_subsample_period_addr = 0x718, .irq_subsample_period_addr = 0x718,
.csid_pxl_hcrop_addr = 0x71c, .hcrop_addr = 0x71c,
.csid_pxl_vcrop_addr = 0x720, .vcrop_addr = 0x720,
.csid_pxl_pix_drop_pattern_addr = 0x724, .pix_drop_pattern_addr = 0x724,
.csid_pxl_pix_drop_period_addr = 0x728, .pix_drop_period_addr = 0x728,
.csid_pxl_line_drop_pattern_addr = 0x72c, .line_drop_pattern_addr = 0x72c,
.csid_pxl_line_drop_period_addr = 0x730, .line_drop_period_addr = 0x730,
.csid_pxl_rst_strobes_addr = 0x740, .rst_strobes_addr = 0x740,
.csid_pxl_status_addr = 0x754, .status_addr = 0x754,
.csid_pxl_misr_val_addr = 0x758, .misr_val_addr = 0x758,
.csid_pxl_format_measure_cfg0_addr = 0x770, .format_measure_cfg0_addr = 0x770,
.csid_pxl_format_measure_cfg1_addr = 0x774, .format_measure_cfg1_addr = 0x774,
.csid_pxl_format_measure0_addr = 0x778, .format_measure0_addr = 0x778,
.csid_pxl_format_measure1_addr = 0x77c, .format_measure1_addr = 0x77c,
.csid_pxl_format_measure2_addr = 0x780, .format_measure2_addr = 0x780,
.csid_pxl_timestamp_curr0_sof_addr = 0x790, .timestamp_curr0_sof_addr = 0x790,
.csid_pxl_timestamp_curr1_sof_addr = 0x794, .timestamp_curr1_sof_addr = 0x794,
.csid_pxl_timestamp_perv0_sof_addr = 0x798, .timestamp_prev0_sof_addr = 0x798,
.csid_pxl_timestamp_perv1_sof_addr = 0x79c, .timestamp_prev1_sof_addr = 0x79c,
.csid_pxl_timestamp_curr0_eof_addr = 0x7a0, .timestamp_curr0_eof_addr = 0x7a0,
.csid_pxl_timestamp_curr1_eof_addr = 0x7a4, .timestamp_curr1_eof_addr = 0x7a4,
.csid_pxl_timestamp_perv0_eof_addr = 0x7a8, .timestamp_prev0_eof_addr = 0x7a8,
.csid_pxl_timestamp_perv1_eof_addr = 0x7ac, .timestamp_prev1_eof_addr = 0x7ac,
/* configurations */ /* configurations */
.pix_store_en_shift_val = 7, .halt_master_sel_master_val = 3,
.early_eof_en_shift_val = 29, .halt_master_sel_shift = 4,
.halt_mode_internal = 0,
.halt_mode_global = 1,
.halt_mode_master = 2,
.halt_mode_slave = 3,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.drop_v_en_shift_val = 4,
.drop_h_en_shift_val = 3,
.pix_store_en_shift_val = 7,
.early_eof_en_shift_val = 29,
.timestamp_en_shift_val = 1,
.format_measure_en_shift_val = 0,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x8000,
}; };
static struct cam_ife_csid_rdi_reg_offset cam_ife_csid_175_rdi_0_reg_offset = { static struct cam_ife_csid_ver1_path_reg_info
.csid_rdi_irq_status_addr = 0x40, cam_ife_csid_175_rdi_0_reg_info = {
.csid_rdi_irq_mask_addr = 0x44, .irq_status_addr = 0x40,
.csid_rdi_irq_clear_addr = 0x48, .irq_mask_addr = 0x44,
.csid_rdi_irq_set_addr = 0x4c, .irq_clear_addr = 0x48,
.csid_rdi_cfg0_addr = 0x300, .irq_set_addr = 0x4c,
.csid_rdi_cfg1_addr = 0x304, .cfg0_addr = 0x300,
.csid_rdi_ctrl_addr = 0x308, .cfg1_addr = 0x304,
.csid_rdi_frm_drop_pattern_addr = 0x30c, .ctrl_addr = 0x308,
.csid_rdi_frm_drop_period_addr = 0x310, .frm_drop_pattern_addr = 0x30c,
.csid_rdi_irq_subsample_pattern_addr = 0x314, .frm_drop_period_addr = 0x310,
.csid_rdi_irq_subsample_period_addr = 0x318, .irq_subsample_pattern_addr = 0x314,
.csid_rdi_rpp_hcrop_addr = 0x31c, .irq_subsample_period_addr = 0x318,
.csid_rdi_rpp_vcrop_addr = 0x320, .hcrop_addr = 0x31c,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x324, .vcrop_addr = 0x320,
.csid_rdi_rpp_pix_drop_period_addr = 0x328, .pix_drop_pattern_addr = 0x324,
.csid_rdi_rpp_line_drop_pattern_addr = 0x32c, .pix_drop_period_addr = 0x328,
.csid_rdi_rpp_line_drop_period_addr = 0x330, .line_drop_pattern_addr = 0x32c,
.csid_rdi_rst_strobes_addr = 0x340, .line_drop_period_addr = 0x330,
.csid_rdi_status_addr = 0x350, .rst_strobes_addr = 0x340,
.csid_rdi_misr_val0_addr = 0x354, .status_addr = 0x350,
.csid_rdi_misr_val1_addr = 0x358, .misr_val0_addr = 0x354,
.csid_rdi_misr_val2_addr = 0x35c, .misr_val1_addr = 0x358,
.csid_rdi_misr_val3_addr = 0x360, .misr_val2_addr = 0x35c,
.csid_rdi_format_measure_cfg0_addr = 0x370, .misr_val3_addr = 0x360,
.csid_rdi_format_measure_cfg1_addr = 0x374, .format_measure_cfg0_addr = 0x370,
.csid_rdi_format_measure0_addr = 0x378, .format_measure_cfg1_addr = 0x374,
.csid_rdi_format_measure1_addr = 0x37c, .format_measure0_addr = 0x378,
.csid_rdi_format_measure2_addr = 0x380, .format_measure1_addr = 0x37c,
.csid_rdi_timestamp_curr0_sof_addr = 0x390, .format_measure2_addr = 0x380,
.csid_rdi_timestamp_curr1_sof_addr = 0x394, .timestamp_curr0_sof_addr = 0x390,
.csid_rdi_timestamp_prev0_sof_addr = 0x398, .timestamp_curr1_sof_addr = 0x394,
.csid_rdi_timestamp_prev1_sof_addr = 0x39c, .timestamp_prev0_sof_addr = 0x398,
.csid_rdi_timestamp_curr0_eof_addr = 0x3a0, .timestamp_prev1_sof_addr = 0x39c,
.csid_rdi_timestamp_curr1_eof_addr = 0x3a4, .timestamp_curr0_eof_addr = 0x3a0,
.csid_rdi_timestamp_prev0_eof_addr = 0x3a8, .timestamp_curr1_eof_addr = 0x3a4,
.csid_rdi_timestamp_prev1_eof_addr = 0x3ac, .timestamp_prev0_eof_addr = 0x3a8,
.csid_rdi_byte_cntr_ping_addr = 0x3e0, .timestamp_prev1_eof_addr = 0x3ac,
.csid_rdi_byte_cntr_pong_addr = 0x3e4, .byte_cntr_ping_addr = 0x3e0,
.byte_cntr_pong_addr = 0x3e4,
.plain_fmt_shift_val = 10,
.halt_mode_internal = 0,
.halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.drop_v_en_shift_val = 4,
.drop_h_en_shift_val = 3,
.timestamp_en_shift_val = 2,
.format_measure_en_shift_val = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x8000,
}; };
static struct cam_ife_csid_rdi_reg_offset cam_ife_csid_175_rdi_1_reg_offset = { static struct cam_ife_csid_ver1_path_reg_info
.csid_rdi_irq_status_addr = 0x50, cam_ife_csid_175_rdi_1_reg_info = {
.csid_rdi_irq_mask_addr = 0x54, .irq_status_addr = 0x50,
.csid_rdi_irq_clear_addr = 0x58, .irq_mask_addr = 0x54,
.csid_rdi_irq_set_addr = 0x5c, .irq_clear_addr = 0x58,
.csid_rdi_cfg0_addr = 0x400, .irq_set_addr = 0x5c,
.csid_rdi_cfg1_addr = 0x404, .cfg0_addr = 0x400,
.csid_rdi_ctrl_addr = 0x408, .cfg1_addr = 0x404,
.csid_rdi_frm_drop_pattern_addr = 0x40c, .ctrl_addr = 0x408,
.csid_rdi_frm_drop_period_addr = 0x410, .frm_drop_pattern_addr = 0x40c,
.csid_rdi_irq_subsample_pattern_addr = 0x414, .frm_drop_period_addr = 0x410,
.csid_rdi_irq_subsample_period_addr = 0x418, .irq_subsample_pattern_addr = 0x414,
.csid_rdi_rpp_hcrop_addr = 0x41c, .irq_subsample_period_addr = 0x418,
.csid_rdi_rpp_vcrop_addr = 0x420, .hcrop_addr = 0x41c,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x424, .vcrop_addr = 0x420,
.csid_rdi_rpp_pix_drop_period_addr = 0x428, .pix_drop_pattern_addr = 0x424,
.csid_rdi_rpp_line_drop_pattern_addr = 0x42c, .pix_drop_period_addr = 0x428,
.csid_rdi_rpp_line_drop_period_addr = 0x430, .line_drop_pattern_addr = 0x42c,
.csid_rdi_rst_strobes_addr = 0x440, .line_drop_period_addr = 0x430,
.csid_rdi_status_addr = 0x450, .rst_strobes_addr = 0x440,
.csid_rdi_misr_val0_addr = 0x454, .status_addr = 0x450,
.csid_rdi_misr_val1_addr = 0x458, .misr_val0_addr = 0x454,
.csid_rdi_misr_val2_addr = 0x45c, .misr_val1_addr = 0x458,
.csid_rdi_misr_val3_addr = 0x460, .misr_val2_addr = 0x45c,
.csid_rdi_format_measure_cfg0_addr = 0x470, .misr_val3_addr = 0x460,
.csid_rdi_format_measure_cfg1_addr = 0x474, .format_measure_cfg0_addr = 0x470,
.csid_rdi_format_measure0_addr = 0x478, .format_measure_cfg1_addr = 0x474,
.csid_rdi_format_measure1_addr = 0x47c, .format_measure0_addr = 0x478,
.csid_rdi_format_measure2_addr = 0x480, .format_measure1_addr = 0x47c,
.csid_rdi_timestamp_curr0_sof_addr = 0x490, .format_measure2_addr = 0x480,
.csid_rdi_timestamp_curr1_sof_addr = 0x494, .timestamp_curr0_sof_addr = 0x490,
.csid_rdi_timestamp_prev0_sof_addr = 0x498, .timestamp_curr1_sof_addr = 0x494,
.csid_rdi_timestamp_prev1_sof_addr = 0x49c, .timestamp_prev0_sof_addr = 0x498,
.csid_rdi_timestamp_curr0_eof_addr = 0x4a0, .timestamp_prev1_sof_addr = 0x49c,
.csid_rdi_timestamp_curr1_eof_addr = 0x4a4, .timestamp_curr0_eof_addr = 0x4a0,
.csid_rdi_timestamp_prev0_eof_addr = 0x4a8, .timestamp_curr1_eof_addr = 0x4a4,
.csid_rdi_timestamp_prev1_eof_addr = 0x4ac, .timestamp_prev0_eof_addr = 0x4a8,
.csid_rdi_byte_cntr_ping_addr = 0x4e0, .timestamp_prev1_eof_addr = 0x4ac,
.csid_rdi_byte_cntr_pong_addr = 0x4e4, .byte_cntr_ping_addr = 0x4e0,
.byte_cntr_pong_addr = 0x4e4,
.halt_mode_internal = 0,
.halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.plain_fmt_shift_val = 10,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.timestamp_en_shift_val = 2,
.format_measure_en_shift_val = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x8000,
}; };
static struct cam_ife_csid_rdi_reg_offset cam_ife_csid_175_rdi_2_reg_offset = { static struct cam_ife_csid_ver1_path_reg_info
.csid_rdi_irq_status_addr = 0x60, cam_ife_csid_175_rdi_2_reg_info = {
.csid_rdi_irq_mask_addr = 0x64, .irq_status_addr = 0x60,
.csid_rdi_irq_clear_addr = 0x68, .irq_mask_addr = 0x64,
.csid_rdi_irq_set_addr = 0x6c, .irq_clear_addr = 0x68,
.csid_rdi_cfg0_addr = 0x500, .irq_set_addr = 0x6c,
.csid_rdi_cfg1_addr = 0x504, .cfg0_addr = 0x500,
.csid_rdi_ctrl_addr = 0x508, .cfg1_addr = 0x504,
.csid_rdi_frm_drop_pattern_addr = 0x50c, .ctrl_addr = 0x508,
.csid_rdi_frm_drop_period_addr = 0x510, .frm_drop_pattern_addr = 0x50c,
.csid_rdi_irq_subsample_pattern_addr = 0x514, .frm_drop_period_addr = 0x510,
.csid_rdi_irq_subsample_period_addr = 0x518, .irq_subsample_pattern_addr = 0x514,
.csid_rdi_rpp_hcrop_addr = 0x51c, .irq_subsample_period_addr = 0x518,
.csid_rdi_rpp_vcrop_addr = 0x520, .hcrop_addr = 0x51c,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x524, .vcrop_addr = 0x520,
.csid_rdi_rpp_pix_drop_period_addr = 0x528, .pix_drop_pattern_addr = 0x524,
.csid_rdi_rpp_line_drop_pattern_addr = 0x52c, .pix_drop_period_addr = 0x528,
.csid_rdi_rpp_line_drop_period_addr = 0x530, .line_drop_pattern_addr = 0x52c,
.csid_rdi_yuv_chroma_conversion_addr = 0x534, .line_drop_period_addr = 0x530,
.csid_rdi_rst_strobes_addr = 0x540, .yuv_chroma_conversion_addr = 0x534,
.csid_rdi_status_addr = 0x550, .rst_strobes_addr = 0x540,
.csid_rdi_misr_val0_addr = 0x554, .status_addr = 0x550,
.csid_rdi_misr_val1_addr = 0x558, .misr_val0_addr = 0x554,
.csid_rdi_misr_val2_addr = 0x55c, .misr_val1_addr = 0x558,
.csid_rdi_misr_val3_addr = 0x560, .misr_val2_addr = 0x55c,
.csid_rdi_format_measure_cfg0_addr = 0x570, .misr_val3_addr = 0x560,
.csid_rdi_format_measure_cfg1_addr = 0x574, .format_measure_cfg0_addr = 0x570,
.csid_rdi_format_measure0_addr = 0x578, .format_measure_cfg1_addr = 0x574,
.csid_rdi_format_measure1_addr = 0x57c, .format_measure0_addr = 0x578,
.csid_rdi_format_measure2_addr = 0x580, .format_measure1_addr = 0x57c,
.csid_rdi_timestamp_curr0_sof_addr = 0x590, .format_measure2_addr = 0x580,
.csid_rdi_timestamp_curr1_sof_addr = 0x594, .timestamp_curr0_sof_addr = 0x590,
.csid_rdi_timestamp_prev0_sof_addr = 0x598, .timestamp_curr1_sof_addr = 0x594,
.csid_rdi_timestamp_prev1_sof_addr = 0x59c, .timestamp_prev0_sof_addr = 0x598,
.csid_rdi_timestamp_curr0_eof_addr = 0x5a0, .timestamp_prev1_sof_addr = 0x59c,
.csid_rdi_timestamp_curr1_eof_addr = 0x5a4, .timestamp_curr0_eof_addr = 0x5a0,
.csid_rdi_timestamp_prev0_eof_addr = 0x5a8, .timestamp_curr1_eof_addr = 0x5a4,
.csid_rdi_timestamp_prev1_eof_addr = 0x5ac, .timestamp_prev0_eof_addr = 0x5a8,
.csid_rdi_byte_cntr_ping_addr = 0x5e0, .timestamp_prev1_eof_addr = 0x5ac,
.csid_rdi_byte_cntr_pong_addr = 0x5e4, .byte_cntr_ping_addr = 0x5e0,
.byte_cntr_pong_addr = 0x5e4,
.halt_mode_internal = 0,
.halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.plain_fmt_shift_val = 10,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.timestamp_en_shift_val = 2,
.format_measure_en_shift_val = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x8000,
}; };
static struct cam_ife_csid_csi2_rx_reg_offset static struct cam_ife_csid_csi2_rx_reg_info
cam_ife_csid_175_csi2_reg_offset = { cam_ife_csid_175_csi2_reg_info = {
.csid_csi2_rx_irq_status_addr = 0x20, .irq_status_addr = 0x20,
.csid_csi2_rx_irq_mask_addr = 0x24, .irq_mask_addr = 0x24,
.csid_csi2_rx_irq_clear_addr = 0x28, .irq_clear_addr = 0x28,
.csid_csi2_rx_irq_set_addr = 0x2c, .irq_set_addr = 0x2c,
/*CSI2 rx control */ /*CSI2 rx control */
.csid_csi2_rx_cfg0_addr = 0x100, .cfg0_addr = 0x100,
.csid_csi2_rx_cfg1_addr = 0x104, .cfg1_addr = 0x104,
.csid_csi2_rx_capture_ctrl_addr = 0x108, .capture_ctrl_addr = 0x108,
.csid_csi2_rx_rst_strobes_addr = 0x110, .rst_strobes_addr = 0x110,
.csid_csi2_rx_de_scramble_cfg0_addr = 0x114, .de_scramble_cfg0_addr = 0x114,
.csid_csi2_rx_de_scramble_cfg1_addr = 0x118, .de_scramble_cfg1_addr = 0x118,
.csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr = 0x120, .cap_unmap_long_pkt_hdr_0_addr = 0x120,
.csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr = 0x124, .cap_unmap_long_pkt_hdr_1_addr = 0x124,
.csid_csi2_rx_captured_short_pkt_0_addr = 0x128, .captured_short_pkt_0_addr = 0x128,
.csid_csi2_rx_captured_short_pkt_1_addr = 0x12c, .captured_short_pkt_1_addr = 0x12c,
.csid_csi2_rx_captured_long_pkt_0_addr = 0x130, .captured_long_pkt_0_addr = 0x130,
.csid_csi2_rx_captured_long_pkt_1_addr = 0x134, .captured_long_pkt_1_addr = 0x134,
.csid_csi2_rx_captured_long_pkt_ftr_addr = 0x138, .captured_long_pkt_ftr_addr = 0x138,
.csid_csi2_rx_captured_cphy_pkt_hdr_addr = 0x13c, .captured_cphy_pkt_hdr_addr = 0x13c,
.csid_csi2_rx_lane0_misr_addr = 0x150, .lane0_misr_addr = 0x150,
.csid_csi2_rx_lane1_misr_addr = 0x154, .lane1_misr_addr = 0x154,
.csid_csi2_rx_lane2_misr_addr = 0x158, .lane2_misr_addr = 0x158,
.csid_csi2_rx_lane3_misr_addr = 0x15c, .lane3_misr_addr = 0x15c,
.csid_csi2_rx_total_pkts_rcvd_addr = 0x160, .total_pkts_rcvd_addr = 0x160,
.csid_csi2_rx_stats_ecc_addr = 0x164, .stats_ecc_addr = 0x164,
.csid_csi2_rx_total_crc_err_addr = 0x168, .total_crc_err_addr = 0x168,
.csi2_rst_srb_all = 0x3FFF, .rst_srb_all = 0x3FFF,
.csi2_rst_done_shift_val = 27, .rst_done_shift_val = 27,
.csi2_irq_mask_all = 0xFFFFFFF, .irq_mask_all = 0xFFFFFFF,
.csi2_misr_enable_shift_val = 6, .misr_enable_shift_val = 6,
.csi2_vc_mode_shift_val = 2, .vc_mode_shift_val = 2,
.csi2_capture_long_pkt_en_shift = 0, .capture_long_pkt_en_shift = 0,
.csi2_capture_short_pkt_en_shift = 1, .capture_short_pkt_en_shift = 1,
.csi2_capture_cphy_pkt_en_shift = 2, .capture_cphy_pkt_en_shift = 2,
.csi2_capture_long_pkt_dt_shift = 4, .capture_long_pkt_dt_shift = 4,
.csi2_capture_long_pkt_vc_shift = 10, .capture_long_pkt_vc_shift = 10,
.csi2_capture_short_pkt_vc_shift = 15, .capture_short_pkt_vc_shift = 15,
.csi2_capture_cphy_pkt_dt_shift = 20, .capture_cphy_pkt_dt_shift = 20,
.csi2_capture_cphy_pkt_vc_shift = 26, .capture_cphy_pkt_vc_shift = 26,
.csi2_rx_phy_num_mask = 0x3, .phy_num_mask = 0x3,
.vc_mask = 0x7C00000,
.dt_mask = 0x3f0000,
.wc_mask = 0xffff0000,
.calc_crc_mask = 0xffff,
.expected_crc_mask = 0xffff,
.ecc_correction_shift_en = 0,
.lane_num_shift = 0,
.lane_cfg_shift = 4,
.phy_type_shift = 24,
.phy_num_shift = 20,
.fatal_err_mask = 0x78000,
.part_fatal_err_mask = 0x1801800,
.non_fatal_err_mask = 0x380000,
}; };
static struct cam_ife_csid_csi2_tpg_reg_offset static struct cam_ife_csid_ver1_tpg_reg_info
cam_ife_csid_175_tpg_reg_offset = { cam_ife_csid_175_tpg_reg_info = {
/*CSID TPG control */ /*CSID TPG control */
.csid_tpg_ctrl_addr = 0x600, .ctrl_addr = 0x600,
.csid_tpg_vc_cfg0_addr = 0x604, .vc_cfg0_addr = 0x604,
.csid_tpg_vc_cfg1_addr = 0x608, .vc_cfg1_addr = 0x608,
.csid_tpg_lfsr_seed_addr = 0x60c, .lfsr_seed_addr = 0x60c,
.csid_tpg_dt_n_cfg_0_addr = 0x610, .dt_n_cfg_0_addr = 0x610,
.csid_tpg_dt_n_cfg_1_addr = 0x614, .dt_n_cfg_1_addr = 0x614,
.csid_tpg_dt_n_cfg_2_addr = 0x618, .dt_n_cfg_2_addr = 0x618,
.csid_tpg_color_bars_cfg_addr = 0x640, .color_bars_cfg_addr = 0x640,
.csid_tpg_color_box_cfg_addr = 0x644, .color_box_cfg_addr = 0x644,
.csid_tpg_common_gen_cfg_addr = 0x648, .common_gen_cfg_addr = 0x648,
.csid_tpg_cgen_n_cfg_addr = 0x650, .cgen_n_cfg_addr = 0x650,
.csid_tpg_cgen_n_x0_addr = 0x654, .cgen_n_x0_addr = 0x654,
.csid_tpg_cgen_n_x1_addr = 0x658, .cgen_n_x1_addr = 0x658,
.csid_tpg_cgen_n_x2_addr = 0x65c, .cgen_n_x2_addr = 0x65c,
.csid_tpg_cgen_n_xy_addr = 0x660, .cgen_n_xy_addr = 0x660,
.csid_tpg_cgen_n_y1_addr = 0x664, .cgen_n_y1_addr = 0x664,
.csid_tpg_cgen_n_y2_addr = 0x668, .cgen_n_y2_addr = 0x668,
/* configurations */ /* configurations */
.tpg_dtn_cfg_offset = 0xc, .dtn_cfg_offset = 0xc,
.tpg_cgen_cfg_offset = 0x20, .cgen_cfg_offset = 0x20,
.tpg_cpas_ife_reg_offset = 0x28, .cpas_ife_reg_offset = 0x28,
.hbi = 0x740,
.vbi = 0x3FF,
.lfsr_seed = 0x12345678,
.ctrl_cfg = 0x408007,
.color_bar = 1,
.num_frames = 0,
.line_interleave_mode = 0x1,
.payload_mode = 0x8,
.num_active_lanes_mask = 0x30,
.num_active_dt = 0,
.fmt_shift = 16,
.num_frame_shift = 16,
.width_shift = 16,
.vbi_shift = 12,
.line_interleave_shift = 10,
.num_active_dt_shift = 8,
.color_bar_shift = 5,
.height_shift = 0,
.hbi_shift = 0,
}; };
static struct cam_ife_csid_common_reg_offset static struct cam_ife_csid_ver1_common_reg_info
cam_ife_csid_175_cmn_reg_offset = { cam_ife_csid_175_cmn_reg_info = {
.csid_hw_version_addr = 0x0, .hw_version_addr = 0x0,
.csid_cfg0_addr = 0x4, .cfg0_addr = 0x4,
.csid_ctrl_addr = 0x8, .ctrl_addr = 0x8,
.csid_reset_addr = 0xc, .reset_addr = 0xc,
.csid_rst_strobes_addr = 0x10, .rst_strobes_addr = 0x10,
.test_bus_ctrl_addr = 0x14,
.csid_test_bus_ctrl_addr = 0x14, .top_irq_status_addr = 0x70,
.csid_top_irq_status_addr = 0x70, .top_irq_mask_addr = 0x74,
.csid_top_irq_mask_addr = 0x74, .top_irq_clear_addr = 0x78,
.csid_top_irq_clear_addr = 0x78, .top_irq_set_addr = 0x7c,
.csid_top_irq_set_addr = 0x7c, .irq_cmd_addr = 0x80,
.csid_irq_cmd_addr = 0x80,
/*configurations */ /*configurations */
.major_version = 1, .major_version = 1,
.minor_version = 7, .minor_version = 7,
.version_incr = 0, .version_incr = 0,
.num_rdis = 3, .num_rdis = 3,
.num_pix = 1, .num_pix = 1,
.num_ppp = 1, .num_ppp = 1,
.csid_reg_rst_stb = 1, .rst_sw_reg_stb = 1,
.csid_rst_stb = 0x1e, .rst_hw_reg_stb = 0x1e,
.csid_rst_stb_sw_all = 0x1f, .rst_sw_hw_reg_stb = 0x1f,
.path_rst_stb_all = 0x7f, .path_rst_stb_all = 0x7f,
.path_rst_done_shift_val = 1, .rst_done_shift_val = 1,
.path_en_shift_val = 31, .path_en_shift_val = 31,
.dt_id_shift_val = 27, .dt_id_shift_val = 27,
.vc_shift_val = 22, .vc_shift_val = 22,
.dt_shift_val = 16, .dt_shift_val = 16,
.fmt_shift_val = 12, .fmt_shift_val = 12,
.plain_fmt_shit_val = 10, .crop_shift_val = 16,
.crop_v_en_shift_val = 6, .decode_format_shift_val = 12,
.crop_h_en_shift_val = 5, .crop_pix_start_mask = 0x3fff,
.crop_shift = 16, .crop_pix_end_mask = 0xffff,
.ipp_irq_mask_all = 0x7FFF, .crop_line_start_mask = 0x3fff,
.rdi_irq_mask_all = 0x7FFF, .crop_line_end_mask = 0xffff,
.ppp_irq_mask_all = 0xFFFF, .ipp_irq_mask_all = 0x7FFF,
.measure_en_hbi_vbi_cnt_mask = 0xC, .rdi_irq_mask_all = 0x7FFF,
.format_measure_en_val = 1, .ppp_irq_mask_all = 0xFFFF,
.format_measure_height_mask_val = 0xFFFF, .measure_en_hbi_vbi_cnt_mask = 0xC,
.format_measure_height_shift_val = 0x10, .timestamp_stb_sel_shift_val = 0,
.format_measure_width_mask_val = 0xFFFF, .timestamp_strobe_val = 0x2,
.format_measure_width_shift_val = 0x0,
}; };
static struct cam_ife_csid_reg_offset cam_ife_csid_175_reg_offset = { static struct cam_ife_csid_ver1_reg_info cam_ife_csid_175_reg_info = {
.cmn_reg = &cam_ife_csid_175_cmn_reg_offset, .cmn_reg = &cam_ife_csid_175_cmn_reg_info,
.csi2_reg = &cam_ife_csid_175_csi2_reg_offset, .csi2_reg = &cam_ife_csid_175_csi2_reg_info,
.ipp_reg = &cam_ife_csid_175_ipp_reg_offset, .ipp_reg = &cam_ife_csid_175_ipp_reg_info,
.ppp_reg = &cam_ife_csid_175_ppp_reg_offset, .ppp_reg = &cam_ife_csid_175_ppp_reg_info,
.rdi_reg = { .rdi_reg = {
&cam_ife_csid_175_rdi_0_reg_offset, &cam_ife_csid_175_rdi_0_reg_info,
&cam_ife_csid_175_rdi_1_reg_offset, &cam_ife_csid_175_rdi_1_reg_info,
&cam_ife_csid_175_rdi_2_reg_offset, &cam_ife_csid_175_rdi_2_reg_info,
NULL, NULL,
}, },
.tpg_reg = &cam_ife_csid_175_tpg_reg_offset, .tpg_reg = &cam_ife_csid_175_tpg_reg_info,
}; };
#endif /*_CAM_IFE_CSID_175_H_ */ #endif /*_CAM_IFE_CSID_175_H_ */

774
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid175_200.h
View File

@@ -6,363 +6,481 @@
#ifndef _CAM_IFE_CSID_175_200_H_ #ifndef _CAM_IFE_CSID_175_200_H_
#define _CAM_IFE_CSID_175_200_H_ #define _CAM_IFE_CSID_175_200_H_
#include "cam_ife_csid_core.h" #include <linux/module.h>
#include "camera_main.h"
#include "cam_ife_csid_dev.h"
#include "cam_ife_csid_common.h"
#include "cam_ife_csid_hw_ver1.h"
static struct cam_ife_csid_pxl_reg_offset #define CAM_CSID_DRV_NAME "csid"
cam_ife_csid_175_200_ipp_reg_offset = { #define CAM_CSID_VERSION_V175 0x10070050
.csid_pxl_irq_status_addr = 0x30,
.csid_pxl_irq_mask_addr = 0x34,
.csid_pxl_irq_clear_addr = 0x38,
.csid_pxl_irq_set_addr = 0x3c,
.csid_pxl_cfg0_addr = 0x200, static struct cam_ife_csid_ver1_path_reg_info
.csid_pxl_cfg1_addr = 0x204, cam_ife_csid_175_200_ipp_reg_info = {
.csid_pxl_ctrl_addr = 0x208, .irq_status_addr = 0x30,
.csid_pxl_frm_drop_pattern_addr = 0x20c, .irq_mask_addr = 0x34,
.csid_pxl_frm_drop_period_addr = 0x210, .irq_clear_addr = 0x38,
.csid_pxl_irq_subsample_pattern_addr = 0x214, .irq_set_addr = 0x3c,
.csid_pxl_irq_subsample_period_addr = 0x218, .cfg0_addr = 0x200,
.csid_pxl_hcrop_addr = 0x21c, .cfg1_addr = 0x204,
.csid_pxl_vcrop_addr = 0x220, .ctrl_addr = 0x208,
.csid_pxl_pix_drop_pattern_addr = 0x224, .frm_drop_pattern_addr = 0x20c,
.csid_pxl_pix_drop_period_addr = 0x228, .frm_drop_period_addr = 0x210,
.csid_pxl_line_drop_pattern_addr = 0x22c, .irq_subsample_pattern_addr = 0x214,
.csid_pxl_line_drop_period_addr = 0x230, .irq_subsample_period_addr = 0x218,
.csid_pxl_rst_strobes_addr = 0x240, .hcrop_addr = 0x21c,
.csid_pxl_status_addr = 0x254, .vcrop_addr = 0x220,
.csid_pxl_misr_val_addr = 0x258, .pix_drop_pattern_addr = 0x224,
.csid_pxl_format_measure_cfg0_addr = 0x270, .pix_drop_period_addr = 0x228,
.csid_pxl_format_measure_cfg1_addr = 0x274, .line_drop_pattern_addr = 0x22c,
.csid_pxl_format_measure0_addr = 0x278, .line_drop_period_addr = 0x230,
.csid_pxl_format_measure1_addr = 0x27c, .rst_strobes_addr = 0x240,
.csid_pxl_format_measure2_addr = 0x280, .status_addr = 0x254,
.csid_pxl_timestamp_curr0_sof_addr = 0x290, .misr_val_addr = 0x258,
.csid_pxl_timestamp_curr1_sof_addr = 0x294, .format_measure_cfg0_addr = 0x270,
.csid_pxl_timestamp_perv0_sof_addr = 0x298, .format_measure_cfg1_addr = 0x274,
.csid_pxl_timestamp_perv1_sof_addr = 0x29c, .format_measure0_addr = 0x278,
.csid_pxl_timestamp_curr0_eof_addr = 0x2a0, .format_measure1_addr = 0x27c,
.csid_pxl_timestamp_curr1_eof_addr = 0x2a4, .format_measure2_addr = 0x280,
.csid_pxl_timestamp_perv0_eof_addr = 0x2a8, .timestamp_curr0_sof_addr = 0x290,
.csid_pxl_timestamp_perv1_eof_addr = 0x2ac, .timestamp_curr1_sof_addr = 0x294,
.timestamp_prev0_sof_addr = 0x298,
.timestamp_prev1_sof_addr = 0x29c,
.timestamp_curr0_eof_addr = 0x2a0,
.timestamp_curr1_eof_addr = 0x2a4,
.timestamp_prev0_eof_addr = 0x2a8,
.timestamp_prev1_eof_addr = 0x2ac,
/* configurations */ /* configurations */
.pix_store_en_shift_val = 7, .halt_master_sel_master_val = 0,
.early_eof_en_shift_val = 29, .halt_master_sel_shift = 4,
.quad_cfa_bin_en_shift_val = 30, .halt_mode_internal = 0,
.ccif_violation_en = 1, .halt_mode_global = 1,
.halt_mode_master = 2,
.halt_mode_slave = 3,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.pix_store_en_shift_val = 7,
.early_eof_en_shift_val = 29,
.bin_qcfa_en_shift_val = 30,
.bin_h_en_shift_val = 2,
.bin_en_shift_val = 2,
.binning_supported = 0x3,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.drop_v_en_shift_val = 4,
.drop_h_en_shift_val = 3,
.timestamp_en_shift_val = 1,
.format_measure_en_shift_val = 0,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x8000,
}; };
static struct cam_ife_csid_pxl_reg_offset static struct cam_ife_csid_ver1_path_reg_info
cam_ife_csid_175_200_ppp_reg_offset = { cam_ife_csid_175_200_ppp_reg_info = {
.csid_pxl_irq_status_addr = 0xa0, .irq_status_addr = 0xa0,
.csid_pxl_irq_mask_addr = 0xa4, .irq_mask_addr = 0xa4,
.csid_pxl_irq_clear_addr = 0xa8, .irq_clear_addr = 0xa8,
.csid_pxl_irq_set_addr = 0xac, .irq_set_addr = 0xac,
.cfg0_addr = 0x700,
.csid_pxl_cfg0_addr = 0x700, .cfg1_addr = 0x704,
.csid_pxl_cfg1_addr = 0x704, .ctrl_addr = 0x708,
.csid_pxl_ctrl_addr = 0x708, .frm_drop_pattern_addr = 0x70c,
.csid_pxl_frm_drop_pattern_addr = 0x70c, .frm_drop_period_addr = 0x710,
.csid_pxl_frm_drop_period_addr = 0x710, .irq_subsample_pattern_addr = 0x714,
.csid_pxl_irq_subsample_pattern_addr = 0x714, .irq_subsample_period_addr = 0x718,
.csid_pxl_irq_subsample_period_addr = 0x718, .hcrop_addr = 0x71c,
.csid_pxl_hcrop_addr = 0x71c, .vcrop_addr = 0x720,
.csid_pxl_vcrop_addr = 0x720, .pix_drop_pattern_addr = 0x724,
.csid_pxl_pix_drop_pattern_addr = 0x724, .pix_drop_period_addr = 0x728,
.csid_pxl_pix_drop_period_addr = 0x728, .line_drop_pattern_addr = 0x72c,
.csid_pxl_line_drop_pattern_addr = 0x72c, .line_drop_period_addr = 0x730,
.csid_pxl_line_drop_period_addr = 0x730, .rst_strobes_addr = 0x740,
.csid_pxl_rst_strobes_addr = 0x740, .status_addr = 0x754,
.csid_pxl_status_addr = 0x754, .misr_val_addr = 0x758,
.csid_pxl_misr_val_addr = 0x758, .format_measure_cfg0_addr = 0x770,
.csid_pxl_format_measure_cfg0_addr = 0x770, .format_measure_cfg1_addr = 0x774,
.csid_pxl_format_measure_cfg1_addr = 0x774, .format_measure0_addr = 0x778,
.csid_pxl_format_measure0_addr = 0x778, .format_measure1_addr = 0x77c,
.csid_pxl_format_measure1_addr = 0x77c, .format_measure2_addr = 0x780,
.csid_pxl_format_measure2_addr = 0x780, .timestamp_curr0_sof_addr = 0x790,
.csid_pxl_timestamp_curr0_sof_addr = 0x790, .timestamp_curr1_sof_addr = 0x794,
.csid_pxl_timestamp_curr1_sof_addr = 0x794, .timestamp_prev0_sof_addr = 0x798,
.csid_pxl_timestamp_perv0_sof_addr = 0x798, .timestamp_prev1_sof_addr = 0x79c,
.csid_pxl_timestamp_perv1_sof_addr = 0x79c, .timestamp_curr0_eof_addr = 0x7a0,
.csid_pxl_timestamp_curr0_eof_addr = 0x7a0, .timestamp_curr1_eof_addr = 0x7a4,
.csid_pxl_timestamp_curr1_eof_addr = 0x7a4, .timestamp_prev0_eof_addr = 0x7a8,
.csid_pxl_timestamp_perv0_eof_addr = 0x7a8, .timestamp_prev1_eof_addr = 0x7ac,
.csid_pxl_timestamp_perv1_eof_addr = 0x7ac,
/* configurations */ /* configurations */
.pix_store_en_shift_val = 7, .halt_master_sel_master_val = 3,
.early_eof_en_shift_val = 29, .halt_master_sel_shift = 4,
.ccif_violation_en = 1, .halt_mode_internal = 0,
.halt_mode_global = 1,
.halt_mode_master = 2,
.halt_mode_slave = 3,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.pix_store_en_shift_val = 7,
.early_eof_en_shift_val = 29,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.drop_v_en_shift_val = 4,
.drop_h_en_shift_val = 3,
.timestamp_en_shift_val = 1,
.format_measure_en_shift_val = 0,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x8000,
}; };
static struct cam_ife_csid_rdi_reg_offset static struct cam_ife_csid_ver1_path_reg_info
cam_ife_csid_175_200_rdi_0_reg_offset = { cam_ife_csid_175_200_rdi_0_reg_info = {
.csid_rdi_irq_status_addr = 0x40, .irq_status_addr = 0x40,
.csid_rdi_irq_mask_addr = 0x44, .irq_mask_addr = 0x44,
.csid_rdi_irq_clear_addr = 0x48, .irq_clear_addr = 0x48,
.csid_rdi_irq_set_addr = 0x4c, .irq_set_addr = 0x4c,
.csid_rdi_cfg0_addr = 0x300, .cfg0_addr = 0x300,
.csid_rdi_cfg1_addr = 0x304, .cfg1_addr = 0x304,
.csid_rdi_ctrl_addr = 0x308, .ctrl_addr = 0x308,
.csid_rdi_frm_drop_pattern_addr = 0x30c, .frm_drop_pattern_addr = 0x30c,
.csid_rdi_frm_drop_period_addr = 0x310, .frm_drop_period_addr = 0x310,
.csid_rdi_irq_subsample_pattern_addr = 0x314, .irq_subsample_pattern_addr = 0x314,
.csid_rdi_irq_subsample_period_addr = 0x318, .irq_subsample_period_addr = 0x318,
.csid_rdi_rpp_hcrop_addr = 0x31c, .hcrop_addr = 0x31c,
.csid_rdi_rpp_vcrop_addr = 0x320, .vcrop_addr = 0x320,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x324, .pix_drop_pattern_addr = 0x324,
.csid_rdi_rpp_pix_drop_period_addr = 0x328, .pix_drop_period_addr = 0x328,
.csid_rdi_rpp_line_drop_pattern_addr = 0x32c, .line_drop_pattern_addr = 0x32c,
.csid_rdi_rpp_line_drop_period_addr = 0x330, .line_drop_period_addr = 0x330,
.csid_rdi_rst_strobes_addr = 0x340, .rst_strobes_addr = 0x340,
.csid_rdi_status_addr = 0x350, .status_addr = 0x350,
.csid_rdi_misr_val0_addr = 0x354, .misr_val0_addr = 0x354,
.csid_rdi_misr_val1_addr = 0x358, .misr_val1_addr = 0x358,
.csid_rdi_misr_val2_addr = 0x35c, .misr_val2_addr = 0x35c,
.csid_rdi_misr_val3_addr = 0x360, .misr_val3_addr = 0x360,
.csid_rdi_format_measure_cfg0_addr = 0x370, .format_measure_cfg0_addr = 0x370,
.csid_rdi_format_measure_cfg1_addr = 0x374, .format_measure_cfg1_addr = 0x374,
.csid_rdi_format_measure0_addr = 0x378, .format_measure0_addr = 0x378,
.csid_rdi_format_measure1_addr = 0x37c, .format_measure1_addr = 0x37c,
.csid_rdi_format_measure2_addr = 0x380, .format_measure2_addr = 0x380,
.csid_rdi_timestamp_curr0_sof_addr = 0x390, .timestamp_curr0_sof_addr = 0x390,
.csid_rdi_timestamp_curr1_sof_addr = 0x394, .timestamp_curr1_sof_addr = 0x394,
.csid_rdi_timestamp_prev0_sof_addr = 0x398, .timestamp_prev0_sof_addr = 0x398,
.csid_rdi_timestamp_prev1_sof_addr = 0x39c, .timestamp_prev1_sof_addr = 0x39c,
.csid_rdi_timestamp_curr0_eof_addr = 0x3a0, .timestamp_curr0_eof_addr = 0x3a0,
.csid_rdi_timestamp_curr1_eof_addr = 0x3a4, .timestamp_curr1_eof_addr = 0x3a4,
.csid_rdi_timestamp_prev0_eof_addr = 0x3a8, .timestamp_prev0_eof_addr = 0x3a8,
.csid_rdi_timestamp_prev1_eof_addr = 0x3ac, .timestamp_prev1_eof_addr = 0x3ac,
.csid_rdi_byte_cntr_ping_addr = 0x3e0, .byte_cntr_ping_addr = 0x3e0,
.csid_rdi_byte_cntr_pong_addr = 0x3e4, .byte_cntr_pong_addr = 0x3e4,
.ccif_violation_en = 1, .halt_mode_internal = 0,
.halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.ccif_violation_en = 1,
.plain_fmt_shift_val = 10,
.packing_fmt_shift_val = 30,
.mipi_pack_supported = 1,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.timestamp_en_shift_val = 2,
.format_measure_en_shift_val = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x8000,
}; };
static struct cam_ife_csid_rdi_reg_offset static struct cam_ife_csid_ver1_path_reg_info
cam_ife_csid_175_200_rdi_1_reg_offset = { cam_ife_csid_175_200_rdi_1_reg_info = {
.csid_rdi_irq_status_addr = 0x50, .irq_status_addr = 0x50,
.csid_rdi_irq_mask_addr = 0x54, .irq_mask_addr = 0x54,
.csid_rdi_irq_clear_addr = 0x58, .irq_clear_addr = 0x58,
.csid_rdi_irq_set_addr = 0x5c, .irq_set_addr = 0x5c,
.csid_rdi_cfg0_addr = 0x400, .cfg0_addr = 0x400,
.csid_rdi_cfg1_addr = 0x404, .cfg1_addr = 0x404,
.csid_rdi_ctrl_addr = 0x408, .ctrl_addr = 0x408,
.csid_rdi_frm_drop_pattern_addr = 0x40c, .frm_drop_pattern_addr = 0x40c,
.csid_rdi_frm_drop_period_addr = 0x410, .frm_drop_period_addr = 0x410,
.csid_rdi_irq_subsample_pattern_addr = 0x414, .irq_subsample_pattern_addr = 0x414,
.csid_rdi_irq_subsample_period_addr = 0x418, .irq_subsample_period_addr = 0x418,
.csid_rdi_rpp_hcrop_addr = 0x41c, .hcrop_addr = 0x41c,
.csid_rdi_rpp_vcrop_addr = 0x420, .vcrop_addr = 0x420,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x424, .pix_drop_pattern_addr = 0x424,
.csid_rdi_rpp_pix_drop_period_addr = 0x428, .pix_drop_period_addr = 0x428,
.csid_rdi_rpp_line_drop_pattern_addr = 0x42c, .line_drop_pattern_addr = 0x42c,
.csid_rdi_rpp_line_drop_period_addr = 0x430, .line_drop_period_addr = 0x430,
.csid_rdi_rst_strobes_addr = 0x440, .rst_strobes_addr = 0x440,
.csid_rdi_status_addr = 0x450, .status_addr = 0x450,
.csid_rdi_misr_val0_addr = 0x454, .misr_val0_addr = 0x454,
.csid_rdi_misr_val1_addr = 0x458, .misr_val1_addr = 0x458,
.csid_rdi_misr_val2_addr = 0x45c, .misr_val2_addr = 0x45c,
.csid_rdi_misr_val3_addr = 0x460, .misr_val3_addr = 0x460,
.csid_rdi_format_measure_cfg0_addr = 0x470, .format_measure_cfg0_addr = 0x470,
.csid_rdi_format_measure_cfg1_addr = 0x474, .format_measure_cfg1_addr = 0x474,
.csid_rdi_format_measure0_addr = 0x478, .format_measure0_addr = 0x478,
.csid_rdi_format_measure1_addr = 0x47c, .format_measure1_addr = 0x47c,
.csid_rdi_format_measure2_addr = 0x480, .format_measure2_addr = 0x480,
.csid_rdi_timestamp_curr0_sof_addr = 0x490, .timestamp_curr0_sof_addr = 0x490,
.csid_rdi_timestamp_curr1_sof_addr = 0x494, .timestamp_curr1_sof_addr = 0x494,
.csid_rdi_timestamp_prev0_sof_addr = 0x498, .timestamp_prev0_sof_addr = 0x498,
.csid_rdi_timestamp_prev1_sof_addr = 0x49c, .timestamp_prev1_sof_addr = 0x49c,
.csid_rdi_timestamp_curr0_eof_addr = 0x4a0, .timestamp_curr0_eof_addr = 0x4a0,
.csid_rdi_timestamp_curr1_eof_addr = 0x4a4, .timestamp_curr1_eof_addr = 0x4a4,
.csid_rdi_timestamp_prev0_eof_addr = 0x4a8, .timestamp_prev0_eof_addr = 0x4a8,
.csid_rdi_timestamp_prev1_eof_addr = 0x4ac, .timestamp_prev1_eof_addr = 0x4ac,
.csid_rdi_byte_cntr_ping_addr = 0x4e0, .byte_cntr_ping_addr = 0x4e0,
.csid_rdi_byte_cntr_pong_addr = 0x4e4, .byte_cntr_pong_addr = 0x4e4,
.ccif_violation_en = 1, .halt_mode_internal = 0,
.halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.ccif_violation_en = 1,
.plain_fmt_shift_val = 10,
.packing_fmt_shift_val = 30,
.mipi_pack_supported = 1,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.timestamp_en_shift_val = 2,
.format_measure_en_shift_val = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x8000,
}; };
static struct cam_ife_csid_rdi_reg_offset static struct cam_ife_csid_ver1_path_reg_info
cam_ife_csid_175_200_rdi_2_reg_offset = { cam_ife_csid_175_200_rdi_2_reg_info = {
.csid_rdi_irq_status_addr = 0x60, .irq_status_addr = 0x60,
.csid_rdi_irq_mask_addr = 0x64, .irq_mask_addr = 0x64,
.csid_rdi_irq_clear_addr = 0x68, .irq_clear_addr = 0x68,
.csid_rdi_irq_set_addr = 0x6c, .irq_set_addr = 0x6c,
.csid_rdi_cfg0_addr = 0x500, .cfg0_addr = 0x500,
.csid_rdi_cfg1_addr = 0x504, .cfg1_addr = 0x504,
.csid_rdi_ctrl_addr = 0x508, .ctrl_addr = 0x508,
.csid_rdi_frm_drop_pattern_addr = 0x50c, .frm_drop_pattern_addr = 0x50c,
.csid_rdi_frm_drop_period_addr = 0x510, .frm_drop_period_addr = 0x510,
.csid_rdi_irq_subsample_pattern_addr = 0x514, .irq_subsample_pattern_addr = 0x514,
.csid_rdi_irq_subsample_period_addr = 0x518, .irq_subsample_period_addr = 0x518,
.csid_rdi_rpp_hcrop_addr = 0x51c, .hcrop_addr = 0x51c,
.csid_rdi_rpp_vcrop_addr = 0x520, .vcrop_addr = 0x520,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x524, .pix_drop_pattern_addr = 0x524,
.csid_rdi_rpp_pix_drop_period_addr = 0x528, .pix_drop_period_addr = 0x528,
.csid_rdi_rpp_line_drop_pattern_addr = 0x52c, .line_drop_pattern_addr = 0x52c,
.csid_rdi_rpp_line_drop_period_addr = 0x530, .line_drop_period_addr = 0x530,
.csid_rdi_yuv_chroma_conversion_addr = 0x534, .yuv_chroma_conversion_addr = 0x534,
.csid_rdi_rst_strobes_addr = 0x540, .rst_strobes_addr = 0x540,
.csid_rdi_status_addr = 0x550, .status_addr = 0x550,
.csid_rdi_misr_val0_addr = 0x554, .misr_val0_addr = 0x554,
.csid_rdi_misr_val1_addr = 0x558, .misr_val1_addr = 0x558,
.csid_rdi_misr_val2_addr = 0x55c, .misr_val2_addr = 0x55c,
.csid_rdi_misr_val3_addr = 0x560, .misr_val3_addr = 0x560,
.csid_rdi_format_measure_cfg0_addr = 0x570, .format_measure_cfg0_addr = 0x570,
.csid_rdi_format_measure_cfg1_addr = 0x574, .format_measure_cfg1_addr = 0x574,
.csid_rdi_format_measure0_addr = 0x578, .format_measure0_addr = 0x578,
.csid_rdi_format_measure1_addr = 0x57c, .format_measure1_addr = 0x57c,
.csid_rdi_format_measure2_addr = 0x580, .format_measure2_addr = 0x580,
.csid_rdi_timestamp_curr0_sof_addr = 0x590, .timestamp_curr0_sof_addr = 0x590,
.csid_rdi_timestamp_curr1_sof_addr = 0x594, .timestamp_curr1_sof_addr = 0x594,
.csid_rdi_timestamp_prev0_sof_addr = 0x598, .timestamp_prev0_sof_addr = 0x598,
.csid_rdi_timestamp_prev1_sof_addr = 0x59c, .timestamp_prev1_sof_addr = 0x59c,
.csid_rdi_timestamp_curr0_eof_addr = 0x5a0, .timestamp_curr0_eof_addr = 0x5a0,
.csid_rdi_timestamp_curr1_eof_addr = 0x5a4, .timestamp_curr1_eof_addr = 0x5a4,
.csid_rdi_timestamp_prev0_eof_addr = 0x5a8, .timestamp_prev0_eof_addr = 0x5a8,
.csid_rdi_timestamp_prev1_eof_addr = 0x5ac, .timestamp_prev1_eof_addr = 0x5ac,
.csid_rdi_byte_cntr_ping_addr = 0x5e0, .byte_cntr_ping_addr = 0x5e0,
.csid_rdi_byte_cntr_pong_addr = 0x5e4, .byte_cntr_pong_addr = 0x5e4,
.ccif_violation_en = 1, .halt_mode_internal = 0,
.halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.ccif_violation_en = 1,
.plain_fmt_shift_val = 10,
.mipi_pack_supported = 1,
.packing_fmt_shift_val = 30,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.timestamp_en_shift_val = 2,
.format_measure_en_shift_val = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x8000,
}; };
static struct cam_ife_csid_csi2_rx_reg_offset static struct cam_ife_csid_csi2_rx_reg_info
cam_ife_csid_175_200_csi2_reg_offset = { cam_ife_csid_175_200_csi2_reg_info = {
.csid_csi2_rx_irq_status_addr = 0x20, .irq_status_addr = 0x20,
.csid_csi2_rx_irq_mask_addr = 0x24, .irq_mask_addr = 0x24,
.csid_csi2_rx_irq_clear_addr = 0x28, .irq_clear_addr = 0x28,
.csid_csi2_rx_irq_set_addr = 0x2c, .irq_set_addr = 0x2c,
/*CSI2 rx control */ /*CSI2 rx control */
.csid_csi2_rx_cfg0_addr = 0x100, .cfg0_addr = 0x100,
.csid_csi2_rx_cfg1_addr = 0x104, .cfg1_addr = 0x104,
.csid_csi2_rx_capture_ctrl_addr = 0x108, .capture_ctrl_addr = 0x108,
.csid_csi2_rx_rst_strobes_addr = 0x110, .rst_strobes_addr = 0x110,
.csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr = 0x120, .cap_unmap_long_pkt_hdr_0_addr = 0x120,
.csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr = 0x124, .cap_unmap_long_pkt_hdr_1_addr = 0x124,
.csid_csi2_rx_captured_short_pkt_0_addr = 0x128, .captured_short_pkt_0_addr = 0x128,
.csid_csi2_rx_captured_short_pkt_1_addr = 0x12c, .captured_short_pkt_1_addr = 0x12c,
.csid_csi2_rx_captured_long_pkt_0_addr = 0x130, .captured_long_pkt_0_addr = 0x130,
.csid_csi2_rx_captured_long_pkt_1_addr = 0x134, .captured_long_pkt_1_addr = 0x134,
.csid_csi2_rx_captured_long_pkt_ftr_addr = 0x138, .captured_long_pkt_ftr_addr = 0x138,
.csid_csi2_rx_captured_cphy_pkt_hdr_addr = 0x13c, .captured_cphy_pkt_hdr_addr = 0x13c,
.csid_csi2_rx_lane0_misr_addr = 0x150, .lane0_misr_addr = 0x150,
.csid_csi2_rx_lane1_misr_addr = 0x154, .lane1_misr_addr = 0x154,
.csid_csi2_rx_lane2_misr_addr = 0x158, .lane2_misr_addr = 0x158,
.csid_csi2_rx_lane3_misr_addr = 0x15c, .lane3_misr_addr = 0x15c,
.csid_csi2_rx_total_pkts_rcvd_addr = 0x160, .total_pkts_rcvd_addr = 0x160,
.csid_csi2_rx_stats_ecc_addr = 0x164, .stats_ecc_addr = 0x164,
.csid_csi2_rx_total_crc_err_addr = 0x168, .total_crc_err_addr = 0x168,
.csid_csi2_rx_de_scramble_type3_cfg0_addr = 0x170, .de_scramble_type3_cfg0_addr = 0x170,
.csid_csi2_rx_de_scramble_type3_cfg1_addr = 0x174, .de_scramble_type3_cfg1_addr = 0x174,
.csid_csi2_rx_de_scramble_type2_cfg0_addr = 0x178, .de_scramble_type2_cfg0_addr = 0x178,
.csid_csi2_rx_de_scramble_type2_cfg1_addr = 0x17c, .de_scramble_type2_cfg1_addr = 0x17c,
.csid_csi2_rx_de_scramble_type1_cfg0_addr = 0x180, .de_scramble_type1_cfg0_addr = 0x180,
.csid_csi2_rx_de_scramble_type1_cfg1_addr = 0x184, .de_scramble_type1_cfg1_addr = 0x184,
.csid_csi2_rx_de_scramble_type0_cfg0_addr = 0x188, .de_scramble_type0_cfg0_addr = 0x188,
.csid_csi2_rx_de_scramble_type0_cfg1_addr = 0x18c, .de_scramble_type0_cfg1_addr = 0x18c,
.csi2_rst_srb_all = 0x3FFF, .rst_srb_all = 0x3FFF,
.csi2_rst_done_shift_val = 27, .rst_done_shift_val = 27,
.csi2_irq_mask_all = 0xFFFFFFF, .irq_mask_all = 0xFFFFFFF,
.csi2_misr_enable_shift_val = 6, .misr_enable_shift_val = 6,
.csi2_vc_mode_shift_val = 2, .vc_mode_shift_val = 2,
.csi2_capture_long_pkt_en_shift = 0, .capture_long_pkt_en_shift = 0,
.csi2_capture_short_pkt_en_shift = 1, .capture_short_pkt_en_shift = 1,
.csi2_capture_cphy_pkt_en_shift = 2, .capture_cphy_pkt_en_shift = 2,
.csi2_capture_long_pkt_dt_shift = 4, .capture_long_pkt_dt_shift = 4,
.csi2_capture_long_pkt_vc_shift = 10, .capture_long_pkt_vc_shift = 10,
.csi2_capture_short_pkt_vc_shift = 15, .capture_short_pkt_vc_shift = 15,
.csi2_capture_cphy_pkt_dt_shift = 20, .capture_cphy_pkt_dt_shift = 20,
.csi2_capture_cphy_pkt_vc_shift = 26, .capture_cphy_pkt_vc_shift = 26,
.csi2_rx_phy_num_mask = 0x7, .phy_num_mask = 0x7,
.vc_mask = 0x7C00000,
.dt_mask = 0x3f0000,
.wc_mask = 0xffff0000,
.calc_crc_mask = 0xffff,
.expected_crc_mask = 0xffff,
.ecc_correction_shift_en = 0,
.lane_num_shift = 0,
.lane_cfg_shift = 4,
.phy_type_shift = 24,
.phy_num_shift = 20,
.fatal_err_mask = 0x78000,
.part_fatal_err_mask = 0x1801800,
.non_fatal_err_mask = 0x380000,
}; };
static struct cam_ife_csid_csi2_tpg_reg_offset static struct cam_ife_csid_ver1_tpg_reg_info
cam_ife_csid_175_200_tpg_reg_offset = { cam_ife_csid_175_200_tpg_reg_info = {
/*CSID TPG control */ /*CSID TPG control */
.csid_tpg_ctrl_addr = 0x600, .ctrl_addr = 0x600,
.csid_tpg_vc_cfg0_addr = 0x604, .vc_cfg0_addr = 0x604,
.csid_tpg_vc_cfg1_addr = 0x608, .vc_cfg1_addr = 0x608,
.csid_tpg_lfsr_seed_addr = 0x60c, .lfsr_seed_addr = 0x60c,
.csid_tpg_dt_n_cfg_0_addr = 0x610, .dt_n_cfg_0_addr = 0x610,
.csid_tpg_dt_n_cfg_1_addr = 0x614, .dt_n_cfg_1_addr = 0x614,
.csid_tpg_dt_n_cfg_2_addr = 0x618, .dt_n_cfg_2_addr = 0x618,
.csid_tpg_color_bars_cfg_addr = 0x640, .color_bars_cfg_addr = 0x640,
.csid_tpg_color_box_cfg_addr = 0x644, .color_box_cfg_addr = 0x644,
.csid_tpg_common_gen_cfg_addr = 0x648, .common_gen_cfg_addr = 0x648,
.csid_tpg_cgen_n_cfg_addr = 0x650, .cgen_n_cfg_addr = 0x650,
.csid_tpg_cgen_n_x0_addr = 0x654, .cgen_n_x0_addr = 0x654,
.csid_tpg_cgen_n_x1_addr = 0x658, .cgen_n_x1_addr = 0x658,
.csid_tpg_cgen_n_x2_addr = 0x65c, .cgen_n_x2_addr = 0x65c,
.csid_tpg_cgen_n_xy_addr = 0x660, .cgen_n_xy_addr = 0x660,
.csid_tpg_cgen_n_y1_addr = 0x664, .cgen_n_y1_addr = 0x664,
.csid_tpg_cgen_n_y2_addr = 0x668, .cgen_n_y2_addr = 0x668,
/* configurations */ /* configurations */
.tpg_dtn_cfg_offset = 0xc, .dtn_cfg_offset = 0xc,
.tpg_cgen_cfg_offset = 0x20, .cgen_cfg_offset = 0x20,
.tpg_cpas_ife_reg_offset = 0x28, .cpas_ife_reg_offset = 0x28,
.hbi = 0x740,
.vbi = 0x3FF,
.ctrl_cfg = 0x408007,
.lfsr_seed = 0x12345678,
.color_bar = 1,
.num_frames = 0,
.line_interleave_mode = 0x1,
.payload_mode = 0x8,
.num_active_lanes_mask = 0x30,
.num_active_dt = 0,
.fmt_shift = 16,
.num_frame_shift = 16,
.width_shift = 16,
.vbi_shift = 12,
.line_interleave_shift = 10,
.num_active_dt_shift = 8,
.color_bar_shift = 5,
.height_shift = 0,
.hbi_shift = 0,
}; };
static struct cam_ife_csid_common_reg_offset static struct cam_ife_csid_ver1_common_reg_info
cam_ife_csid_175_200_cmn_reg_offset = { cam_ife_csid_175_200_cmn_reg_info = {
.csid_hw_version_addr = 0x0, .hw_version_addr = 0x0,
.csid_cfg0_addr = 0x4, .cfg0_addr = 0x4,
.csid_ctrl_addr = 0x8, .ctrl_addr = 0x8,
.csid_reset_addr = 0xc, .reset_addr = 0xc,
.csid_rst_strobes_addr = 0x10, .rst_strobes_addr = 0x10,
.test_bus_ctrl_addr = 0x14,
.csid_test_bus_ctrl_addr = 0x14, .top_irq_status_addr = 0x70,
.csid_top_irq_status_addr = 0x70, .top_irq_mask_addr = 0x74,
.csid_top_irq_mask_addr = 0x74, .top_irq_clear_addr = 0x78,
.csid_top_irq_clear_addr = 0x78, .top_irq_set_addr = 0x7c,
.csid_top_irq_set_addr = 0x7c, .irq_cmd_addr = 0x80,
.csid_irq_cmd_addr = 0x80,
/*configurations */ /*configurations */
.major_version = 1, .major_version = 1,
.minor_version = 7, .minor_version = 7,
.version_incr = 5, .version_incr = 5,
.num_rdis = 3, .num_rdis = 3,
.num_pix = 1, .num_pix = 1,
.num_ppp = 1, .num_ppp = 1,
.csid_reg_rst_stb = 1, .rst_sw_reg_stb = 1,
.csid_rst_stb = 0x1e, .rst_hw_reg_stb = 0x1e,
.csid_rst_stb_sw_all = 0x1f, .rst_sw_hw_reg_stb = 0x1f,
.path_rst_stb_all = 0x7f, .path_rst_stb_all = 0x7f,
.path_rst_done_shift_val = 1, .rst_done_shift_val = 1,
.path_en_shift_val = 31, .path_en_shift_val = 31,
.packing_fmt_shift_val = 30, .dt_id_shift_val = 27,
.dt_id_shift_val = 27, .vc_shift_val = 22,
.vc_shift_val = 22, .dt_shift_val = 16,
.dt_shift_val = 16, .fmt_shift_val = 12,
.fmt_shift_val = 12, .crop_shift_val = 16,
.plain_fmt_shit_val = 10, .decode_format_shift_val = 12,
.crop_v_en_shift_val = 6, .crop_pix_start_mask = 0x3fff,
.crop_h_en_shift_val = 5, .crop_pix_end_mask = 0xffff,
.crop_shift = 16, .crop_line_start_mask = 0x3fff,
.ipp_irq_mask_all = 0xFFFF, .crop_line_end_mask = 0xffff,
.rdi_irq_mask_all = 0xFFFF, .ipp_irq_mask_all = 0xFFFF,
.ppp_irq_mask_all = 0xFFFF, .rdi_irq_mask_all = 0xFFFF,
.measure_en_hbi_vbi_cnt_mask = 0xC, .ppp_irq_mask_all = 0xFFFF,
.format_measure_en_val = 1, .measure_en_hbi_vbi_cnt_mask = 0xC,
.format_measure_height_mask_val = 0xFFFF, .timestamp_strobe_val = 0x2,
.format_measure_height_shift_val = 0x10, .timestamp_stb_sel_shift_val = 0,
.format_measure_width_mask_val = 0xFFFF,
.format_measure_width_shift_val = 0x0,
}; };
static struct cam_ife_csid_reg_offset cam_ife_csid_175_200_reg_offset = { static struct cam_ife_csid_ver1_reg_info cam_ife_csid_175_200_reg_info = {
.cmn_reg = &cam_ife_csid_175_200_cmn_reg_offset, .cmn_reg = &cam_ife_csid_175_200_cmn_reg_info,
.csi2_reg = &cam_ife_csid_175_200_csi2_reg_offset, .csi2_reg = &cam_ife_csid_175_200_csi2_reg_info,
.ipp_reg = &cam_ife_csid_175_200_ipp_reg_offset, .ipp_reg = &cam_ife_csid_175_200_ipp_reg_info,
.ppp_reg = &cam_ife_csid_175_200_ppp_reg_offset, .ppp_reg = &cam_ife_csid_175_200_ppp_reg_info,
.rdi_reg = { .rdi_reg = {
&cam_ife_csid_175_200_rdi_0_reg_offset, &cam_ife_csid_175_200_rdi_0_reg_info,
&cam_ife_csid_175_200_rdi_1_reg_offset, &cam_ife_csid_175_200_rdi_1_reg_info,
&cam_ife_csid_175_200_rdi_2_reg_offset, &cam_ife_csid_175_200_rdi_2_reg_info,
NULL, NULL,
}, },
.tpg_reg = &cam_ife_csid_175_200_tpg_reg_offset, .tpg_reg = &cam_ife_csid_175_200_tpg_reg_info,
}; };
#endif /*_CAM_IFE_CSID_175_200_H_ */ #endif /*_CAM_IFE_CSID_175_200_H_ */

99
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid17x.c
View File

@@ -1,99 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
*/
#include <linux/module.h>
#include "cam_ife_csid_core.h"
#include "cam_ife_csid170.h"
#include "cam_ife_csid170_200.h"
#include "cam_ife_csid175.h"
#include "cam_ife_csid175_200.h"
#include "cam_ife_csid480.h"
#include "cam_ife_csid_dev.h"
#include "camera_main.h"
#define CAM_CSID_DRV_NAME "csid_17x"
#define CAM_CSID_VERSION_V170 0x10070000
#define CAM_CSID_VERSION_V175 0x10070050
#define CAM_CSID_VERSION_V480 0x40080000
static struct cam_ife_csid_hw_info cam_ife_csid170_hw_info = {
.csid_reg = &cam_ife_csid_170_reg_offset,
.hw_dts_version = CAM_CSID_VERSION_V170,
};
static struct cam_ife_csid_hw_info cam_ife_csid170_200_hw_info = {
.csid_reg = &cam_ife_csid_170_200_reg_offset,
.hw_dts_version = CAM_CSID_VERSION_V170,
};
static struct cam_ife_csid_hw_info cam_ife_csid175_hw_info = {
.csid_reg = &cam_ife_csid_175_reg_offset,
.hw_dts_version = CAM_CSID_VERSION_V175,
};
static struct cam_ife_csid_hw_info cam_ife_csid175_200_hw_info = {
.csid_reg = &cam_ife_csid_175_200_reg_offset,
.hw_dts_version = CAM_CSID_VERSION_V175,
};
static struct cam_ife_csid_hw_info cam_ife_csid480_hw_info = {
.csid_reg = &cam_ife_csid_480_reg_offset,
.hw_dts_version = CAM_CSID_VERSION_V480,
};
static const struct of_device_id cam_ife_csid17x_dt_match[] = {
{
.compatible = "qcom,csid170",
.data = &cam_ife_csid170_hw_info,
},
{
.compatible = "qcom,csid170_200",
.data = &cam_ife_csid170_200_hw_info,
},
{
.compatible = "qcom,csid175",
.data = &cam_ife_csid175_hw_info,
},
{
.compatible = "qcom,csid175_200",
.data = &cam_ife_csid175_200_hw_info,
},
{
.compatible = "qcom,csid480",
.data = &cam_ife_csid480_hw_info,
},
{
.compatible = "qcom,csid580",
.data = &cam_ife_csid480_hw_info,
},
{}
};
MODULE_DEVICE_TABLE(of, cam_ife_csid17x_dt_match);
struct platform_driver cam_ife_csid17x_driver = {
.probe = cam_ife_csid_probe,
.remove = cam_ife_csid_remove,
.driver = {
.name = CAM_CSID_DRV_NAME,
.owner = THIS_MODULE,
.of_match_table = cam_ife_csid17x_dt_match,
.suppress_bind_attrs = true,
},
};
int cam_ife_csid17x_init_module(void)
{
return platform_driver_register(&cam_ife_csid17x_driver);
}
void cam_ife_csid17x_exit_module(void)
{
platform_driver_unregister(&cam_ife_csid17x_driver);
}
MODULE_DESCRIPTION("CAM IFE_CSID17X driver");
MODULE_LICENSE("GPL v2");

827
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid480.h
View File

@@ -6,384 +6,525 @@
#ifndef _CAM_IFE_CSID_480_H_ #ifndef _CAM_IFE_CSID_480_H_
#define _CAM_IFE_CSID_480_H_ #define _CAM_IFE_CSID_480_H_
#include "cam_ife_csid_core.h" #include <linux/module.h>
#include "camera_main.h"
#include "cam_ife_csid_dev.h"
#include "cam_ife_csid_common.h"
#include "cam_ife_csid_hw_ver1.h"
static struct cam_ife_csid_pxl_reg_offset cam_ife_csid_480_ipp_reg_offset = { #define CAM_CSID_VERSION_V480 0x40080000
.csid_pxl_irq_status_addr = 0x30,
.csid_pxl_irq_mask_addr = 0x34,
.csid_pxl_irq_clear_addr = 0x38,
.csid_pxl_irq_set_addr = 0x3c,
.csid_pxl_cfg0_addr = 0x200, static struct cam_ife_csid_ver1_path_reg_info
.csid_pxl_cfg1_addr = 0x204, cam_ife_csid_480_ipp_reg_info = {
.csid_pxl_ctrl_addr = 0x208, .irq_status_addr = 0x30,
.csid_pxl_frm_drop_pattern_addr = 0x20c, .irq_mask_addr = 0x34,
.csid_pxl_frm_drop_period_addr = 0x210, .irq_clear_addr = 0x38,
.csid_pxl_irq_subsample_pattern_addr = 0x214, .irq_set_addr = 0x3c,
.csid_pxl_irq_subsample_period_addr = 0x218,
.csid_pxl_hcrop_addr = 0x21c, .cfg0_addr = 0x200,
.csid_pxl_vcrop_addr = 0x220, .cfg1_addr = 0x204,
.csid_pxl_pix_drop_pattern_addr = 0x224, .ctrl_addr = 0x208,
.csid_pxl_pix_drop_period_addr = 0x228, .frm_drop_pattern_addr = 0x20c,
.csid_pxl_line_drop_pattern_addr = 0x22c, .frm_drop_period_addr = 0x210,
.csid_pxl_line_drop_period_addr = 0x230, .irq_subsample_pattern_addr = 0x214,
.csid_pxl_rst_strobes_addr = 0x240, .irq_subsample_period_addr = 0x218,
.csid_pxl_status_addr = 0x254, .hcrop_addr = 0x21c,
.csid_pxl_misr_val_addr = 0x258, .vcrop_addr = 0x220,
.csid_pxl_format_measure_cfg0_addr = 0x270, .pix_drop_pattern_addr = 0x224,
.csid_pxl_format_measure_cfg1_addr = 0x274, .pix_drop_period_addr = 0x228,
.csid_pxl_format_measure0_addr = 0x278, .line_drop_pattern_addr = 0x22c,
.csid_pxl_format_measure1_addr = 0x27c, .line_drop_period_addr = 0x230,
.csid_pxl_format_measure2_addr = 0x280, .rst_strobes_addr = 0x240,
.csid_pxl_timestamp_curr0_sof_addr = 0x290, .status_addr = 0x254,
.csid_pxl_timestamp_curr1_sof_addr = 0x294, .misr_val_addr = 0x258,
.csid_pxl_timestamp_perv0_sof_addr = 0x298, .format_measure_cfg0_addr = 0x270,
.csid_pxl_timestamp_perv1_sof_addr = 0x29c, .format_measure_cfg1_addr = 0x274,
.csid_pxl_timestamp_curr0_eof_addr = 0x2a0, .format_measure0_addr = 0x278,
.csid_pxl_timestamp_curr1_eof_addr = 0x2a4, .format_measure1_addr = 0x27c,
.csid_pxl_timestamp_perv0_eof_addr = 0x2a8, .format_measure2_addr = 0x280,
.csid_pxl_timestamp_perv1_eof_addr = 0x2ac, .timestamp_curr0_sof_addr = 0x290,
.csid_pxl_err_recovery_cfg0_addr = 0x2d0, .timestamp_curr1_sof_addr = 0x294,
.csid_pxl_err_recovery_cfg1_addr = 0x2d4, .timestamp_prev0_sof_addr = 0x298,
.csid_pxl_err_recovery_cfg2_addr = 0x2d8, .timestamp_prev1_sof_addr = 0x29c,
.csid_pxl_multi_vcdt_cfg0_addr = 0x2dc, .timestamp_curr0_eof_addr = 0x2a0,
.timestamp_curr1_eof_addr = 0x2a4,
.timestamp_prev0_eof_addr = 0x2a8,
.timestamp_prev1_eof_addr = 0x2ac,
.err_recovery_cfg0_addr = 0x2d0,
.err_recovery_cfg1_addr = 0x2d4,
.err_recovery_cfg2_addr = 0x2d8,
.multi_vcdt_cfg0_addr = 0x2dc,
/* configurations */ /* configurations */
.pix_store_en_shift_val = 7, .pix_store_en_shift_val = 7,
.early_eof_en_shift_val = 29, .early_eof_en_shift_val = 29,
.horizontal_bin_en_shift_val = 2, .ccif_violation_en = 1,
.quad_cfa_bin_en_shift_val = 30, .overflow_ctrl_en = 1,
.ccif_violation_en = 1, //.hblank_cfg_shift_val = 4,
.overflow_ctrl_en = 1, .halt_master_sel_master_val = 0,
.hblank_cfg_shift_val = 4, .halt_master_sel_shift = 4,
.halt_mode_internal = 0,
.halt_mode_global = 1,
.halt_mode_master = 2,
.halt_mode_slave = 3,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.drop_v_en_shift_val = 4,
.drop_h_en_shift_val = 3,
.bin_h_en_shift_val = 2,
.bin_en_shift_val = 2,
.bin_qcfa_en_shift_val = 30,
.binning_supported = 0x3,
.overflow_ctrl_mode_val = 0x8,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.timestamp_en_shift_val = 1,
.format_measure_en_shift_val = 0,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x28000,
}; };
static struct cam_ife_csid_pxl_reg_offset cam_ife_csid_480_ppp_reg_offset = { static struct cam_ife_csid_ver1_path_reg_info
.csid_pxl_irq_status_addr = 0xa0, cam_ife_csid_480_ppp_reg_info = {
.csid_pxl_irq_mask_addr = 0xa4, .irq_status_addr = 0xa0,
.csid_pxl_irq_clear_addr = 0xa8, .irq_mask_addr = 0xa4,
.csid_pxl_irq_set_addr = 0xac, .irq_clear_addr = 0xa8,
.irq_set_addr = 0xac,
.csid_pxl_cfg0_addr = 0x700, .cfg0_addr = 0x700,
.csid_pxl_cfg1_addr = 0x704, .cfg1_addr = 0x704,
.csid_pxl_ctrl_addr = 0x708, .ctrl_addr = 0x708,
.csid_pxl_frm_drop_pattern_addr = 0x70c, .frm_drop_pattern_addr = 0x70c,
.csid_pxl_frm_drop_period_addr = 0x710, .frm_drop_period_addr = 0x710,
.csid_pxl_irq_subsample_pattern_addr = 0x714, .irq_subsample_pattern_addr = 0x714,
.csid_pxl_irq_subsample_period_addr = 0x718, .irq_subsample_period_addr = 0x718,
.csid_pxl_hcrop_addr = 0x71c, .hcrop_addr = 0x71c,
.csid_pxl_vcrop_addr = 0x720, .vcrop_addr = 0x720,
.csid_pxl_pix_drop_pattern_addr = 0x724, .pix_drop_pattern_addr = 0x724,
.csid_pxl_pix_drop_period_addr = 0x728, .pix_drop_period_addr = 0x728,
.csid_pxl_line_drop_pattern_addr = 0x72c, .line_drop_pattern_addr = 0x72c,
.csid_pxl_line_drop_period_addr = 0x730, .line_drop_period_addr = 0x730,
.csid_pxl_rst_strobes_addr = 0x740, .rst_strobes_addr = 0x740,
.csid_pxl_status_addr = 0x754, .status_addr = 0x754,
.csid_pxl_misr_val_addr = 0x758, .misr_val_addr = 0x758,
.csid_pxl_format_measure_cfg0_addr = 0x770, .format_measure_cfg0_addr = 0x770,
.csid_pxl_format_measure_cfg1_addr = 0x774, .format_measure_cfg1_addr = 0x774,
.csid_pxl_format_measure0_addr = 0x778, .format_measure0_addr = 0x778,
.csid_pxl_format_measure1_addr = 0x77c, .format_measure1_addr = 0x77c,
.csid_pxl_format_measure2_addr = 0x780, .format_measure2_addr = 0x780,
.csid_pxl_timestamp_curr0_sof_addr = 0x790, .timestamp_curr0_sof_addr = 0x790,
.csid_pxl_timestamp_curr1_sof_addr = 0x794, .timestamp_curr1_sof_addr = 0x794,
.csid_pxl_timestamp_perv0_sof_addr = 0x798, .timestamp_prev0_sof_addr = 0x798,
.csid_pxl_timestamp_perv1_sof_addr = 0x79c, .timestamp_prev1_sof_addr = 0x79c,
.csid_pxl_timestamp_curr0_eof_addr = 0x7a0, .timestamp_curr0_eof_addr = 0x7a0,
.csid_pxl_timestamp_curr1_eof_addr = 0x7a4, .timestamp_curr1_eof_addr = 0x7a4,
.csid_pxl_timestamp_perv0_eof_addr = 0x7a8, .timestamp_prev0_eof_addr = 0x7a8,
.csid_pxl_timestamp_perv1_eof_addr = 0x7ac, .timestamp_prev1_eof_addr = 0x7ac,
.csid_pxl_err_recovery_cfg0_addr = 0x7d0, .err_recovery_cfg0_addr = 0x7d0,
.csid_pxl_err_recovery_cfg1_addr = 0x7d4, .err_recovery_cfg1_addr = 0x7d4,
.csid_pxl_err_recovery_cfg2_addr = 0x7d8, .err_recovery_cfg2_addr = 0x7d8,
.csid_pxl_multi_vcdt_cfg0_addr = 0x7dc, .multi_vcdt_cfg0_addr = 0x7dc,
/* configurations */ /* configurations */
.pix_store_en_shift_val = 7, .halt_master_sel_master_val = 3,
.early_eof_en_shift_val = 29, .halt_master_sel_shift = 4,
.ccif_violation_en = 1, .halt_mode_internal = 0,
.overflow_ctrl_en = 1, .halt_mode_global = 1,
.halt_mode_master = 2,
.halt_mode_slave = 3,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.drop_v_en_shift_val = 4,
.drop_h_en_shift_val = 3,
.pix_store_en_shift_val = 7,
.early_eof_en_shift_val = 29,
.ccif_violation_en = 1,
.overflow_ctrl_en = 1,
.overflow_ctrl_mode_val = 0x8,
.timestamp_en_shift_val = 1,
.format_measure_en_shift_val = 0,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x28000,
}; };
static struct cam_ife_csid_ver1_path_reg_info
static struct cam_ife_csid_rdi_reg_offset cam_ife_csid_480_rdi_0_reg_offset = { cam_ife_csid_480_rdi_0_reg_info = {
.csid_rdi_irq_status_addr = 0x40, .irq_status_addr = 0x40,
.csid_rdi_irq_mask_addr = 0x44, .irq_mask_addr = 0x44,
.csid_rdi_irq_clear_addr = 0x48, .irq_clear_addr = 0x48,
.csid_rdi_irq_set_addr = 0x4c, .irq_set_addr = 0x4c,
.csid_rdi_cfg0_addr = 0x300, .cfg0_addr = 0x300,
.csid_rdi_cfg1_addr = 0x304, .cfg1_addr = 0x304,
.csid_rdi_ctrl_addr = 0x308, .ctrl_addr = 0x308,
.csid_rdi_frm_drop_pattern_addr = 0x30c, .frm_drop_pattern_addr = 0x30c,
.csid_rdi_frm_drop_period_addr = 0x310, .frm_drop_period_addr = 0x310,
.csid_rdi_irq_subsample_pattern_addr = 0x314, .irq_subsample_pattern_addr = 0x314,
.csid_rdi_irq_subsample_period_addr = 0x318, .irq_subsample_period_addr = 0x318,
.csid_rdi_rpp_hcrop_addr = 0x31c, .hcrop_addr = 0x31c,
.csid_rdi_rpp_vcrop_addr = 0x320, .vcrop_addr = 0x320,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x324, .pix_drop_pattern_addr = 0x324,
.csid_rdi_rpp_pix_drop_period_addr = 0x328, .pix_drop_period_addr = 0x328,
.csid_rdi_rpp_line_drop_pattern_addr = 0x32c, .line_drop_pattern_addr = 0x32c,
.csid_rdi_rpp_line_drop_period_addr = 0x330, .line_drop_period_addr = 0x330,
.csid_rdi_rst_strobes_addr = 0x340, .rst_strobes_addr = 0x340,
.csid_rdi_status_addr = 0x350, .status_addr = 0x350,
.csid_rdi_misr_val0_addr = 0x354, .misr_val0_addr = 0x354,
.csid_rdi_misr_val1_addr = 0x358, .misr_val1_addr = 0x358,
.csid_rdi_misr_val2_addr = 0x35c, .misr_val2_addr = 0x35c,
.csid_rdi_misr_val3_addr = 0x360, .misr_val3_addr = 0x360,
.csid_rdi_format_measure_cfg0_addr = 0x370, .format_measure_cfg0_addr = 0x370,
.csid_rdi_format_measure_cfg1_addr = 0x374, .format_measure_cfg1_addr = 0x374,
.csid_rdi_format_measure0_addr = 0x378, .format_measure0_addr = 0x378,
.csid_rdi_format_measure1_addr = 0x37c, .format_measure1_addr = 0x37c,
.csid_rdi_format_measure2_addr = 0x380, .format_measure2_addr = 0x380,
.csid_rdi_timestamp_curr0_sof_addr = 0x390, .timestamp_curr0_sof_addr = 0x390,
.csid_rdi_timestamp_curr1_sof_addr = 0x394, .timestamp_curr1_sof_addr = 0x394,
.csid_rdi_timestamp_prev0_sof_addr = 0x398, .timestamp_prev0_sof_addr = 0x398,
.csid_rdi_timestamp_prev1_sof_addr = 0x39c, .timestamp_prev1_sof_addr = 0x39c,
.csid_rdi_timestamp_curr0_eof_addr = 0x3a0, .timestamp_curr0_eof_addr = 0x3a0,
.csid_rdi_timestamp_curr1_eof_addr = 0x3a4, .timestamp_curr1_eof_addr = 0x3a4,
.csid_rdi_timestamp_prev0_eof_addr = 0x3a8, .timestamp_prev0_eof_addr = 0x3a8,
.csid_rdi_timestamp_prev1_eof_addr = 0x3ac, .timestamp_prev1_eof_addr = 0x3ac,
.csid_rdi_err_recovery_cfg0_addr = 0x3b0, .err_recovery_cfg0_addr = 0x3b0,
.csid_rdi_err_recovery_cfg1_addr = 0x3b4, .err_recovery_cfg1_addr = 0x3b4,
.csid_rdi_err_recovery_cfg2_addr = 0x3b8, .err_recovery_cfg2_addr = 0x3b8,
.csid_rdi_multi_vcdt_cfg0_addr = 0x3bc, .multi_vcdt_cfg0_addr = 0x3bc,
.csid_rdi_byte_cntr_ping_addr = 0x3e0, .byte_cntr_ping_addr = 0x3e0,
.csid_rdi_byte_cntr_pong_addr = 0x3e4, .byte_cntr_pong_addr = 0x3e4,
/* configurations */ /* configurations */
.ccif_violation_en = 1, .halt_mode_internal = 0,
.overflow_ctrl_en = 1, .halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.drop_v_en_shift_val = 4,
.drop_h_en_shift_val = 3,
.plain_fmt_shift_val = 10,
.ccif_violation_en = 1,
.overflow_ctrl_en = 1,
.overflow_ctrl_mode_val = 0x8,
.packing_fmt_shift_val = 30,
.mipi_pack_supported = 1,
.timestamp_en_shift_val = 2,
.format_measure_en_shift_val = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x28000,
}; };
static struct cam_ife_csid_rdi_reg_offset cam_ife_csid_480_rdi_1_reg_offset = { static struct cam_ife_csid_ver1_path_reg_info
.csid_rdi_irq_status_addr = 0x50, cam_ife_csid_480_rdi_1_reg_info = {
.csid_rdi_irq_mask_addr = 0x54, .irq_status_addr = 0x50,
.csid_rdi_irq_clear_addr = 0x58, .irq_mask_addr = 0x54,
.csid_rdi_irq_set_addr = 0x5c, .irq_clear_addr = 0x58,
.csid_rdi_cfg0_addr = 0x400, .irq_set_addr = 0x5c,
.csid_rdi_cfg1_addr = 0x404, .cfg0_addr = 0x400,
.csid_rdi_ctrl_addr = 0x408, .cfg1_addr = 0x404,
.csid_rdi_frm_drop_pattern_addr = 0x40c, .ctrl_addr = 0x408,
.csid_rdi_frm_drop_period_addr = 0x410, .frm_drop_pattern_addr = 0x40c,
.csid_rdi_irq_subsample_pattern_addr = 0x414, .frm_drop_period_addr = 0x410,
.csid_rdi_irq_subsample_period_addr = 0x418, .irq_subsample_pattern_addr = 0x414,
.csid_rdi_rpp_hcrop_addr = 0x41c, .irq_subsample_period_addr = 0x418,
.csid_rdi_rpp_vcrop_addr = 0x420, .hcrop_addr = 0x41c,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x424, .vcrop_addr = 0x420,
.csid_rdi_rpp_pix_drop_period_addr = 0x428, .pix_drop_pattern_addr = 0x424,
.csid_rdi_rpp_line_drop_pattern_addr = 0x42c, .pix_drop_period_addr = 0x428,
.csid_rdi_rpp_line_drop_period_addr = 0x430, .line_drop_pattern_addr = 0x42c,
.csid_rdi_rst_strobes_addr = 0x440, .line_drop_period_addr = 0x430,
.csid_rdi_status_addr = 0x450, .rst_strobes_addr = 0x440,
.csid_rdi_misr_val0_addr = 0x454, .status_addr = 0x450,
.csid_rdi_misr_val1_addr = 0x458, .misr_val0_addr = 0x454,
.csid_rdi_misr_val2_addr = 0x45c, .misr_val1_addr = 0x458,
.csid_rdi_misr_val3_addr = 0x460, .misr_val2_addr = 0x45c,
.csid_rdi_format_measure_cfg0_addr = 0x470, .misr_val3_addr = 0x460,
.csid_rdi_format_measure_cfg1_addr = 0x474, .format_measure_cfg0_addr = 0x470,
.csid_rdi_format_measure0_addr = 0x478, .format_measure_cfg1_addr = 0x474,
.csid_rdi_format_measure1_addr = 0x47c, .format_measure0_addr = 0x478,
.csid_rdi_format_measure2_addr = 0x480, .format_measure1_addr = 0x47c,
.csid_rdi_timestamp_curr0_sof_addr = 0x490, .format_measure2_addr = 0x480,
.csid_rdi_timestamp_curr1_sof_addr = 0x494, .timestamp_curr0_sof_addr = 0x490,
.csid_rdi_timestamp_prev0_sof_addr = 0x498, .timestamp_curr1_sof_addr = 0x494,
.csid_rdi_timestamp_prev1_sof_addr = 0x49c, .timestamp_prev0_sof_addr = 0x498,
.csid_rdi_timestamp_curr0_eof_addr = 0x4a0, .timestamp_prev1_sof_addr = 0x49c,
.csid_rdi_timestamp_curr1_eof_addr = 0x4a4, .timestamp_curr0_eof_addr = 0x4a0,
.csid_rdi_timestamp_prev0_eof_addr = 0x4a8, .timestamp_curr1_eof_addr = 0x4a4,
.csid_rdi_timestamp_prev1_eof_addr = 0x4ac, .timestamp_prev0_eof_addr = 0x4a8,
.csid_rdi_err_recovery_cfg0_addr = 0x4b0, .timestamp_prev1_eof_addr = 0x4ac,
.csid_rdi_err_recovery_cfg1_addr = 0x4b4, .err_recovery_cfg0_addr = 0x4b0,
.csid_rdi_err_recovery_cfg2_addr = 0x4b8, .err_recovery_cfg1_addr = 0x4b4,
.csid_rdi_multi_vcdt_cfg0_addr = 0x4bc, .err_recovery_cfg2_addr = 0x4b8,
.csid_rdi_byte_cntr_ping_addr = 0x4e0, .multi_vcdt_cfg0_addr = 0x4bc,
.csid_rdi_byte_cntr_pong_addr = 0x4e4, .byte_cntr_ping_addr = 0x4e0,
.byte_cntr_pong_addr = 0x4e4,
/* configurations */ /* configurations */
.ccif_violation_en = 1, .halt_mode_internal = 0,
.overflow_ctrl_en = 1, .halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.drop_v_en_shift_val = 4,
.drop_h_en_shift_val = 3,
.plain_fmt_shift_val = 10,
.ccif_violation_en = 1,
.overflow_ctrl_en = 1,
.overflow_ctrl_mode_val = 0x8,
.packing_fmt_shift_val = 30,
.mipi_pack_supported = 1,
.timestamp_en_shift_val = 2,
.format_measure_en_shift_val = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x28000,
}; };
static struct cam_ife_csid_rdi_reg_offset cam_ife_csid_480_rdi_2_reg_offset = { static struct cam_ife_csid_ver1_path_reg_info
.csid_rdi_irq_status_addr = 0x60, cam_ife_csid_480_rdi_2_reg_info = {
.csid_rdi_irq_mask_addr = 0x64, .irq_status_addr = 0x60,
.csid_rdi_irq_clear_addr = 0x68, .irq_mask_addr = 0x64,
.csid_rdi_irq_set_addr = 0x6c, .irq_clear_addr = 0x68,
.csid_rdi_cfg0_addr = 0x500, .irq_set_addr = 0x6c,
.csid_rdi_cfg1_addr = 0x504, .cfg0_addr = 0x500,
.csid_rdi_ctrl_addr = 0x508, .cfg1_addr = 0x504,
.csid_rdi_frm_drop_pattern_addr = 0x50c, .ctrl_addr = 0x508,
.csid_rdi_frm_drop_period_addr = 0x510, .frm_drop_pattern_addr = 0x50c,
.csid_rdi_irq_subsample_pattern_addr = 0x514, .frm_drop_period_addr = 0x510,
.csid_rdi_irq_subsample_period_addr = 0x518, .irq_subsample_pattern_addr = 0x514,
.csid_rdi_rpp_hcrop_addr = 0x51c, .irq_subsample_period_addr = 0x518,
.csid_rdi_rpp_vcrop_addr = 0x520, .hcrop_addr = 0x51c,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x524, .vcrop_addr = 0x520,
.csid_rdi_rpp_pix_drop_period_addr = 0x528, .pix_drop_pattern_addr = 0x524,
.csid_rdi_rpp_line_drop_pattern_addr = 0x52c, .pix_drop_period_addr = 0x528,
.csid_rdi_rpp_line_drop_period_addr = 0x530, .line_drop_pattern_addr = 0x52c,
.csid_rdi_yuv_chroma_conversion_addr = 0x534, .line_drop_period_addr = 0x530,
.csid_rdi_rst_strobes_addr = 0x540, .yuv_chroma_conversion_addr = 0x534,
.csid_rdi_status_addr = 0x550, .rst_strobes_addr = 0x540,
.csid_rdi_misr_val0_addr = 0x554, .status_addr = 0x550,
.csid_rdi_misr_val1_addr = 0x558, .misr_val0_addr = 0x554,
.csid_rdi_misr_val2_addr = 0x55c, .misr_val1_addr = 0x558,
.csid_rdi_misr_val3_addr = 0x560, .misr_val2_addr = 0x55c,
.csid_rdi_format_measure_cfg0_addr = 0x570, .misr_val3_addr = 0x560,
.csid_rdi_format_measure_cfg1_addr = 0x574, .format_measure_cfg0_addr = 0x570,
.csid_rdi_format_measure0_addr = 0x578, .format_measure_cfg1_addr = 0x574,
.csid_rdi_format_measure1_addr = 0x57c, .format_measure0_addr = 0x578,
.csid_rdi_format_measure2_addr = 0x580, .format_measure1_addr = 0x57c,
.csid_rdi_timestamp_curr0_sof_addr = 0x590, .format_measure2_addr = 0x580,
.csid_rdi_timestamp_curr1_sof_addr = 0x594, .timestamp_curr0_sof_addr = 0x590,
.csid_rdi_timestamp_prev0_sof_addr = 0x598, .timestamp_curr1_sof_addr = 0x594,
.csid_rdi_timestamp_prev1_sof_addr = 0x59c, .timestamp_prev0_sof_addr = 0x598,
.csid_rdi_timestamp_curr0_eof_addr = 0x5a0, .timestamp_prev1_sof_addr = 0x59c,
.csid_rdi_timestamp_curr1_eof_addr = 0x5a4, .timestamp_curr0_eof_addr = 0x5a0,
.csid_rdi_timestamp_prev0_eof_addr = 0x5a8, .timestamp_curr1_eof_addr = 0x5a4,
.csid_rdi_timestamp_prev1_eof_addr = 0x5ac, .timestamp_prev0_eof_addr = 0x5a8,
.csid_rdi_err_recovery_cfg0_addr = 0x5b0, .timestamp_prev1_eof_addr = 0x5ac,
.csid_rdi_err_recovery_cfg1_addr = 0x5b4, .err_recovery_cfg0_addr = 0x5b0,
.csid_rdi_err_recovery_cfg2_addr = 0x5b8, .err_recovery_cfg1_addr = 0x5b4,
.csid_rdi_multi_vcdt_cfg0_addr = 0x5bc, .err_recovery_cfg2_addr = 0x5b8,
.csid_rdi_byte_cntr_ping_addr = 0x5e0, .multi_vcdt_cfg0_addr = 0x5bc,
.csid_rdi_byte_cntr_pong_addr = 0x5e4, .byte_cntr_ping_addr = 0x5e0,
.byte_cntr_pong_addr = 0x5e4,
/* configurations */ /* configurations */
.ccif_violation_en = 1, .halt_mode_internal = 0,
.overflow_ctrl_en = 1, .halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.drop_v_en_shift_val = 4,
.drop_h_en_shift_val = 3,
.plain_fmt_shift_val = 10,
.ccif_violation_en = 1,
.overflow_ctrl_en = 1,
.overflow_ctrl_mode_val = 0x8,
.packing_fmt_shift_val = 30,
.mipi_pack_supported = 1,
.timestamp_en_shift_val = 2,
.format_measure_en_shift_val = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x28000,
}; };
static struct cam_ife_csid_csi2_rx_reg_offset static struct cam_ife_csid_csi2_rx_reg_info
cam_ife_csid_480_csi2_reg_offset = { cam_ife_csid_480_csi2_reg_info = {
.csid_csi2_rx_irq_status_addr = 0x20, .irq_status_addr = 0x20,
.csid_csi2_rx_irq_mask_addr = 0x24, .irq_mask_addr = 0x24,
.csid_csi2_rx_irq_clear_addr = 0x28, .irq_clear_addr = 0x28,
.csid_csi2_rx_irq_set_addr = 0x2c, .irq_set_addr = 0x2c,
/*CSI2 rx control */ /*CSI2 rx control */
.csid_csi2_rx_cfg0_addr = 0x100, .cfg0_addr = 0x100,
.csid_csi2_rx_cfg1_addr = 0x104, .cfg1_addr = 0x104,
.csid_csi2_rx_capture_ctrl_addr = 0x108, .capture_ctrl_addr = 0x108,
.csid_csi2_rx_rst_strobes_addr = 0x110, .rst_strobes_addr = 0x110,
.csid_csi2_rx_de_scramble_cfg0_addr = 0x114, .de_scramble_cfg0_addr = 0x114,
.csid_csi2_rx_de_scramble_cfg1_addr = 0x118, .de_scramble_cfg1_addr = 0x118,
.csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr = 0x120, .cap_unmap_long_pkt_hdr_0_addr = 0x120,
.csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr = 0x124, .cap_unmap_long_pkt_hdr_1_addr = 0x124,
.csid_csi2_rx_captured_short_pkt_0_addr = 0x128, .captured_short_pkt_0_addr = 0x128,
.csid_csi2_rx_captured_short_pkt_1_addr = 0x12c, .captured_short_pkt_1_addr = 0x12c,
.csid_csi2_rx_captured_long_pkt_0_addr = 0x130, .captured_long_pkt_0_addr = 0x130,
.csid_csi2_rx_captured_long_pkt_1_addr = 0x134, .captured_long_pkt_1_addr = 0x134,
.csid_csi2_rx_captured_long_pkt_ftr_addr = 0x138, .captured_long_pkt_ftr_addr = 0x138,
.csid_csi2_rx_captured_cphy_pkt_hdr_addr = 0x13c, .captured_cphy_pkt_hdr_addr = 0x13c,
.csid_csi2_rx_lane0_misr_addr = 0x150, .lane0_misr_addr = 0x150,
.csid_csi2_rx_lane1_misr_addr = 0x154, .lane1_misr_addr = 0x154,
.csid_csi2_rx_lane2_misr_addr = 0x158, .lane2_misr_addr = 0x158,
.csid_csi2_rx_lane3_misr_addr = 0x15c, .lane3_misr_addr = 0x15c,
.csid_csi2_rx_total_pkts_rcvd_addr = 0x160, .total_pkts_rcvd_addr = 0x160,
.csid_csi2_rx_stats_ecc_addr = 0x164, .stats_ecc_addr = 0x164,
.csid_csi2_rx_total_crc_err_addr = 0x168, .total_crc_err_addr = 0x168,
.csi2_rst_srb_all = 0x3FFF, .rst_srb_all = 0x3FFF,
.csi2_rst_done_shift_val = 27, .rst_done_shift_val = 27,
.csi2_irq_mask_all = 0xFFFFFFF, .irq_mask_all = 0xFFFFFFF,
.csi2_misr_enable_shift_val = 6, .misr_enable_shift_val = 6,
.csi2_vc_mode_shift_val = 2, .vc_mode_shift_val = 2,
.csi2_capture_long_pkt_en_shift = 0, .capture_long_pkt_en_shift = 0,
.csi2_capture_short_pkt_en_shift = 1, .capture_short_pkt_en_shift = 1,
.csi2_capture_cphy_pkt_en_shift = 2, .capture_cphy_pkt_en_shift = 2,
.csi2_capture_long_pkt_dt_shift = 4, .capture_long_pkt_dt_shift = 4,
.csi2_capture_long_pkt_vc_shift = 10, .capture_long_pkt_vc_shift = 10,
.csi2_capture_short_pkt_vc_shift = 15, .capture_short_pkt_vc_shift = 15,
.csi2_capture_cphy_pkt_dt_shift = 20, .capture_cphy_pkt_dt_shift = 20,
.csi2_capture_cphy_pkt_vc_shift = 26, .capture_cphy_pkt_vc_shift = 26,
.csi2_rx_phy_num_mask = 0x7, .phy_num_mask = 0x7,
.vc_mask = 0x7C00000,
.dt_mask = 0x3f0000,
.wc_mask = 0xffff0000,
.calc_crc_mask = 0xffff,
.expected_crc_mask = 0xffff,
.ecc_correction_shift_en = 0,
.lane_num_shift = 0,
.lane_cfg_shift = 4,
.phy_type_shift = 24,
.phy_num_shift = 20,
.fatal_err_mask = 0x78000,
.part_fatal_err_mask = 0x1801800,
.non_fatal_err_mask = 0x380000,
}; };
static struct cam_ife_csid_csi2_tpg_reg_offset static struct cam_ife_csid_ver1_tpg_reg_info
cam_ife_csid_480_tpg_reg_offset = { cam_ife_csid_480_tpg_reg_info = {
/*CSID TPG control */ /*CSID TPG control */
.csid_tpg_ctrl_addr = 0x600, .ctrl_addr = 0x600,
.csid_tpg_vc_cfg0_addr = 0x604, .vc_cfg0_addr = 0x604,
.csid_tpg_vc_cfg1_addr = 0x608, .vc_cfg1_addr = 0x608,
.csid_tpg_lfsr_seed_addr = 0x60c, .lfsr_seed_addr = 0x60c,
.csid_tpg_dt_n_cfg_0_addr = 0x610, .dt_n_cfg_0_addr = 0x610,
.csid_tpg_dt_n_cfg_1_addr = 0x614, .dt_n_cfg_1_addr = 0x614,
.csid_tpg_dt_n_cfg_2_addr = 0x618, .dt_n_cfg_2_addr = 0x618,
.csid_tpg_color_bars_cfg_addr = 0x640, .color_bars_cfg_addr = 0x640,
.csid_tpg_color_box_cfg_addr = 0x644, .color_box_cfg_addr = 0x644,
.csid_tpg_common_gen_cfg_addr = 0x648, .common_gen_cfg_addr = 0x648,
.csid_tpg_cgen_n_cfg_addr = 0x650, .cgen_n_cfg_addr = 0x650,
.csid_tpg_cgen_n_x0_addr = 0x654, .cgen_n_x0_addr = 0x654,
.csid_tpg_cgen_n_x1_addr = 0x658, .cgen_n_x1_addr = 0x658,
.csid_tpg_cgen_n_x2_addr = 0x65c, .cgen_n_x2_addr = 0x65c,
.csid_tpg_cgen_n_xy_addr = 0x660, .cgen_n_xy_addr = 0x660,
.csid_tpg_cgen_n_y1_addr = 0x664, .cgen_n_y1_addr = 0x664,
.csid_tpg_cgen_n_y2_addr = 0x668, .cgen_n_y2_addr = 0x668,
/* configurations */ /* configurations */
.tpg_dtn_cfg_offset = 0xc, .dtn_cfg_offset = 0xc,
.tpg_cgen_cfg_offset = 0x20, .cgen_cfg_offset = 0x20,
.tpg_cpas_ife_reg_offset = 0x28, .cpas_ife_reg_offset = 0x28,
.hbi = 0x740,
.vbi = 0x3FF,
.ctrl_cfg = 0x408007,
.lfsr_seed = 0x12345678,
.color_bar = 1,
.num_frames = 0,
.line_interleave_mode = 0x1,
.payload_mode = 0x8,
.num_active_lanes_mask = 0x30,
.num_active_dt = 0,
.fmt_shift = 16,
.num_frame_shift = 16,
.width_shift = 16,
.vbi_shift = 12,
.line_interleave_shift = 10,
.num_active_dt_shift = 8,
.color_bar_shift = 5,
.height_shift = 0,
.hbi_shift = 0,
}; };
static struct cam_ife_csid_common_reg_offset static struct cam_ife_csid_ver1_common_reg_info
cam_ife_csid_480_cmn_reg_offset = { cam_ife_csid_480_cmn_reg_info = {
.csid_hw_version_addr = 0x0, .hw_version_addr = 0x0,
.csid_cfg0_addr = 0x4, .cfg0_addr = 0x4,
.csid_ctrl_addr = 0x8, .ctrl_addr = 0x8,
.csid_reset_addr = 0xc, .reset_addr = 0xc,
.csid_rst_strobes_addr = 0x10, .rst_strobes_addr = 0x10,
.csid_test_bus_ctrl_addr = 0x14, .test_bus_ctrl_addr = 0x14,
.csid_top_irq_status_addr = 0x70, .top_irq_status_addr = 0x70,
.csid_top_irq_mask_addr = 0x74, .top_irq_mask_addr = 0x74,
.csid_top_irq_clear_addr = 0x78, .top_irq_clear_addr = 0x78,
.csid_top_irq_set_addr = 0x7c, .top_irq_set_addr = 0x7c,
.csid_irq_cmd_addr = 0x80, .irq_cmd_addr = 0x80,
/*configurations */ /*configurations */
.major_version = 1, .major_version = 1,
.minor_version = 7, .minor_version = 7,
.version_incr = 0, .version_incr = 0,
.num_rdis = 3, .num_rdis = 3,
.num_pix = 1, .num_pix = 1,
.num_ppp = 1, .num_ppp = 1,
.csid_reg_rst_stb = 1, .drop_supported = 1,
.csid_rst_stb = 0x1e, .rst_sw_reg_stb = 1,
.csid_rst_stb_sw_all = 0x1f, .rst_hw_reg_stb = 0x1e,
.path_rst_stb_all = 0x7f, .rst_sw_hw_reg_stb = 0x1f,
.path_rst_done_shift_val = 1, .path_rst_stb_all = 0x7f,
.path_en_shift_val = 31, .rst_done_shift_val = 1,
.packing_fmt_shift_val = 30, .path_en_shift_val = 31,
.dt_id_shift_val = 27, .dt_id_shift_val = 27,
.vc_shift_val = 22, .vc_shift_val = 22,
.dt_shift_val = 16, .dt_shift_val = 16,
.fmt_shift_val = 12, .fmt_shift_val = 12,
.plain_fmt_shit_val = 10, .crop_shift_val = 16,
.crop_v_en_shift_val = 6, .decode_format_shift_val = 12,
.crop_h_en_shift_val = 5, .multi_vcdt_vc1_shift_val = 2,
.drop_v_en_shift_val = 4, .multi_vcdt_dt1_shift_val = 7,
.drop_h_en_shift_val = 3, .timestamp_strobe_val = 0x2,
.crop_shift = 16, .timestamp_stb_sel_shift_val = 0,
.ipp_irq_mask_all = 0x7FFF, .multi_vcdt_en_shift_val = 0,
.rdi_irq_mask_all = 0x7FFF, .crop_pix_start_mask = 0x3fff,
.ppp_irq_mask_all = 0xFFFF, .crop_pix_end_mask = 0xffff,
.measure_en_hbi_vbi_cnt_mask = 0xC, .crop_line_start_mask = 0x3fff,
.format_measure_en_val = 1, .crop_line_end_mask = 0xffff,
.format_measure_height_mask_val = 0xFFFF, .ipp_irq_mask_all = 0x7FFF,
.format_measure_height_shift_val = 0x10, .rdi_irq_mask_all = 0x7FFF,
.format_measure_width_mask_val = 0xFFFF, .ppp_irq_mask_all = 0xFFFF,
.format_measure_width_shift_val = 0x0, .measure_en_hbi_vbi_cnt_mask = 0xC,
}; };
static struct cam_ife_csid_reg_offset cam_ife_csid_480_reg_offset = { static struct cam_ife_csid_ver1_reg_info cam_ife_csid_480_reg_info = {
.cmn_reg = &cam_ife_csid_480_cmn_reg_offset, .cmn_reg = &cam_ife_csid_480_cmn_reg_info,
.csi2_reg = &cam_ife_csid_480_csi2_reg_offset, .csi2_reg = &cam_ife_csid_480_csi2_reg_info,
.ipp_reg = &cam_ife_csid_480_ipp_reg_offset, .ipp_reg = &cam_ife_csid_480_ipp_reg_info,
.ppp_reg = &cam_ife_csid_480_ppp_reg_offset, .ppp_reg = &cam_ife_csid_480_ppp_reg_info,
.rdi_reg = { .rdi_reg = {
&cam_ife_csid_480_rdi_0_reg_offset, &cam_ife_csid_480_rdi_0_reg_info,
&cam_ife_csid_480_rdi_1_reg_offset, &cam_ife_csid_480_rdi_1_reg_info,
&cam_ife_csid_480_rdi_2_reg_offset, &cam_ife_csid_480_rdi_2_reg_info,
NULL, NULL,
}, },
.tpg_reg = &cam_ife_csid_480_tpg_reg_offset, .tpg_reg = &cam_ife_csid_480_tpg_reg_info,
.csid_cust_node_map = {0x2, 0x4},
}; };
#endif /*_CAM_IFE_CSID_480_H_ */ #endif /*_CAM_IFE_CSID_480_H_ */

33
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid580.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
*/
#ifndef _CAM_IFE_CSID_580_H_
#define _CAM_IFE_CSID_580_H_
#include <linux/module.h>
#include "camera_main.h"
#include "cam_ife_csid_dev.h"
#include "cam_ife_csid_common.h"
#include "cam_ife_csid_hw_ver1.h"
/* Settings for 580 CSID are leveraged from 480 */
static struct cam_ife_csid_ver1_reg_info cam_ife_csid_580_reg_info = {
.cmn_reg = &cam_ife_csid_480_cmn_reg_info,
.csi2_reg = &cam_ife_csid_480_csi2_reg_info,
.ipp_reg = &cam_ife_csid_480_ipp_reg_info,
.ppp_reg = &cam_ife_csid_480_ppp_reg_info,
.rdi_reg = {
&cam_ife_csid_480_rdi_0_reg_info,
&cam_ife_csid_480_rdi_1_reg_info,
&cam_ife_csid_480_rdi_2_reg_info,
NULL,
},
.tpg_reg = &cam_ife_csid_480_tpg_reg_info,
.csid_cust_node_map = {0x2, 0x4},
.width_fuse_max_val = 3,
.fused_max_width = {5612, 6048, 7308, UINT_MAX},
};
#endif /*_CAM_IFE_CSID_580_H_ */

978
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid680.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef _CAM_IFE_CSID_680_H_
#define _CAM_IFE_CSID_680_H_
#include <linux/module.h>
#include "cam_ife_csid_dev.h"
#include "camera_main.h"
#include "cam_ife_csid_common.h"
#include "cam_ife_csid_hw_ver2.h"
#include "cam_irq_controller.h"
#define CAM_CSID_VERSION_V680 0x60080000
static struct cam_irq_register_set cam_ife_csid_680_irq_reg_set[9] = {
/* Top */
{
.mask_reg_offset = 0x00000080,
.clear_reg_offset = 0x00000084,
.status_reg_offset = 0x0000007C,
},
/* RX */
{
.mask_reg_offset = 0x000000A0,
.clear_reg_offset = 0x000000A4,
.status_reg_offset = 0x0000009C,
},
/* RDI0 */
{
.mask_reg_offset = 0x000000F0,
.clear_reg_offset = 0x000000F4,
.status_reg_offset = 0x000000EC,
},
/* RDI1 */
{
.mask_reg_offset = 0x00000100,
.clear_reg_offset = 0x00000104,
.status_reg_offset = 0x000000FC,
},
/* RDI2 */
{
.mask_reg_offset = 0x00000110,
.clear_reg_offset = 0x00000114,
.status_reg_offset = 0x0000010C,
},
/* RDI3 */
{
.mask_reg_offset = 0x00000120,
.clear_reg_offset = 0x00000124,
.status_reg_offset = 0x0000011C,
},
/* RDI4 */
{
.mask_reg_offset = 0x00000130,
.clear_reg_offset = 0x00000134,
.status_reg_offset = 0x0000012C,
},
/* IPP */
{
.mask_reg_offset = 0x000000B0,
.clear_reg_offset = 0x000000B4,
.status_reg_offset = 0x000000AC,
},
/* PPP */
{
.mask_reg_offset = 0x000000D0,
.clear_reg_offset = 0x000000D4,
.status_reg_offset = 0x000000CC,
},
};
static struct cam_irq_controller_reg_info cam_ife_csid_680_irq_reg_info = {
.num_registers = 9,
.irq_reg_set = cam_ife_csid_680_irq_reg_set,
.global_clear_offset = 0x00000014,
.global_clear_bitmask = 0x00000001,
};
static struct cam_irq_register_set cam_ife_csid_680_buf_done_irq_reg_set[9] = {
{
.mask_reg_offset = 0x00000090,
.clear_reg_offset = 0x00000094,
.status_reg_offset = 0x0000008C,
},
};
static struct cam_irq_controller_reg_info
cam_ife_csid_680_buf_done_irq_reg_info = {
.num_registers = 1,
.irq_reg_set = cam_ife_csid_680_buf_done_irq_reg_set,
.global_clear_offset = 0x00000014,
.global_clear_bitmask = 0x00000001,
};
static struct cam_ife_csid_ver2_pxl_reg_info
cam_ife_csid_680_ipp_reg_info = {
.irq_status_addr = 0xAC,
.irq_mask_addr = 0xB0,
.irq_clear_addr = 0xB4,
.irq_set_addr = 0xB8,
.cfg0_addr = 0x300,
.ctrl_addr = 0x304,
.debug_clr_cmd_addr = 0x308,
.multi_vcdt_cfg0_addr = 0x30c,
.cfg1_addr = 0x310,
.err_recovery_cfg0_addr = 0x318,
.err_recovery_cfg1_addr = 0x31C,
.err_recovery_cfg2_addr = 0x320,
.bin_pd_detect_cfg0_addr = 0x324,
.bin_pd_detect_cfg1_addr = 0x328,
.bin_pd_detect_cfg2_addr = 0x32C,
.camif_frame_cfg_addr = 0x330,
.epoch_irq_cfg_addr = 0x334,
.epoch0_subsample_ptrn_addr = 0x338,
.epoch1_subsample_ptrn_addr = 0x33C,
.debug_camif_1_addr = 0x340,
.debug_camif_0_addr = 0x344,
.debug_halt_status_addr = 0x348,
.debug_misr_val0_addr = 0x34C,
.debug_misr_val1_addr = 0x350,
.debug_misr_val2_addr = 0x354,
.debug_misr_val3_addr = 0x358,
.hcrop_addr = 0x35c,
.vcrop_addr = 0x360,
.pix_drop_pattern_addr = 0x364,
.pix_drop_period_addr = 0x368,
.line_drop_pattern_addr = 0x36C,
.line_drop_period_addr = 0x370,
.frm_drop_pattern_addr = 0x374,
.frm_drop_period_addr = 0x378,
.irq_subsample_pattern_addr = 0x37C,
.irq_subsample_period_addr = 0x380,
.format_measure_cfg0_addr = 0x384,
.format_measure_cfg1_addr = 0x388,
.format_measure0_addr = 0x38C,
.format_measure1_addr = 0x390,
.format_measure2_addr = 0x394,
.timestamp_curr0_sof_addr = 0x398,
.timestamp_curr1_sof_addr = 0x39C,
.timestamp_perv0_sof_addr = 0x3A0,
.timestamp_perv1_sof_addr = 0x3A4,
.timestamp_curr0_eof_addr = 0x3A8,
.timestamp_curr1_eof_addr = 0x3AC,
.timestamp_perv0_eof_addr = 0x3B0,
.timestamp_perv1_eof_addr = 0x3B4,
.lut_bank_cfg_addr = 0x3B8,
.batch_id_cfg0_addr = 0x3BC,
.batch_id_cfg1_addr = 0x3C0,
.batch_period_cfg_addr = 0x3C4,
.batch_stream_id_cfg_addr = 0x3C8,
.epoch0_cfg_batch_id0_addr = 0x3CC,
.epoch1_cfg_batch_id0_addr = 0x3D0,
.epoch0_cfg_batch_id1_addr = 0x3D4,
.epoch1_cfg_batch_id1_addr = 0x3D8,
.epoch0_cfg_batch_id2_addr = 0x3DC,
.epoch1_cfg_batch_id2_addr = 0x3E0,
.epoch0_cfg_batch_id3_addr = 0x3E4,
.epoch1_cfg_batch_id3_addr = 0x3E8,
.epoch0_cfg_batch_id4_addr = 0x3EC,
.epoch1_cfg_batch_id4_addr = 0x3F0,
.epoch0_cfg_batch_id5_addr = 0x3F4,
.epoch1_cfg_batch_id5_addr = 0x3F8,
/* configurations */
.resume_frame_boundary = 1,
.binning_supported = 0x7,
.start_mode_internal = 0x0,
.start_mode_global = 0x1,
.start_mode_master = 0x2,
.start_mode_slave = 0x3,
.start_mode_shift = 2,
.start_master_sel_val = 0,
.start_master_sel_shift = 4,
.crop_v_en_shift_val = 13,
.crop_h_en_shift_val = 12,
.drop_v_en_shift_val = 11,
.drop_h_en_shift_val = 10,
.pix_store_en_shift_val = 14,
.early_eof_en_shift_val = 16,
.bin_h_en_shift_val = 20,
.bin_v_en_shift_val = 21,
.bin_en_shift_val = 18,
.bin_qcfa_en_shift_val = 19,
.format_measure_en_shift_val = 8,
.timestamp_en_shift_val = 9,
.overflow_ctrl_en = 1,
.overflow_ctrl_mode_val = 0x8,
.min_hbi_shift_val = 4,
.start_master_sel_shift_val = 4,
.bin_pd_en_shift_val = 0,
.bin_pd_blk_w_shift_val = 8,
.bin_pd_blk_h_shift_val = 24,
.bin_pd_detect_x_offset_shift_val = 0,
.bin_pd_detect_x_end_shift_val = 16,
.bin_pd_detect_y_offset_shift_val = 0,
.bin_pd_detect_y_end_shift_val = 16,
.pix_pattern_shift_val = 24,
.stripe_loc_shift_val = 20,
.lut_bank_0_sel_val = 0,
.lut_bank_1_sel_val = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x28000,
.camif_irq_mask = 0x800000,
.rup_aup_mask = 0x10001,
};
static struct cam_ife_csid_ver2_pxl_reg_info
cam_ife_csid_680_ppp_reg_info = {
.irq_status_addr = 0xCC,
.irq_mask_addr = 0xD0,
.irq_clear_addr = 0xD4,
.irq_set_addr = 0xD8,
.cfg0_addr = 0xB00,
.ctrl_addr = 0xB04,
.debug_clr_cmd_addr = 0xB08,
.multi_vcdt_cfg0_addr = 0xB0c,
.cfg1_addr = 0xB10,
.sparse_pd_extractor_cfg_addr = 0xB14,
.err_recovery_cfg0_addr = 0xB18,
.err_recovery_cfg1_addr = 0xB1C,
.err_recovery_cfg2_addr = 0xB20,
.camif_frame_cfg_addr = 0xB30,
.epoch_irq_cfg_addr = 0xB34,
.epoch0_subsample_ptrn_addr = 0xB38,
.epoch1_subsample_ptrn_addr = 0xB3C,
.debug_camif_1_addr = 0xB40,
.debug_camif_0_addr = 0xB44,
.debug_halt_status_addr = 0xB48,
.debug_misr_val0_addr = 0xB4C,
.debug_misr_val1_addr = 0xB50,
.debug_misr_val2_addr = 0xB54,
.debug_misr_val3_addr = 0xB58,
.hcrop_addr = 0xB5c,
.vcrop_addr = 0xB60,
.pix_drop_pattern_addr = 0xB64,
.pix_drop_period_addr = 0xB68,
.line_drop_pattern_addr = 0xB6C,
.line_drop_period_addr = 0xB70,
.frm_drop_pattern_addr = 0xB74,
.frm_drop_period_addr = 0xB78,
.irq_subsample_pattern_addr = 0xB7C,
.irq_subsample_period_addr = 0xB80,
.format_measure_cfg0_addr = 0xB84,
.format_measure_cfg1_addr = 0xB88,
.format_measure0_addr = 0xB8C,
.format_measure1_addr = 0xB90,
.format_measure2_addr = 0xB94,
.timestamp_curr0_sof_addr = 0xB98,
.timestamp_curr1_sof_addr = 0xB9C,
.timestamp_perv0_sof_addr = 0xBA0,
.timestamp_perv1_sof_addr = 0xBA4,
.timestamp_curr0_eof_addr = 0xBA8,
.timestamp_curr1_eof_addr = 0xBAC,
.timestamp_perv0_eof_addr = 0xBB0,
.timestamp_perv1_eof_addr = 0xBB4,
.lut_bank_cfg_addr = 0xBB8,
.batch_id_cfg0_addr = 0xBBC,
.batch_id_cfg1_addr = 0xBC0,
.batch_period_cfg_addr = 0xBC4,
.batch_stream_id_cfg_addr = 0xBC8,
.epoch0_cfg_batch_id0_addr = 0xBCC,
.epoch1_cfg_batch_id0_addr = 0xBD0,
.epoch0_cfg_batch_id1_addr = 0xBD4,
.epoch1_cfg_batch_id1_addr = 0xBD8,
.epoch0_cfg_batch_id2_addr = 0xBDC,
.epoch1_cfg_batch_id2_addr = 0xBE0,
.epoch0_cfg_batch_id3_addr = 0xBE4,
.epoch1_cfg_batch_id3_addr = 0xBE8,
.epoch0_cfg_batch_id4_addr = 0xBEC,
.epoch1_cfg_batch_id4_addr = 0xBF0,
.epoch0_cfg_batch_id5_addr = 0xBF4,
.epoch1_cfg_batch_id5_addr = 0xBF8,
/* configurations */
.resume_frame_boundary = 1,
.start_mode_shift = 2,
.start_mode_internal = 0x0,
.start_mode_global = 0x1,
.start_mode_master = 0x2,
.start_mode_slave = 0x3,
.start_master_sel_val = 3,
.start_master_sel_shift = 4,
.binning_supported = 0x1,
.bin_h_en_shift_val = 18,
.bin_en_shift_val = 18,
.early_eof_en_shift_val = 16,
.pix_store_en_shift_val = 14,
.crop_v_en_shift_val = 13,
.crop_h_en_shift_val = 12,
.drop_v_en_shift_val = 11,
.drop_h_en_shift_val = 10,
.format_measure_en_shift_val = 8,
.timestamp_en_shift_val = 9,
.min_hbi_shift_val = 4,
.start_master_sel_shift_val = 4,
.lut_bank_0_sel_val = 0,
.lut_bank_1_sel_val = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x28000,
.rup_aup_mask = 0x40004,
};
static struct cam_ife_csid_ver2_rdi_reg_info
cam_ife_csid_680_rdi_0_reg_info = {
.irq_status_addr = 0xEC,
.irq_mask_addr = 0xF0,
.irq_clear_addr = 0xF4,
.irq_set_addr = 0xF8,
.cfg0_addr = 0x500,
.ctrl_addr = 0x504,
.debug_clr_cmd_addr = 0x508,
.multi_vcdt_cfg0_addr = 0x50c,
.cfg1_addr = 0x510,
.err_recovery_cfg0_addr = 0x514,
.err_recovery_cfg1_addr = 0x518,
.err_recovery_cfg2_addr = 0x51C,
.debug_byte_cntr_ping_addr = 0x520,
.debug_byte_cntr_pong_addr = 0x524,
.camif_frame_cfg_addr = 0x528,
.epoch_irq_cfg_addr = 0x52C,
.epoch0_subsample_ptrn_addr = 0x530,
.epoch1_subsample_ptrn_addr = 0x534,
.debug_camif_1_addr = 0x538,
.debug_camif_0_addr = 0x53C,
.frm_drop_pattern_addr = 0x540,
.frm_drop_period_addr = 0x540,
.irq_subsample_pattern_addr = 0x548,
.irq_subsample_period_addr = 0x54C,
.hcrop_addr = 0x550,
.vcrop_addr = 0x554,
.pix_drop_pattern_addr = 0x558,
.pix_drop_period_addr = 0x55C,
.line_drop_pattern_addr = 0x560,
.line_drop_period_addr = 0x564,
.debug_halt_status_addr = 0x568,
.debug_misr_val0_addr = 0x570,
.debug_misr_val1_addr = 0x574,
.debug_misr_val2_addr = 0x578,
.debug_misr_val3_addr = 0x57C,
.format_measure_cfg0_addr = 0x580,
.format_measure_cfg1_addr = 0x584,
.format_measure0_addr = 0x588,
.format_measure1_addr = 0x58C,
.format_measure2_addr = 0x590,
.timestamp_curr0_sof_addr = 0x594,
.timestamp_curr1_sof_addr = 0x598,
.timestamp_perv0_sof_addr = 0x59C,
.timestamp_perv1_sof_addr = 0x5A0,
.timestamp_curr0_eof_addr = 0x5A4,
.timestamp_curr1_eof_addr = 0x5A8,
.timestamp_perv0_eof_addr = 0x5AC,
.timestamp_perv1_eof_addr = 0x5B0,
.batch_id_cfg0_addr = 0x5B4,
.batch_id_cfg1_addr = 0x5B8,
.batch_period_cfg_addr = 0x5BC,
.batch_stream_id_cfg_addr = 0x5C0,
.epoch0_cfg_batch_id0_addr = 0x5C4,
.epoch1_cfg_batch_id0_addr = 0x5C8,
.epoch0_cfg_batch_id1_addr = 0x5CC,
.epoch1_cfg_batch_id1_addr = 0x5D0,
.epoch0_cfg_batch_id2_addr = 0x5D4,
.epoch1_cfg_batch_id2_addr = 0x5D8,
.epoch0_cfg_batch_id3_addr = 0x5DC,
.epoch1_cfg_batch_id3_addr = 0x5E0,
.epoch0_cfg_batch_id4_addr = 0x5E4,
.epoch1_cfg_batch_id4_addr = 0x5E8,
.epoch0_cfg_batch_id5_addr = 0x5EC,
.epoch1_cfg_batch_id5_addr = 0x5F0,
/* configurations */
.resume_frame_boundary = 1,
.overflow_ctrl_en = 1,
.overflow_ctrl_mode_val = 0x8,
.offline_mode_supported = 1,
.mipi_pack_supported = 1,
.packing_fmt_shift_val = 15,
.plain_alignment_shift_val = 11,
.plain_fmt_shift_val = 12,
.crop_v_en_shift_val = 8,
.crop_h_en_shift_val = 7,
.drop_v_en_shift_val = 6,
.drop_h_en_shift_val = 5,
.early_eof_en_shift_val = 14,
.format_measure_en_shift_val = 3,
.timestamp_en_shift_val = 4,
.debug_byte_cntr_rst_shift_val = 2,
.offline_mode_en_shift_val = 2,
.pix_pattern_shift_val = 24,
.stripe_loc_shift_val = 20,
.ccif_violation_en = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x28000,
.camif_irq_mask = 0x800000,
.rup_aup_mask = 0x100010,
};
static struct cam_ife_csid_ver2_rdi_reg_info
cam_ife_csid_680_rdi_1_reg_info = {
.irq_status_addr = 0xFC,
.irq_mask_addr = 0x100,
.irq_clear_addr = 0x104,
.irq_set_addr = 0x108,
.cfg0_addr = 0x600,
.ctrl_addr = 0x604,
.debug_clr_cmd_addr = 0x608,
.multi_vcdt_cfg0_addr = 0x60c,
.cfg1_addr = 0x610,
.err_recovery_cfg0_addr = 0x614,
.err_recovery_cfg1_addr = 0x618,
.err_recovery_cfg2_addr = 0x61C,
.debug_byte_cntr_ping_addr = 0x620,
.debug_byte_cntr_pong_addr = 0x624,
.camif_frame_cfg_addr = 0x628,
.epoch_irq_cfg_addr = 0x62C,
.epoch0_subsample_ptrn_addr = 0x630,
.epoch1_subsample_ptrn_addr = 0x634,
.debug_camif_1_addr = 0x638,
.debug_camif_0_addr = 0x63C,
.frm_drop_pattern_addr = 0x640,
.frm_drop_period_addr = 0x644,
.irq_subsample_pattern_addr = 0x648,
.irq_subsample_period_addr = 0x64C,
.hcrop_addr = 0x650,
.vcrop_addr = 0x654,
.pix_drop_pattern_addr = 0x658,
.pix_drop_period_addr = 0x65C,
.line_drop_pattern_addr = 0x660,
.line_drop_period_addr = 0x664,
.debug_halt_status_addr = 0x66C,
.debug_misr_val0_addr = 0x670,
.debug_misr_val1_addr = 0x674,
.debug_misr_val2_addr = 0x678,
.debug_misr_val3_addr = 0x67C,
.format_measure_cfg0_addr = 0x680,
.format_measure_cfg1_addr = 0x684,
.format_measure0_addr = 0x688,
.format_measure1_addr = 0x68C,
.format_measure2_addr = 0x690,
.timestamp_curr0_sof_addr = 0x694,
.timestamp_curr1_sof_addr = 0x698,
.timestamp_perv0_sof_addr = 0x69C,
.timestamp_perv1_sof_addr = 0x6A0,
.timestamp_curr0_eof_addr = 0x6A4,
.timestamp_curr1_eof_addr = 0x6A8,
.timestamp_perv0_eof_addr = 0x6AC,
.timestamp_perv1_eof_addr = 0x6B0,
.batch_id_cfg0_addr = 0x6B4,
.batch_id_cfg1_addr = 0x6B8,
.batch_period_cfg_addr = 0x6BC,
.batch_stream_id_cfg_addr = 0x6C0,
.epoch0_cfg_batch_id0_addr = 0x6C4,
.epoch1_cfg_batch_id0_addr = 0x6C8,
.epoch0_cfg_batch_id1_addr = 0x6CC,
.epoch1_cfg_batch_id1_addr = 0x6D0,
.epoch0_cfg_batch_id2_addr = 0x6D4,
.epoch1_cfg_batch_id2_addr = 0x6D8,
.epoch0_cfg_batch_id3_addr = 0x6DC,
.epoch1_cfg_batch_id3_addr = 0x6E0,
.epoch0_cfg_batch_id4_addr = 0x6E4,
.epoch1_cfg_batch_id4_addr = 0x6E8,
.epoch0_cfg_batch_id5_addr = 0x6EC,
.epoch1_cfg_batch_id5_addr = 0x6F0,
/* configurations */
.resume_frame_boundary = 1,
.overflow_ctrl_en = 1,
.overflow_ctrl_mode_val = 0x8,
.offline_mode_supported = 1,
.packing_fmt_shift_val = 15,
.plain_alignment_shift_val = 11,
.plain_fmt_shift_val = 12,
.crop_v_en_shift_val = 8,
.crop_h_en_shift_val = 7,
.drop_v_en_shift_val = 6,
.drop_h_en_shift_val = 5,
.early_eof_en_shift_val = 14,
.format_measure_en_shift_val = 3,
.timestamp_en_shift_val = 4,
.debug_byte_cntr_rst_shift_val = 2,
.offline_mode_en_shift_val = 2,
.pix_pattern_shift_val = 24,
.stripe_loc_shift_val = 20,
.ccif_violation_en = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x28000,
.camif_irq_mask = 0x800000,
.rup_aup_mask = 0x200020,
};
static struct cam_ife_csid_ver2_rdi_reg_info
cam_ife_csid_680_rdi_2_reg_info = {
.irq_status_addr = 0x10C,
.irq_mask_addr = 0x110,
.irq_clear_addr = 0x114,
.irq_set_addr = 0x118,
.cfg0_addr = 0x700,
.ctrl_addr = 0x704,
.debug_clr_cmd_addr = 0x708,
.multi_vcdt_cfg0_addr = 0x70c,
.cfg1_addr = 0x710,
.err_recovery_cfg0_addr = 0x714,
.err_recovery_cfg1_addr = 0x718,
.err_recovery_cfg2_addr = 0x71C,
.debug_byte_cntr_ping_addr = 0x720,
.debug_byte_cntr_pong_addr = 0x724,
.camif_frame_cfg_addr = 0x728,
.epoch_irq_cfg_addr = 0x72C,
.epoch0_subsample_ptrn_addr = 0x730,
.epoch1_subsample_ptrn_addr = 0x734,
.debug_camif_1_addr = 0x738,
.debug_camif_0_addr = 0x73C,
.frm_drop_pattern_addr = 0x740,
.frm_drop_period_addr = 0x744,
.irq_subsample_pattern_addr = 0x748,
.irq_subsample_period_addr = 0x74C,
.hcrop_addr = 0x750,
.vcrop_addr = 0x754,
.pix_drop_pattern_addr = 0x758,
.pix_drop_period_addr = 0x75C,
.line_drop_pattern_addr = 0x760,
.line_drop_period_addr = 0x764,
.debug_halt_status_addr = 0x76C,
.debug_misr_val0_addr = 0x770,
.debug_misr_val1_addr = 0x774,
.debug_misr_val2_addr = 0x778,
.debug_misr_val3_addr = 0x77C,
.format_measure_cfg0_addr = 0x780,
.format_measure_cfg1_addr = 0x784,
.format_measure0_addr = 0x788,
.format_measure1_addr = 0x78C,
.format_measure2_addr = 0x790,
.timestamp_curr0_sof_addr = 0x794,
.timestamp_curr1_sof_addr = 0x798,
.timestamp_perv0_sof_addr = 0x79C,
.timestamp_perv1_sof_addr = 0x7A0,
.timestamp_curr0_eof_addr = 0x7A4,
.timestamp_curr1_eof_addr = 0x7A8,
.timestamp_perv0_eof_addr = 0x7AC,
.timestamp_perv1_eof_addr = 0x7B0,
.batch_id_cfg0_addr = 0x7B4,
.batch_id_cfg1_addr = 0x7B8,
.batch_period_cfg_addr = 0x7BC,
.batch_stream_id_cfg_addr = 0x7C0,
.epoch0_cfg_batch_id0_addr = 0x7C4,
.epoch1_cfg_batch_id0_addr = 0x7C8,
.epoch0_cfg_batch_id1_addr = 0x7CC,
.epoch1_cfg_batch_id1_addr = 0x7D0,
.epoch0_cfg_batch_id2_addr = 0x7D4,
.epoch1_cfg_batch_id2_addr = 0x7D8,
.epoch0_cfg_batch_id3_addr = 0x7DC,
.epoch1_cfg_batch_id3_addr = 0x7E0,
.epoch0_cfg_batch_id4_addr = 0x7E4,
.epoch1_cfg_batch_id4_addr = 0x7E8,
.epoch0_cfg_batch_id5_addr = 0x7EC,
.epoch1_cfg_batch_id5_addr = 0x7F0,
/* configurations */
.resume_frame_boundary = 1,
.overflow_ctrl_en = 1,
.overflow_ctrl_mode_val = 0x8,
.offline_mode_supported = 1,
.packing_fmt_shift_val = 15,
.plain_alignment_shift_val = 11,
.plain_fmt_shift_val = 12,
.crop_v_en_shift_val = 8,
.crop_h_en_shift_val = 7,
.drop_v_en_shift_val = 6,
.drop_h_en_shift_val = 5,
.early_eof_en_shift_val = 14,
.format_measure_en_shift_val = 3,
.timestamp_en_shift_val = 4,
.debug_byte_cntr_rst_shift_val = 2,
.offline_mode_en_shift_val = 2,
.pix_pattern_shift_val = 24,
.stripe_loc_shift_val = 20,
.ccif_violation_en = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x28000,
.camif_irq_mask = 0x800000,
.rup_aup_mask = 0x400040,
};
static struct cam_ife_csid_ver2_rdi_reg_info
cam_ife_csid_680_rdi_3_reg_info = {
.irq_status_addr = 0x11C,
.irq_mask_addr = 0x120,
.irq_clear_addr = 0x124,
.irq_set_addr = 0x128,
.cfg0_addr = 0x800,
.ctrl_addr = 0x804,
.debug_clr_cmd_addr = 0x808,
.multi_vcdt_cfg0_addr = 0x80c,
.cfg1_addr = 0x810,
.err_recovery_cfg0_addr = 0x814,
.err_recovery_cfg1_addr = 0x818,
.err_recovery_cfg2_addr = 0x81C,
.debug_byte_cntr_ping_addr = 0x820,
.debug_byte_cntr_pong_addr = 0x824,
.camif_frame_cfg_addr = 0x828,
.epoch_irq_cfg_addr = 0x82C,
.epoch0_subsample_ptrn_addr = 0x830,
.epoch1_subsample_ptrn_addr = 0x834,
.debug_camif_1_addr = 0x838,
.debug_camif_0_addr = 0x83C,
.frm_drop_pattern_addr = 0x840,
.frm_drop_period_addr = 0x840,
.irq_subsample_pattern_addr = 0x848,
.irq_subsample_period_addr = 0x84C,
.hcrop_addr = 0x850,
.vcrop_addr = 0x854,
.pix_drop_pattern_addr = 0x858,
.pix_drop_period_addr = 0x85C,
.line_drop_pattern_addr = 0x860,
.line_drop_period_addr = 0x864,
.debug_halt_status_addr = 0x868,
.debug_misr_val0_addr = 0x870,
.debug_misr_val1_addr = 0x874,
.debug_misr_val2_addr = 0x878,
.debug_misr_val3_addr = 0x87C,
.format_measure_cfg0_addr = 0x880,
.format_measure_cfg1_addr = 0x884,
.format_measure0_addr = 0x888,
.format_measure1_addr = 0x88C,
.format_measure2_addr = 0x890,
.timestamp_curr0_sof_addr = 0x894,
.timestamp_curr1_sof_addr = 0x898,
.timestamp_perv0_sof_addr = 0x89C,
.timestamp_perv1_sof_addr = 0x8A0,
.timestamp_curr0_eof_addr = 0x8A4,
.timestamp_curr1_eof_addr = 0x8A8,
.timestamp_perv0_eof_addr = 0x8AC,
.timestamp_perv1_eof_addr = 0x8B0,
.batch_id_cfg0_addr = 0x8B4,
.batch_id_cfg1_addr = 0x8B8,
.batch_period_cfg_addr = 0x8BC,
.batch_stream_id_cfg_addr = 0x8C0,
.epoch0_cfg_batch_id0_addr = 0x8C4,
.epoch1_cfg_batch_id0_addr = 0x8C8,
.epoch0_cfg_batch_id1_addr = 0x8CC,
.epoch1_cfg_batch_id1_addr = 0x8D0,
.epoch0_cfg_batch_id2_addr = 0x8D4,
.epoch1_cfg_batch_id2_addr = 0x8D8,
.epoch0_cfg_batch_id3_addr = 0x8DC,
.epoch1_cfg_batch_id3_addr = 0x8E0,
.epoch0_cfg_batch_id4_addr = 0x8E4,
.epoch1_cfg_batch_id4_addr = 0x8E8,
.epoch0_cfg_batch_id5_addr = 0x8EC,
.epoch1_cfg_batch_id5_addr = 0x8F0,
/* configurations */
.resume_frame_boundary = 1,
.overflow_ctrl_en = 1,
.overflow_ctrl_mode_val = 0x8,
.offline_mode_supported = 1,
.packing_fmt_shift_val = 15,
.plain_alignment_shift_val = 11,
.plain_fmt_shift_val = 12,
.crop_v_en_shift_val = 8,
.crop_h_en_shift_val = 7,
.drop_v_en_shift_val = 6,
.drop_h_en_shift_val = 5,
.early_eof_en_shift_val = 14,
.format_measure_en_shift_val = 3,
.timestamp_en_shift_val = 4,
.debug_byte_cntr_rst_shift_val = 2,
.offline_mode_en_shift_val = 2,
.pix_pattern_shift_val = 24,
.stripe_loc_shift_val = 20,
.ccif_violation_en = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x28000,
.camif_irq_mask = 0x800000,
.rup_aup_mask = 0x800080,
};
static struct cam_ife_csid_ver2_rdi_reg_info
cam_ife_csid_680_rdi_4_reg_info = {
.irq_status_addr = 0x12C,
.irq_mask_addr = 0x130,
.irq_clear_addr = 0x134,
.irq_set_addr = 0x138,
.cfg0_addr = 0x900,
.ctrl_addr = 0x904,
.debug_clr_cmd_addr = 0x908,
.multi_vcdt_cfg0_addr = 0x90c,
.cfg1_addr = 0x910,
.err_recovery_cfg0_addr = 0x914,
.err_recovery_cfg1_addr = 0x918,
.err_recovery_cfg2_addr = 0x91C,
.debug_byte_cntr_ping_addr = 0x920,
.debug_byte_cntr_pong_addr = 0x924,
.camif_frame_cfg_addr = 0x928,
.epoch_irq_cfg_addr = 0x92C,
.epoch0_subsample_ptrn_addr = 0x930,
.epoch1_subsample_ptrn_addr = 0x934,
.debug_camif_1_addr = 0x938,
.debug_camif_0_addr = 0x93C,
.frm_drop_pattern_addr = 0x940,
.frm_drop_period_addr = 0x940,
.irq_subsample_pattern_addr = 0x948,
.irq_subsample_period_addr = 0x94C,
.hcrop_addr = 0x950,
.vcrop_addr = 0x954,
.pix_drop_pattern_addr = 0x958,
.pix_drop_period_addr = 0x95C,
.line_drop_pattern_addr = 0x960,
.line_drop_period_addr = 0x964,
.debug_halt_status_addr = 0x968,
.debug_misr_val0_addr = 0x970,
.debug_misr_val1_addr = 0x974,
.debug_misr_val2_addr = 0x978,
.debug_misr_val3_addr = 0x97C,
.format_measure_cfg0_addr = 0x980,
.format_measure_cfg1_addr = 0x984,
.format_measure0_addr = 0x988,
.format_measure1_addr = 0x98C,
.format_measure2_addr = 0x990,
.timestamp_curr0_sof_addr = 0x994,
.timestamp_curr1_sof_addr = 0x998,
.timestamp_perv0_sof_addr = 0x99C,
.timestamp_perv1_sof_addr = 0x9A0,
.timestamp_curr0_eof_addr = 0x9A4,
.timestamp_curr1_eof_addr = 0x9A8,
.timestamp_perv0_eof_addr = 0x9AC,
.timestamp_perv1_eof_addr = 0x9B0,
.batch_id_cfg0_addr = 0x9B4,
.batch_id_cfg1_addr = 0x9B8,
.batch_period_cfg_addr = 0x9BC,
.batch_stream_id_cfg_addr = 0x9C0,
.epoch0_cfg_batch_id0_addr = 0x9C4,
.epoch1_cfg_batch_id0_addr = 0x9C8,
.epoch0_cfg_batch_id1_addr = 0x9CC,
.epoch1_cfg_batch_id1_addr = 0x9D0,
.epoch0_cfg_batch_id2_addr = 0x9D4,
.epoch1_cfg_batch_id2_addr = 0x9D8,
.epoch0_cfg_batch_id3_addr = 0x9DC,
.epoch1_cfg_batch_id3_addr = 0x9E0,
.epoch0_cfg_batch_id4_addr = 0x9E4,
.epoch1_cfg_batch_id4_addr = 0x9E8,
.epoch0_cfg_batch_id5_addr = 0x9EC,
.epoch1_cfg_batch_id5_addr = 0x9F0,
/* configurations */
.resume_frame_boundary = 1,
.overflow_ctrl_en = 1,
.overflow_ctrl_mode_val = 0x8,
.offline_mode_supported = 1,
.packing_fmt_shift_val = 15,
.early_eof_en_shift_val = 14,
.plain_fmt_shift_val = 12,
.plain_alignment_shift_val = 11,
.crop_v_en_shift_val = 8,
.crop_h_en_shift_val = 7,
.drop_v_en_shift_val = 6,
.drop_h_en_shift_val = 5,
.timestamp_en_shift_val = 4,
.format_measure_en_shift_val = 3,
.debug_byte_cntr_rst_shift_val = 2,
.offline_mode_en_shift_val = 2,
.pix_pattern_shift_val = 24,
.stripe_loc_shift_val = 20,
.ccif_violation_en = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x28000,
.camif_irq_mask = 0x800000,
.rup_aup_mask = 0x1000100,
};
static struct cam_ife_csid_csi2_rx_reg_info
cam_ife_csid_680_csi2_reg_info = {
.irq_status_addr = 0x9C,
.irq_mask_addr = 0xA0,
.irq_clear_addr = 0xA4,
.irq_set_addr = 0xA8,
/*CSI2 rx control */
.cfg0_addr = 0x200,
.cfg1_addr = 0x204,
.capture_ctrl_addr = 0x208,
.rst_strobes_addr = 0x20C,
.cap_unmap_long_pkt_hdr_0_addr = 0x210,
.cap_unmap_long_pkt_hdr_1_addr = 0x214,
.captured_short_pkt_0_addr = 0x218,
.captured_short_pkt_1_addr = 0x21c,
.captured_long_pkt_0_addr = 0x220,
.captured_long_pkt_1_addr = 0x224,
.captured_long_pkt_ftr_addr = 0x228,
.captured_cphy_pkt_hdr_addr = 0x22c,
.lane0_misr_addr = 0x230,
.lane1_misr_addr = 0x234,
.lane2_misr_addr = 0x238,
.lane3_misr_addr = 0x23c,
.total_pkts_rcvd_addr = 0x240,
.stats_ecc_addr = 0x244,
.total_crc_err_addr = 0x248,
.de_scramble_type3_cfg0_addr = 0x24C,
.de_scramble_type3_cfg1_addr = 0x250,
.de_scramble_type2_cfg0_addr = 0x254,
.de_scramble_type2_cfg1_addr = 0x258,
.de_scramble_type1_cfg0_addr = 0x25C,
.de_scramble_type1_cfg1_addr = 0x260,
.de_scramble_type0_cfg0_addr = 0x264,
.de_scramble_type0_cfg1_addr = 0x268,
.rst_done_shift_val = 27,
.irq_mask_all = 0xFFFFFFF,
.misr_enable_shift_val = 6,
.vc_mode_shift_val = 2,
.capture_long_pkt_en_shift = 0,
.capture_short_pkt_en_shift = 1,
.capture_cphy_pkt_en_shift = 2,
.capture_long_pkt_dt_shift = 4,
.capture_long_pkt_vc_shift = 10,
.capture_short_pkt_vc_shift = 15,
.capture_cphy_pkt_dt_shift = 20,
.capture_cphy_pkt_vc_shift = 26,
.phy_num_mask = 0xf,
.vc_mask = 0x7C00000,
.dt_mask = 0x3f0000,
.wc_mask = 0xffff0000,
.calc_crc_mask = 0xffff,
.expected_crc_mask = 0xffff,
.ecc_correction_shift_en = 0,
.lane_num_shift = 0,
.lane_cfg_shift = 4,
.phy_type_shift = 24,
.phy_num_shift = 20,
.tpg_mux_en_shift = 27,
.tpg_num_sel_shift = 28,
.phy_bist_shift_en = 7,
.epd_mode_shift_en = 8,
.eotp_shift_en = 9,
.dyn_sensor_switch_shift_en = 10,
.fatal_err_mask = 0x78000,
.part_fatal_err_mask = 0x1801800,
.non_fatal_err_mask = 0x380000,
};
static struct cam_ife_csid_ver2_common_reg_info
cam_ife_csid_680_cmn_reg_info = {
.hw_version_addr = 0x0,
.cfg0_addr = 0x4,
.global_cmd_addr = 0x8,
.reset_cfg_addr = 0xc,
.reset_cmd_addr = 0x10,
.irq_cmd_addr = 0x14,
.rup_aup_cmd_addr = 0x18,
.offline_cmd_addr = 0x1C,
.shdr_master_slave_cfg_addr = 0x20,
.top_irq_status_addr = 0x7C,
.top_irq_mask_addr = 0x80,
.top_irq_clear_addr = 0x84,
.top_irq_set_addr = 0x88,
.buf_done_irq_status_addr = 0x8C,
.buf_done_irq_mask_addr = 0x90,
.buf_done_irq_clear_addr = 0x94,
.buf_done_irq_set_addr = 0x98,
/*configurations */
.major_version = 6,
.minor_version = 8,
.version_incr = 0,
.num_rdis = 5,
.num_pix = 1,
.num_ppp = 1,
.rst_done_shift_val = 1,
.path_en_shift_val = 31,
.dt_id_shift_val = 27,
.vc_shift_val = 22,
.dt_shift_val = 16,
.crop_shift_val = 16,
.decode_format_shift_val = 12,
.frame_id_decode_en_shift_val = 1,
.multi_vcdt_vc1_shift_val = 2,
.multi_vcdt_dt1_shift_val = 7,
.multi_vcdt_en_shift_val = 0,
.timestamp_stb_sel_shift_val = 0,
.vfr_en_shift_val = 0,
.mup_shift_val = 28,
.shdr_slave_rdi2_shift = 22,
.shdr_slave_rdi1_shift = 21,
.shdr_master_rdi0_shift = 5,
.shdr_master_slave_en_shift = 0,
.early_eof_supported = 1,
.vfr_supported = 1,
.multi_vcdt_supported = 1,
.frame_id_dec_supported = 1,
.measure_en_hbi_vbi_cnt_mask = 0xc,
.measure_pixel_line_en_mask = 0x3,
.crop_pix_start_mask = 0x3fff,
.crop_pix_end_mask = 0xffff,
.crop_line_start_mask = 0x3fff,
.crop_line_end_mask = 0xffff,
.drop_supported = 1,
.ipp_irq_mask_all = 0x7FFF,
.rdi_irq_mask_all = 0x7FFF,
.ppp_irq_mask_all = 0xFFFF,
.rst_loc_path_only_val = 0x0,
.rst_loc_complete_csid_val = 0x1,
.rst_mode_frame_boundary_val = 0x0,
.rst_mode_immediate_val = 0x1,
.rst_cmd_hw_reset_complete_val = 0x0,
.rst_cmd_sw_reset_complete_val = 0x2,
.rst_cmd_irq_ctrl_only_val = 0x4,
.timestamp_strobe_val = 0x2,
.top_reset_irq_shift_val = 0,
.rst_location_shift_val = 4,
.rst_mode_shift_val = 0,
.epoch_div_factor = 4,
.global_reset = 1,
.rup_supported = 1,
};
static struct cam_ife_csid_ver2_top_reg_info
cam_ife_csid_680_top_reg_info = {
.io_path_cfg0_addr = {
0x0,
0x4,
0x8,
},
.dual_csid_cfg0_addr = {
0xC,
0x10,
0x14,
},
.input_core_type_shift_val = 0,
.sfe_offline_en_shift_val = 12,
.out_ife_en_shift_val = 8,
.dual_sync_sel_shift_val = 8,
.dual_en_shift_val = 0,
.master_slave_sel_shift_val = 1,
.master_sel_val = 0,
.slave_sel_val = 1,
};
static struct cam_ife_csid_ver2_reg_info cam_ife_csid_680_reg_info = {
.irq_reg_info = &cam_ife_csid_680_irq_reg_info,
.buf_done_irq_reg_info = &cam_ife_csid_680_buf_done_irq_reg_info,
.cmn_reg = &cam_ife_csid_680_cmn_reg_info,
.csi2_reg = &cam_ife_csid_680_csi2_reg_info,
.ipp_reg = &cam_ife_csid_680_ipp_reg_info,
.ppp_reg = &cam_ife_csid_680_ppp_reg_info,
.rdi_reg = {
&cam_ife_csid_680_rdi_0_reg_info,
&cam_ife_csid_680_rdi_1_reg_info,
&cam_ife_csid_680_rdi_2_reg_info,
&cam_ife_csid_680_rdi_3_reg_info,
&cam_ife_csid_680_rdi_4_reg_info,
},
.top_reg = &cam_ife_csid_680_top_reg_info,
.input_core_sel = {
{
0x0,
0x1,
0x2,
0x3,
0x8,
-1,
-1,
},
{
0x0,
0x1,
0x2,
0x3,
-1,
-1,
-1,
},
{
0x0,
0x1,
0x2,
0x3,
-1,
0x9,
-1,
},
},
.need_top_cfg = 0x1,
.csid_cust_node_map = {0x1, 0x0, 0x2},
};
#endif /*_CAM_IFE_CSID_680_H_ */

661
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.c Normal file
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@@ -0,0 +1,661 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#include <linux/iopoll.h>
#include <linux/slab.h>
#include <media/cam_isp.h>
#include <media/cam_defs.h>
#include <dt-bindings/msm/msm-camera.h>
#include "cam_soc_util.h"
#include "cam_io_util.h"
#include "cam_debug_util.h"
#include "cam_cpas_api.h"
#include "cam_hw.h"
#include "cam_cdm_util.h"
#include "cam_ife_csid_hw_intf.h"
#include "cam_ife_csid_soc.h"
#include "cam_ife_csid_common.h"
#include "cam_ife_csid_hw_ver1.h"
#include "cam_ife_csid_hw_ver2.h"
const uint8_t *cam_ife_csid_irq_reg_tag[CAM_IFE_CSID_IRQ_REG_MAX] = {
"TOP",
"RX",
"RDI0",
"RDI1",
"RDI2",
"RDI3",
"RDI4",
"IPP",
"PPP",
"UDI0",
"UDI1",
"UDI2",
};
static int cam_ife_csid_get_cid(struct cam_ife_csid_cid_data *cid_data,
struct cam_csid_hw_reserve_resource_args *reserve)
{
uint32_t i;
if (cid_data->cid_cnt == 0) {
for (i = 0; i < reserve->in_port->num_valid_vc_dt; i++) {
cid_data->vc_dt[i].vc = reserve->in_port->vc[i];
cid_data->vc_dt[i].dt = reserve->in_port->dt[i];
cid_data->vc_dt[i].valid = true;
}
cid_data->num_vc_dt = reserve->in_port->num_valid_vc_dt;
return 0;
}
for (i = 0; i < reserve->in_port->num_valid_vc_dt; i++) {
if (cid_data->vc_dt[i].vc == reserve->in_port->vc[i] &&
cid_data->vc_dt[i].dt == reserve->in_port->dt[i])
return 0;
}
return -EINVAL;
}
int cam_ife_csid_is_pix_res_format_supported(
uint32_t in_format)
{
int rc = -EINVAL;
switch (in_format) {
case CAM_FORMAT_MIPI_RAW_6:
case CAM_FORMAT_MIPI_RAW_8:
case CAM_FORMAT_MIPI_RAW_10:
case CAM_FORMAT_MIPI_RAW_12:
case CAM_FORMAT_MIPI_RAW_14:
case CAM_FORMAT_MIPI_RAW_16:
case CAM_FORMAT_MIPI_RAW_20:
case CAM_FORMAT_DPCM_10_6_10:
case CAM_FORMAT_DPCM_10_8_10:
case CAM_FORMAT_DPCM_12_6_12:
case CAM_FORMAT_DPCM_12_8_12:
case CAM_FORMAT_DPCM_14_8_14:
case CAM_FORMAT_DPCM_14_10_14:
case CAM_FORMAT_DPCM_12_10_12:
rc = 0;
break;
default:
break;
}
return rc;
}
int cam_ife_csid_get_format_rdi(
uint32_t in_format, uint32_t out_format,
struct cam_ife_csid_path_format *path_format, bool rpp)
{
int rc = 0;
switch (in_format) {
case CAM_FORMAT_MIPI_RAW_6:
switch (out_format) {
case CAM_FORMAT_MIPI_RAW_6:
path_format->decode_fmt = 0xf;
if (rpp) {
path_format->decode_fmt = 0x0;
path_format->packing_fmt = 0x1;
}
break;
case CAM_FORMAT_PLAIN8:
path_format->decode_fmt = 0x0;
path_format->plain_fmt = 0x0;
break;
default:
rc = -EINVAL;
break;
}
path_format->bits_per_pxl = 6;
break;
case CAM_FORMAT_MIPI_RAW_8:
switch (out_format) {
case CAM_FORMAT_MIPI_RAW_8:
case CAM_FORMAT_PLAIN128:
path_format->decode_fmt = 0xf;
if (rpp) {
path_format->decode_fmt = 0x1;
path_format->packing_fmt = 0x1;
}
break;
case CAM_FORMAT_PLAIN8:
path_format->decode_fmt = 0x1;
path_format->plain_fmt = 0x0;
break;
default:
rc = -EINVAL;
break;
}
path_format->bits_per_pxl = 8;
break;
case CAM_FORMAT_MIPI_RAW_10:
switch (out_format) {
case CAM_FORMAT_MIPI_RAW_10:
case CAM_FORMAT_PLAIN128:
path_format->decode_fmt = 0xf;
if (rpp) {
path_format->decode_fmt = 0x2;
path_format->packing_fmt = 0x1;
}
break;
case CAM_FORMAT_PLAIN16_10:
path_format->decode_fmt = 0x2;
path_format->plain_fmt = 0x1;
break;
default:
rc = -EINVAL;
break;
}
path_format->bits_per_pxl = 10;
break;
case CAM_FORMAT_MIPI_RAW_12:
switch (out_format) {
case CAM_FORMAT_MIPI_RAW_12:
path_format->decode_fmt = 0xf;
if (rpp) {
path_format->decode_fmt = 0x3;
path_format->packing_fmt = 0x1;
}
break;
case CAM_FORMAT_PLAIN16_12:
path_format->decode_fmt = 0x3;
path_format->plain_fmt = 0x1;
break;
default:
rc = -EINVAL;
break;
}
path_format->bits_per_pxl = 12;
break;
case CAM_FORMAT_MIPI_RAW_14:
switch (out_format) {
case CAM_FORMAT_MIPI_RAW_14:
path_format->decode_fmt = 0xf;
if (rpp) {
path_format->decode_fmt = 0x4;
path_format->packing_fmt = 0x1;
}
break;
case CAM_FORMAT_PLAIN16_14:
path_format->decode_fmt = 0x4;
path_format->plain_fmt = 0x1;
break;
default:
rc = -EINVAL;
break;
}
path_format->bits_per_pxl = 14;
break;
case CAM_FORMAT_MIPI_RAW_16:
switch (out_format) {
case CAM_FORMAT_MIPI_RAW_16:
path_format->decode_fmt = 0xf;
if (rpp) {
path_format->decode_fmt = 0x5;
path_format->packing_fmt = 0x1;
}
break;
case CAM_FORMAT_PLAIN16_16:
path_format->decode_fmt = 0x5;
path_format->plain_fmt = 0x1;
break;
default:
rc = -EINVAL;
break;
}
path_format->bits_per_pxl = 16;
break;
case CAM_FORMAT_MIPI_RAW_20:
switch (out_format) {
case CAM_FORMAT_MIPI_RAW_20:
path_format->decode_fmt = 0xf;
if (rpp) {
path_format->decode_fmt = 0x6;
path_format->packing_fmt = 0x1;
}
break;
case CAM_FORMAT_PLAIN32_20:
path_format->decode_fmt = 0x6;
path_format->plain_fmt = 0x2;
break;
default:
rc = -EINVAL;
break;
}
path_format->bits_per_pxl = 20;
break;
case CAM_FORMAT_DPCM_10_6_10:
path_format->decode_fmt = 0x7;
path_format->plain_fmt = 0x1;
break;
case CAM_FORMAT_DPCM_10_8_10:
path_format->decode_fmt = 0x8;
path_format->plain_fmt = 0x1;
break;
case CAM_FORMAT_DPCM_12_6_12:
path_format->decode_fmt = 0x9;
path_format->plain_fmt = 0x1;
break;
case CAM_FORMAT_DPCM_12_8_12:
path_format->decode_fmt = 0xA;
path_format->plain_fmt = 0x1;
break;
case CAM_FORMAT_DPCM_14_8_14:
path_format->decode_fmt = 0xB;
path_format->plain_fmt = 0x1;
break;
case CAM_FORMAT_DPCM_14_10_14:
path_format->decode_fmt = 0xC;
path_format->plain_fmt = 0x1;
break;
case CAM_FORMAT_DPCM_12_10_12:
path_format->decode_fmt = 0xD;
path_format->plain_fmt = 0x1;
break;
default:
rc = -EINVAL;
break;
}
if (rc)
CAM_ERR(CAM_ISP, "Unsupported format pair in %d out %d",
in_format, out_format);
return rc;
}
int cam_ife_csid_get_format_ipp_ppp(
uint32_t in_format,
struct cam_ife_csid_path_format *path_format)
{
int rc = 0;
CAM_DBG(CAM_ISP, "input format:%d",
in_format);
switch (in_format) {
case CAM_FORMAT_MIPI_RAW_6:
path_format->decode_fmt = 0;
path_format->plain_fmt = 0;
break;
case CAM_FORMAT_MIPI_RAW_8:
path_format->decode_fmt = 0x1;
path_format->plain_fmt = 0;
break;
case CAM_FORMAT_MIPI_RAW_10:
path_format->decode_fmt = 0x2;
path_format->plain_fmt = 0x1;
break;
case CAM_FORMAT_MIPI_RAW_12:
path_format->decode_fmt = 0x3;
path_format->plain_fmt = 0x1;
break;
case CAM_FORMAT_MIPI_RAW_14:
path_format->decode_fmt = 0x4;
path_format->plain_fmt = 0x1;
break;
case CAM_FORMAT_MIPI_RAW_16:
path_format->decode_fmt = 0x5;
path_format->plain_fmt = 0x1;
break;
case CAM_FORMAT_MIPI_RAW_20:
path_format->decode_fmt = 0x6;
path_format->plain_fmt = 0x2;
break;
case CAM_FORMAT_DPCM_10_6_10:
path_format->decode_fmt = 0x7;
path_format->plain_fmt = 0x1;
break;
case CAM_FORMAT_DPCM_10_8_10:
path_format->decode_fmt = 0x8;
path_format->plain_fmt = 0x1;
break;
case CAM_FORMAT_DPCM_12_6_12:
path_format->decode_fmt = 0x9;
path_format->plain_fmt = 0x1;
break;
case CAM_FORMAT_DPCM_12_8_12:
path_format->decode_fmt = 0xA;
path_format->plain_fmt = 0x1;
break;
case CAM_FORMAT_DPCM_14_8_14:
path_format->decode_fmt = 0xB;
path_format->plain_fmt = 0x1;
break;
case CAM_FORMAT_DPCM_14_10_14:
path_format->decode_fmt = 0xC;
path_format->plain_fmt = 0x1;
break;
case CAM_FORMAT_DPCM_12_10_12:
path_format->decode_fmt = 0xD;
path_format->plain_fmt = 0x1;
break;
default:
CAM_ERR(CAM_ISP, "Unsupported format %d",
in_format);
rc = -EINVAL;
}
CAM_DBG(CAM_ISP, "decode_fmt:%d plain_fmt:%d",
path_format->decode_fmt,
path_format->plain_fmt);
return rc;
}
int cam_ife_csid_hw_probe_init(struct cam_hw_intf *hw_intf,
struct cam_ife_csid_core_info *core_info, bool is_custom)
{
int rc = -EINVAL;
if (core_info->sw_version == CAM_IFE_CSID_VER_1_0) {
rc = cam_ife_csid_hw_ver1_init(hw_intf,
core_info, is_custom);
} else if (core_info->sw_version == CAM_IFE_CSID_VER_2_0) {
rc = cam_ife_csid_hw_ver2_init(hw_intf,
core_info, is_custom);
}
return rc;
}
int cam_ife_csid_hw_deinit(struct cam_hw_intf *hw_intf,
struct cam_ife_csid_core_info *core_info)
{
int rc = -EINVAL;
if (core_info->sw_version == CAM_IFE_CSID_VER_1_0)
rc = cam_ife_csid_hw_ver1_deinit(hw_intf->hw_priv);
else if (core_info->sw_version == CAM_IFE_CSID_VER_2_0)
rc = cam_ife_csid_hw_ver2_deinit(
hw_intf->hw_priv);
return rc;
}
int cam_ife_csid_is_vc_full_width(struct cam_ife_csid_cid_data *cid_data)
{
int i, j;
int rc = 0;
struct cam_ife_csid_cid_data *p_cid;
for (i = 0; i < CAM_IFE_CSID_CID_MAX; i++) {
p_cid = &cid_data[i];
if (!p_cid->cid_cnt)
continue;
if (p_cid->num_vc_dt >= CAM_IFE_CSID_MULTI_VC_DT_GRP_MAX) {
CAM_ERR(CAM_ISP, "Invalid num_vc_dt:%d cid: %d",
p_cid->num_vc_dt, i);
rc = -EINVAL;
goto end;
}
for (j = 0; j < p_cid->num_vc_dt; j++) {
if (p_cid->vc_dt[j].valid &&
p_cid->vc_dt[j].vc > 3) {
rc = 1;
goto end;
}
}
}
end:
return rc;
}
int cam_ife_csid_cid_reserve(struct cam_ife_csid_cid_data *cid_data,
uint32_t *cid_value,
uint32_t hw_idx,
struct cam_csid_hw_reserve_resource_args *reserve)
{
int i, j, rc = 0;
for (i = 0; i < CAM_IFE_CSID_CID_MAX; i++) {
rc = cam_ife_csid_get_cid(&cid_data[i], reserve);
if (!rc)
break;
}
if (i == CAM_IFE_CSID_CID_MAX) {
for (j = 0; j < reserve->in_port->num_valid_vc_dt; j++) {
CAM_ERR(CAM_ISP,
"CSID[%d] reserve fail vc[%d] dt[%d]",
hw_idx, reserve->in_port->vc[j],
reserve->in_port->dt[j]);
return -EINVAL;
}
}
cid_data[i].cid_cnt++;
*cid_value = i;
return 0;
}
int cam_ife_csid_cid_release(
struct cam_ife_csid_cid_data *cid_data,
uint32_t hw_idx,
uint32_t cid)
{
int i;
if (!cid_data->cid_cnt) {
CAM_WARN(CAM_ISP, "CSID[%d] unbalanced cid:%d release",
hw_idx, cid);
return 0;
}
cid_data->cid_cnt--;
if (cid_data->cid_cnt == 0) {
for (i = 0; i < cid_data->num_vc_dt; i++)
cid_data->vc_dt[i].valid = false;
cid_data->num_vc_dt = 0;
}
return 0;
}
int cam_ife_csid_check_in_port_args(
struct cam_csid_hw_reserve_resource_args *reserve,
uint32_t hw_idx)
{
if (reserve->in_port->res_type >= CAM_ISP_IFE_IN_RES_MAX) {
CAM_ERR(CAM_ISP, "CSID:%d Invalid phy sel %d",
hw_idx, reserve->in_port->res_type);
return -EINVAL;
}
if (reserve->in_port->lane_type >= CAM_ISP_LANE_TYPE_MAX &&
reserve->in_port->res_type != CAM_ISP_IFE_IN_RES_TPG) {
CAM_ERR(CAM_ISP, "CSID:%d Invalid lane type %d",
hw_idx, reserve->in_port->lane_type);
return -EINVAL;
}
if ((reserve->in_port->lane_type == CAM_ISP_LANE_TYPE_DPHY &&
reserve->in_port->lane_num > 4) &&
reserve->in_port->res_type != CAM_ISP_IFE_IN_RES_TPG) {
CAM_ERR(CAM_ISP, "CSID:%d Invalid lane num %d",
hw_idx, reserve->in_port->lane_num);
return -EINVAL;
}
if ((reserve->in_port->lane_type == CAM_ISP_LANE_TYPE_CPHY &&
reserve->in_port->lane_num > 3) &&
reserve->in_port->res_type != CAM_ISP_IFE_IN_RES_TPG) {
CAM_ERR(CAM_ISP, " CSID:%d Invalid lane type %d & num %d",
hw_idx,
reserve->in_port->lane_type,
reserve->in_port->lane_num);
return -EINVAL;
}
if ((reserve->res_id == CAM_IFE_PIX_PATH_RES_IPP ||
reserve->res_id == CAM_IFE_PIX_PATH_RES_PPP) &&
(cam_ife_csid_is_pix_res_format_supported(
reserve->in_port->format))) {
CAM_ERR(CAM_ISP, "CSID %d, res_id %d, unsupported format %d",
hw_idx, reserve->res_id, reserve->in_port->format);
return -EINVAL;
}
return 0;
}
int cam_ife_csid_set_epd_config(struct cam_ife_csid_hw_flags *flags,
void *cmd_args, uint32_t hw_idx)
{
struct cam_ife_csid_epd_update_args *epd_update = NULL;
if ((!flags) || (!cmd_args))
return -EINVAL;
epd_update =
(struct cam_ife_csid_epd_update_args *)cmd_args;
flags->epd_supported = epd_update->epd_supported;
CAM_DBG(CAM_ISP, "CSID[%u] EPD supported %d", hw_idx,
flags->epd_supported);
return 0;
}
int cam_ife_csid_get_rt_irq_idx(
uint32_t irq_reg, uint32_t num_ipp,
uint32_t num_ppp, uint32_t num_rdi)
{
int rt_irq_reg_idx = -EINVAL;
switch (irq_reg) {
case CAM_IFE_CSID_IRQ_REG_IPP:
rt_irq_reg_idx = CAM_IFE_CSID_IRQ_REG_RX +
num_rdi + 1;
break;
case CAM_IFE_CSID_IRQ_REG_PPP:
rt_irq_reg_idx = CAM_IFE_CSID_IRQ_REG_RX +
num_rdi + num_ipp + 1;
break;
case CAM_IFE_CSID_IRQ_REG_RDI_0:
case CAM_IFE_CSID_IRQ_REG_RDI_1:
case CAM_IFE_CSID_IRQ_REG_RDI_2:
case CAM_IFE_CSID_IRQ_REG_RDI_3:
case CAM_IFE_CSID_IRQ_REG_RDI_4:
rt_irq_reg_idx = irq_reg;
break;
case CAM_IFE_CSID_IRQ_REG_UDI_0:
case CAM_IFE_CSID_IRQ_REG_UDI_1:
case CAM_IFE_CSID_IRQ_REG_UDI_2:
rt_irq_reg_idx = CAM_IFE_CSID_IRQ_REG_RX +
num_rdi + num_ipp + num_ppp +
(irq_reg - CAM_IFE_CSID_IRQ_REG_UDI_0) + 1;
break;
default:
CAM_ERR(CAM_ISP, "Invalid irq reg %d", irq_reg);
break;
}
return rt_irq_reg_idx;
}
int cam_ife_csid_convert_res_to_irq_reg(uint32_t res_id)
{
switch (res_id) {
case CAM_IFE_PIX_PATH_RES_RDI_0:
return CAM_IFE_CSID_IRQ_REG_RDI_0;
case CAM_IFE_PIX_PATH_RES_RDI_1:
return CAM_IFE_CSID_IRQ_REG_RDI_1;
case CAM_IFE_PIX_PATH_RES_RDI_2:
return CAM_IFE_CSID_IRQ_REG_RDI_2;
case CAM_IFE_PIX_PATH_RES_RDI_3:
return CAM_IFE_CSID_IRQ_REG_RDI_3;
case CAM_IFE_PIX_PATH_RES_RDI_4:
return CAM_IFE_CSID_IRQ_REG_RDI_4;
case CAM_IFE_PIX_PATH_RES_IPP:
return CAM_IFE_CSID_IRQ_REG_IPP;
case CAM_IFE_PIX_PATH_RES_PPP:
return CAM_IFE_CSID_IRQ_REG_PPP;
case CAM_IFE_PIX_PATH_RES_UDI_0:
return CAM_IFE_CSID_IRQ_REG_UDI_0;
case CAM_IFE_PIX_PATH_RES_UDI_1:
return CAM_IFE_CSID_IRQ_REG_UDI_1;
case CAM_IFE_PIX_PATH_RES_UDI_2:
return CAM_IFE_CSID_IRQ_REG_UDI_2;
default:
return -EINVAL;
}
}
int cam_ife_csid_get_base(struct cam_hw_soc_info *soc_info,
uint32_t base_id, void *cmd_args, size_t arg_size)
{
struct cam_isp_hw_get_cmd_update *cdm_args = cmd_args;
struct cam_cdm_utils_ops *cdm_util_ops = NULL;
size_t size = 0;
uint32_t mem_base = 0;
if (arg_size != sizeof(struct cam_isp_hw_get_cmd_update)) {
CAM_ERR(CAM_ISP, "Error, Invalid cmd size");
return -EINVAL;
}
if (!cdm_args || !cdm_args->res) {
CAM_ERR(CAM_ISP, "Error, Invalid args");
return -EINVAL;
}
cdm_util_ops =
(struct cam_cdm_utils_ops *)cdm_args->res->cdm_ops;
if (!cdm_util_ops) {
CAM_ERR(CAM_ISP, "Invalid CDM ops");
return -EINVAL;
}
size = cdm_util_ops->cdm_required_size_changebase();
/* since cdm returns dwords, we need to convert it into bytes */
if ((size * 4) > cdm_args->cmd.size) {
CAM_ERR(CAM_ISP, "buf size:%d is not sufficient, expected: %d",
cdm_args->cmd.size, size);
return -EINVAL;
}
mem_base = CAM_SOC_GET_REG_MAP_CAM_BASE(
soc_info, base_id);
CAM_DBG(CAM_ISP, "core %d mem_base 0x%x",
soc_info->index, mem_base);
cdm_util_ops->cdm_write_changebase(
cdm_args->cmd.cmd_buf_addr, mem_base);
cdm_args->cmd.used_bytes = (size * 4);
return 0;
}
const uint8_t **cam_ife_csid_get_irq_reg_tag_ptr(void)
{
return cam_ife_csid_irq_reg_tag;
}

362
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.h Normal file
View File

@@ -0,0 +1,362 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef _CAM_IFE_CSID_COMMON_H_
#define _CAM_IFE_CSID_COMMON_H_
#include "cam_hw.h"
#include "cam_ife_csid_hw_intf.h"
#include "cam_ife_csid_soc.h"
#define CAM_IFE_CSID_VER_1_0 0x100
#define CAM_IFE_CSID_VER_2_0 0x200
#define CAM_IFE_CSID_MAX_ERR_COUNT 100
#define CAM_IFE_CSID_HW_CAP_IPP 0x1
#define CAM_IFE_CSID_HW_CAP_RDI 0x2
#define CAM_IFE_CSID_HW_CAP_PPP 0x4
#define CAM_IFE_CSID_HW_CAP_TOP 0x8
#define CAM_IFE_CSID_TPG_ENCODE_RAW8 0x1
#define CAM_IFE_CSID_TPG_ENCODE_RAW10 0x2
#define CAM_IFE_CSID_TPG_ENCODE_RAW12 0x3
#define CAM_IFE_CSID_TPG_ENCODE_RAW14 0x4
#define CAM_IFE_CSID_TPG_ENCODE_RAW16 0x5
#define CAM_IFE_CSID_TPG_TEST_PATTERN_YUV 0x4
#define CAM_IFE_CSID_HW_IDX_0 0x1
#define CAM_IFE_CSID_HW_IDX_1 0x2
#define CAM_IFE_CSID_HW_IDX_2 0x4
#define CAM_IFE_CSID_LOG_BUF_LEN 512
/*
* Debug values enable the corresponding interrupts and debug logs provide
* necessary information
*/
#define CAM_IFE_CSID_DEBUG_ENABLE_SOF_IRQ BIT(0)
#define CAM_IFE_CSID_DEBUG_ENABLE_EOF_IRQ BIT(1)
#define CAM_IFE_CSID_DEBUG_ENABLE_SOT_IRQ BIT(2)
#define CAM_IFE_CSID_DEBUG_ENABLE_EOT_IRQ BIT(3)
#define CAM_IFE_CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE BIT(4)
#define CAM_IFE_CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE BIT(5)
#define CAM_IFE_CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE BIT(6)
#define CAM_IFE_CSID_DEBUG_ENABLE_HBI_VBI_INFO BIT(7)
#define CAM_IFE_CSID_DEBUG_DISABLE_EARLY_EOF BIT(8)
/* Binning supported masks. Binning support changes for specific paths
* and also for targets. With the mask, we handle the supported features
* in reg files and handle in code accordingly.
*/
#define CAM_IFE_CSID_BIN_HORIZONTAL BIT(0)
#define CAM_IFE_CSID_BIN_QCFA BIT(1)
#define CAM_IFE_CSID_BIN_VERTICAL BIT(2)
#define CAM_IFE_CSID_WIDTH_FUSE_VAL_MAX 4
/* enum for multiple mem base in some of the targets */
enum cam_ife_csid_mem_base_id {
CAM_IFE_CSID_CLC_MEM_BASE_ID,
CAM_IFE_CSID_TOP_MEM_BASE_ID,
};
/* enum cam_ife_csid_path_multi_vc_dt_grp: for multi vc dt suppot */
enum cam_ife_csid_path_multi_vc_dt_grp {
CAM_IFE_CSID_MULTI_VC_DT_GRP_0,
CAM_IFE_CSID_MULTI_VC_DT_GRP_1,
CAM_IFE_CSID_MULTI_VC_DT_GRP_MAX,
};
/**
* enum cam_ife_csid_irq_reg - Specify the csid irq reg
*/
enum cam_ife_csid_irq_reg {
CAM_IFE_CSID_IRQ_REG_TOP,
CAM_IFE_CSID_IRQ_REG_RX,
CAM_IFE_CSID_IRQ_REG_RDI_0,
CAM_IFE_CSID_IRQ_REG_RDI_1,
CAM_IFE_CSID_IRQ_REG_RDI_2,
CAM_IFE_CSID_IRQ_REG_RDI_3,
CAM_IFE_CSID_IRQ_REG_RDI_4,
CAM_IFE_CSID_IRQ_REG_IPP,
CAM_IFE_CSID_IRQ_REG_PPP,
CAM_IFE_CSID_IRQ_REG_UDI_0,
CAM_IFE_CSID_IRQ_REG_UDI_1,
CAM_IFE_CSID_IRQ_REG_UDI_2,
CAM_IFE_CSID_IRQ_REG_MAX,
};
/*
* struct cam_ife_csid_irq_desc: Structure to hold IRQ description
*
* @irq_desc: String to describe the IRQ bit
*/
struct cam_ife_csid_irq_desc {
uint8_t *desc;
};
/*
* struct cam_ife_csid_vc_dt: Structure to hold vc dt combination
*
* @vc: Virtual channel number
* @dt: Data type of incoming data
* @valid: flag to indicate if combimation is valid
*/
struct cam_ife_csid_vc_dt {
uint32_t vc;
uint32_t dt;
bool valid;
};
/*
* struct cam_ife_csid_path_format: Structure format info
*
* @decode_fmt: Decode format
* @packing_fmt: Packing format
* @plain_fmt: Plain format
* @bits_per_pixel: Bits per pixel
*/
struct cam_ife_csid_path_format {
uint32_t decode_fmt;
uint32_t packing_fmt;
uint32_t plain_fmt;
uint32_t bits_per_pxl;
};
/*
* struct cam_ife_csid_csi2_rx_reg_info: Structure to hold Rx reg offset
* holds register address offsets
* shift values
* masks
*/
struct cam_ife_csid_csi2_rx_reg_info {
uint32_t irq_status_addr;
uint32_t irq_mask_addr;
uint32_t irq_clear_addr;
uint32_t irq_set_addr;
uint32_t cfg0_addr;
uint32_t cfg1_addr;
uint32_t capture_ctrl_addr;
uint32_t rst_strobes_addr;
uint32_t de_scramble_cfg0_addr;
uint32_t de_scramble_cfg1_addr;
uint32_t cap_unmap_long_pkt_hdr_0_addr;
uint32_t cap_unmap_long_pkt_hdr_1_addr;
uint32_t captured_short_pkt_0_addr;
uint32_t captured_short_pkt_1_addr;
uint32_t captured_long_pkt_0_addr;
uint32_t captured_long_pkt_1_addr;
uint32_t captured_long_pkt_ftr_addr;
uint32_t captured_cphy_pkt_hdr_addr;
uint32_t lane0_misr_addr;
uint32_t lane1_misr_addr;
uint32_t lane2_misr_addr;
uint32_t lane3_misr_addr;
uint32_t total_pkts_rcvd_addr;
uint32_t stats_ecc_addr;
uint32_t total_crc_err_addr;
uint32_t de_scramble_type3_cfg0_addr;
uint32_t de_scramble_type3_cfg1_addr;
uint32_t de_scramble_type2_cfg0_addr;
uint32_t de_scramble_type2_cfg1_addr;
uint32_t de_scramble_type1_cfg0_addr;
uint32_t de_scramble_type1_cfg1_addr;
uint32_t de_scramble_type0_cfg0_addr;
uint32_t de_scramble_type0_cfg1_addr;
/*configurations */
uint32_t rst_srb_all;
uint32_t rst_done_shift_val;
uint32_t irq_mask_all;
uint32_t misr_enable_shift_val;
uint32_t vc_mode_shift_val;
uint32_t capture_long_pkt_en_shift;
uint32_t capture_short_pkt_en_shift;
uint32_t capture_cphy_pkt_en_shift;
uint32_t capture_long_pkt_dt_shift;
uint32_t capture_long_pkt_vc_shift;
uint32_t capture_short_pkt_vc_shift;
uint32_t capture_cphy_pkt_dt_shift;
uint32_t capture_cphy_pkt_vc_shift;
uint32_t ecc_correction_shift_en;
uint32_t phy_bist_shift_en;
uint32_t epd_mode_shift_en;
uint32_t eotp_shift_en;
uint32_t dyn_sensor_switch_shift_en;
uint32_t phy_num_mask;
uint32_t vc_mask;
uint32_t wc_mask;
uint32_t dt_mask;
uint32_t calc_crc_mask;
uint32_t expected_crc_mask;
uint32_t lane_num_shift;
uint32_t lane_cfg_shift;
uint32_t phy_type_shift;
uint32_t phy_num_shift;
uint32_t tpg_mux_en_shift;
uint32_t tpg_num_sel_shift;
uint32_t fatal_err_mask;
uint32_t part_fatal_err_mask;
uint32_t non_fatal_err_mask;
uint32_t debug_irq_mask;
};
/*
* struct cam_ife_csid_timestamp: place holder for csid core info
*
* @prev_boot_timestamp: Previous frame boot timestamp
* @prev_sof_timestamp: Previous frame SOF timetamp
*/
struct cam_ife_csid_timestamp {
uint64_t prev_boot_ts;
uint64_t prev_sof_ts;
};
/*
* struct cam_ife_csid_core_info: place holder for csid core info
*
* @csid_reg: Pointer to csid reg info
* @sw_version: sw version based on targets
*/
struct cam_ife_csid_core_info {
void *csid_reg;
uint32_t sw_version;
};
/*
* struct cam_ife_csid_hw_counters: place holder for csid counters
*
* @csi2_reserve_cnt: Reserve count for csi2
* @irq_debug_cnt: irq debug counter
* @error_irq_count: error irq counter
*/
struct cam_ife_csid_hw_counters {
uint32_t csi2_reserve_cnt;
uint32_t irq_debug_cnt;
uint32_t error_irq_count;
};
/*
* struct cam_ife_csid_debug_info: place holder for csid debug
*
* @debug_val: Debug val for enabled features
* @rx_mask: Debug mask for rx irq
* @path_mask: Debug mask for path irq
*/
struct cam_ife_csid_debug_info {
uint32_t debug_val;
uint32_t rx_mask;
uint32_t path_mask;
};
/*
* struct cam_ife_csid_hw_flags: place holder for flags
*
* @epd_supported: flag to indicate if epd supported
* @device_enabled: flag to indicate if device enabled
* @binning_enabled: flag to indicate if binning enabled
* @sof_irq_triggered: flag to indicate if sof irq triggered
* @fatal_err_detected: flag to indicate if fatal err detected
* @rx_enabled: flag to indicate if rx is enabled
* @tpg_configured: flag to indicate if internal_tpg is configured
* @sfe_inline_shdr: flag to indicate if sfe is inline shdr
* @reset_awaited: flag to indicate if reset is awaited
*/
struct cam_ife_csid_hw_flags {
bool epd_supported;
bool device_enabled;
bool binning_enabled;
bool sof_irq_triggered;
bool process_reset;
bool fatal_err_detected;
bool rx_enabled;
bool tpg_enabled;
bool tpg_configured;
bool sfe_inline_shdr;
bool reset_awaited;
};
/*
* struct cam_ife_csid_hw_flags: place holder for flags
*
* @vc_dt: vc_dt structure
* @cid_cnt: count of cid acquired
* @num_vc_dt: num of vc dt combinaton for this cid in multi vcdt case
*/
struct cam_ife_csid_cid_data {
struct cam_ife_csid_vc_dt vc_dt[CAM_IFE_CSID_MULTI_VC_DT_GRP_MAX];
uint32_t cid_cnt;
uint32_t num_vc_dt;
};
/*
* struct cam_ife_csid_hw_flags: place holder for flags
*
* @phy_sel: selected phy
* @lane_type: type of lane selected
* @lane_num: number of lanes
* @lane_cfg: lane configuration
* @tpg_mux_sel: TPG mux sel
* @tpg_num_sel: TPG num sel
*/
struct cam_ife_csid_rx_cfg {
uint32_t phy_sel;
uint32_t lane_type;
uint32_t lane_num;
uint32_t lane_cfg;
uint32_t tpg_mux_sel;
uint32_t tpg_num_sel;
};
int cam_ife_csid_is_pix_res_format_supported(
uint32_t in_format);
int cam_ife_csid_get_format_rdi(
uint32_t in_format, uint32_t out_format,
struct cam_ife_csid_path_format *path_format, bool rpp);
int cam_ife_csid_get_format_ipp_ppp(
uint32_t in_format,
struct cam_ife_csid_path_format *path_format);
int cam_ife_csid_hw_probe_init(struct cam_hw_intf *hw_intf,
struct cam_ife_csid_core_info *core_info, bool is_custom);
int cam_ife_csid_hw_deinit(struct cam_hw_intf *hw_intf,
struct cam_ife_csid_core_info *core_info);
int cam_ife_csid_cid_reserve(struct cam_ife_csid_cid_data *cid_data,
uint32_t *cid_value,
uint32_t hw_idx,
struct cam_csid_hw_reserve_resource_args *reserve);
int cam_ife_csid_cid_release(
struct cam_ife_csid_cid_data *cid_data,
uint32_t hw_idx,
uint32_t cid);
int cam_ife_csid_check_in_port_args(
struct cam_csid_hw_reserve_resource_args *reserve,
uint32_t hw_idx);
int cam_ife_csid_set_epd_config(struct cam_ife_csid_hw_flags *flags,
void *cmd_args, uint32_t hw_idx);
int cam_ife_csid_is_vc_full_width(struct cam_ife_csid_cid_data *cid_data);
int cam_ife_csid_get_rt_irq_idx(
uint32_t irq_reg, uint32_t num_ipp,
uint32_t num_ppp, uint32_t num_rdi);
int cam_ife_csid_convert_res_to_irq_reg(uint32_t res_id);
int cam_ife_csid_get_base(struct cam_hw_soc_info *soc_info,
uint32_t base_id, void *cmd_args, size_t arg_size);
const uint8_t **cam_ife_csid_get_irq_reg_tag_ptr(void);
#endif /*_CAM_IFE_CSID_COMMON_H_ */

5694
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.c
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drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_core.h
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@@ -1,675 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
*/
#ifndef _CAM_IFE_CSID_HW_H_
#define _CAM_IFE_CSID_HW_H_
#include "cam_hw.h"
#include "cam_ife_csid_hw_intf.h"
#include "cam_ife_csid_soc.h"
#include "cam_ife_csid_core.h"
#define CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED BIT(0)
#define CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED BIT(1)
#define CSID_CSI2_RX_INFO_PHY_DL2_EOT_CAPTURED BIT(2)
#define CSID_CSI2_RX_INFO_PHY_DL3_EOT_CAPTURED BIT(3)
#define CSID_CSI2_RX_INFO_PHY_DL0_SOT_CAPTURED BIT(4)
#define CSID_CSI2_RX_INFO_PHY_DL1_SOT_CAPTURED BIT(5)
#define CSID_CSI2_RX_INFO_PHY_DL2_SOT_CAPTURED BIT(6)
#define CSID_CSI2_RX_INFO_PHY_DL3_SOT_CAPTURED BIT(7)
#define CSID_CSI2_RX_INFO_LONG_PKT_CAPTURED BIT(8)
#define CSID_CSI2_RX_INFO_SHORT_PKT_CAPTURED BIT(9)
#define CSID_CSI2_RX_INFO_CPHY_PKT_HDR_CAPTURED BIT(10)
#define CSID_CSI2_RX_ERROR_CPHY_EOT_RECEPTION BIT(11)
#define CSID_CSI2_RX_ERROR_CPHY_SOT_RECEPTION BIT(12)
#define CSID_CSI2_RX_ERROR_CPHY_PH_CRC BIT(13)
#define CSID_CSI2_RX_WARNING_ECC BIT(14)
#define CSID_CSI2_RX_ERROR_LANE0_FIFO_OVERFLOW BIT(15)
#define CSID_CSI2_RX_ERROR_LANE1_FIFO_OVERFLOW BIT(16)
#define CSID_CSI2_RX_ERROR_LANE2_FIFO_OVERFLOW BIT(17)
#define CSID_CSI2_RX_ERROR_LANE3_FIFO_OVERFLOW BIT(18)
#define CSID_CSI2_RX_ERROR_CRC BIT(19)
#define CSID_CSI2_RX_ERROR_ECC BIT(20)
#define CSID_CSI2_RX_ERROR_MMAPPED_VC_DT BIT(21)
#define CSID_CSI2_RX_ERROR_UNMAPPED_VC_DT BIT(22)
#define CSID_CSI2_RX_ERROR_STREAM_UNDERFLOW BIT(23)
#define CSID_CSI2_RX_ERROR_UNBOUNDED_FRAME BIT(24)
#define CSID_CSI2_RX_INFO_TG_DONE BIT(25)
#define CSID_CSI2_RX_ERROR_TG_FIFO_OVERFLOW BIT(26)
#define CSID_CSI2_RX_INFO_RST_DONE BIT(27)
#define CSID_TOP_IRQ_DONE BIT(0)
#define CSID_PATH_INFO_RST_DONE BIT(1)
#define CSID_PATH_ERROR_FIFO_OVERFLOW BIT(2)
#define CSID_PATH_INFO_SUBSAMPLED_EOF BIT(3)
#define CSID_PATH_INFO_SUBSAMPLED_SOF BIT(4)
#define CSID_PATH_INFO_FRAME_DROP_EOF BIT(5)
#define CSID_PATH_INFO_FRAME_DROP_EOL BIT(6)
#define CSID_PATH_INFO_FRAME_DROP_SOL BIT(7)
#define CSID_PATH_INFO_FRAME_DROP_SOF BIT(8)
#define CSID_PATH_INFO_INPUT_EOF BIT(9)
#define CSID_PATH_INFO_INPUT_EOL BIT(10)
#define CSID_PATH_INFO_INPUT_SOL BIT(11)
#define CSID_PATH_INFO_INPUT_SOF BIT(12)
#define CSID_PATH_ERROR_PIX_COUNT BIT(13)
#define CSID_PATH_ERROR_LINE_COUNT BIT(14)
#define CSID_PATH_ERROR_CCIF_VIOLATION BIT(15)
#define CSID_PATH_OVERFLOW_RECOVERY BIT(17)
/*
* Debug values enable the corresponding interrupts and debug logs provide
* necessary information
*/
#define CSID_DEBUG_ENABLE_SOF_IRQ BIT(0)
#define CSID_DEBUG_ENABLE_EOF_IRQ BIT(1)
#define CSID_DEBUG_ENABLE_SOT_IRQ BIT(2)
#define CSID_DEBUG_ENABLE_EOT_IRQ BIT(3)
#define CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE BIT(4)
#define CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE BIT(5)
#define CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE BIT(6)
#define CSID_DEBUG_ENABLE_HBI_VBI_INFO BIT(7)
#define CSID_DEBUG_DISABLE_EARLY_EOF BIT(8)
#define CSID_DEBUG_ENABLE_UNMAPPED_VC_DT_IRQ BIT(9)
#define CAM_CSID_EVT_PAYLOAD_MAX 10
#define CAM_CSID_MIN_HBI_CFG_MAX_VAL 0xF
#define CAM_CSID_RESOLUTION_22MP_WIDTH 5612
#define CAM_CSID_RESOLUTION_25MP_WIDTH 6048
#define CAM_CSID_RESOLUTION_28MP_WIDTH 7308
/* enum cam_csid_path_halt_mode select the path halt mode control */
enum cam_csid_path_halt_mode {
CSID_HALT_MODE_INTERNAL,
CSID_HALT_MODE_GLOBAL,
CSID_HALT_MODE_MASTER,
CSID_HALT_MODE_SLAVE,
};
/**
*enum cam_csid_path_timestamp_stb_sel - select the sof/eof strobes used to
* capture the timestamp
*/
enum cam_csid_path_timestamp_stb_sel {
CSID_TIMESTAMP_STB_PRE_HALT,
CSID_TIMESTAMP_STB_POST_HALT,
CSID_TIMESTAMP_STB_POST_IRQ,
CSID_TIMESTAMP_STB_MAX,
};
/**
* enum cam_ife_pix_path_res_id - Specify the csid patch
*/
enum cam_ife_csid_irq_reg {
CAM_IFE_CSID_IRQ_REG_RDI_0,
CAM_IFE_CSID_IRQ_REG_RDI_1,
CAM_IFE_CSID_IRQ_REG_RDI_2,
CAM_IFE_CSID_IRQ_REG_RDI_3,
CAM_IFE_CSID_IRQ_REG_TOP,
CAM_IFE_CSID_IRQ_REG_RX,
CAM_IFE_CSID_IRQ_REG_IPP,
CAM_IFE_CSID_IRQ_REG_PPP,
CAM_IFE_CSID_IRQ_REG_UDI_0,
CAM_IFE_CSID_IRQ_REG_UDI_1,
CAM_IFE_CSID_IRQ_REG_UDI_2,
CAM_IFE_CSID_IRQ_REG_MAX,
};
struct cam_ife_csid_pxl_reg_offset {
/* Pxl path register offsets*/
uint32_t csid_pxl_irq_status_addr;
uint32_t csid_pxl_irq_mask_addr;
uint32_t csid_pxl_irq_clear_addr;
uint32_t csid_pxl_irq_set_addr;
uint32_t csid_pxl_cfg0_addr;
uint32_t csid_pxl_cfg1_addr;
uint32_t csid_pxl_ctrl_addr;
uint32_t csid_pxl_frm_drop_pattern_addr;
uint32_t csid_pxl_frm_drop_period_addr;
uint32_t csid_pxl_irq_subsample_pattern_addr;
uint32_t csid_pxl_irq_subsample_period_addr;
uint32_t csid_pxl_hcrop_addr;
uint32_t csid_pxl_vcrop_addr;
uint32_t csid_pxl_pix_drop_pattern_addr;
uint32_t csid_pxl_pix_drop_period_addr;
uint32_t csid_pxl_line_drop_pattern_addr;
uint32_t csid_pxl_line_drop_period_addr;
uint32_t csid_pxl_rst_strobes_addr;
uint32_t csid_pxl_status_addr;
uint32_t csid_pxl_misr_val_addr;
uint32_t csid_pxl_format_measure_cfg0_addr;
uint32_t csid_pxl_format_measure_cfg1_addr;
uint32_t csid_pxl_format_measure0_addr;
uint32_t csid_pxl_format_measure1_addr;
uint32_t csid_pxl_format_measure2_addr;
uint32_t csid_pxl_timestamp_curr0_sof_addr;
uint32_t csid_pxl_timestamp_curr1_sof_addr;
uint32_t csid_pxl_timestamp_perv0_sof_addr;
uint32_t csid_pxl_timestamp_perv1_sof_addr;
uint32_t csid_pxl_timestamp_curr0_eof_addr;
uint32_t csid_pxl_timestamp_curr1_eof_addr;
uint32_t csid_pxl_timestamp_perv0_eof_addr;
uint32_t csid_pxl_timestamp_perv1_eof_addr;
uint32_t csid_pxl_err_recovery_cfg0_addr;
uint32_t csid_pxl_err_recovery_cfg1_addr;
uint32_t csid_pxl_err_recovery_cfg2_addr;
uint32_t csid_pxl_multi_vcdt_cfg0_addr;
/* configuration */
uint32_t pix_store_en_shift_val;
uint32_t early_eof_en_shift_val;
uint32_t horizontal_bin_en_shift_val;
uint32_t quad_cfa_bin_en_shift_val;
uint32_t ccif_violation_en;
uint32_t overflow_ctrl_en;
uint32_t hblank_cfg_shift_val;
uint32_t halt_master_sel_en;
uint32_t halt_sel_internal_master_val;
};
struct cam_ife_csid_rdi_reg_offset {
uint32_t csid_rdi_irq_status_addr;
uint32_t csid_rdi_irq_mask_addr;
uint32_t csid_rdi_irq_clear_addr;
uint32_t csid_rdi_irq_set_addr;
/*RDI N register address */
uint32_t csid_rdi_cfg0_addr;
uint32_t csid_rdi_cfg1_addr;
uint32_t csid_rdi_ctrl_addr;
uint32_t csid_rdi_frm_drop_pattern_addr;
uint32_t csid_rdi_frm_drop_period_addr;
uint32_t csid_rdi_irq_subsample_pattern_addr;
uint32_t csid_rdi_irq_subsample_period_addr;
uint32_t csid_rdi_rpp_hcrop_addr;
uint32_t csid_rdi_rpp_vcrop_addr;
uint32_t csid_rdi_rpp_pix_drop_pattern_addr;
uint32_t csid_rdi_rpp_pix_drop_period_addr;
uint32_t csid_rdi_rpp_line_drop_pattern_addr;
uint32_t csid_rdi_rpp_line_drop_period_addr;
uint32_t csid_rdi_yuv_chroma_conversion_addr;
uint32_t csid_rdi_rst_strobes_addr;
uint32_t csid_rdi_status_addr;
uint32_t csid_rdi_misr_val0_addr;
uint32_t csid_rdi_misr_val1_addr;
uint32_t csid_rdi_misr_val2_addr;
uint32_t csid_rdi_misr_val3_addr;
uint32_t csid_rdi_format_measure_cfg0_addr;
uint32_t csid_rdi_format_measure_cfg1_addr;
uint32_t csid_rdi_format_measure0_addr;
uint32_t csid_rdi_format_measure1_addr;
uint32_t csid_rdi_format_measure2_addr;
uint32_t csid_rdi_timestamp_curr0_sof_addr;
uint32_t csid_rdi_timestamp_curr1_sof_addr;
uint32_t csid_rdi_timestamp_prev0_sof_addr;
uint32_t csid_rdi_timestamp_prev1_sof_addr;
uint32_t csid_rdi_timestamp_curr0_eof_addr;
uint32_t csid_rdi_timestamp_curr1_eof_addr;
uint32_t csid_rdi_timestamp_prev0_eof_addr;
uint32_t csid_rdi_timestamp_prev1_eof_addr;
uint32_t csid_rdi_err_recovery_cfg0_addr;
uint32_t csid_rdi_err_recovery_cfg1_addr;
uint32_t csid_rdi_err_recovery_cfg2_addr;
uint32_t csid_rdi_multi_vcdt_cfg0_addr;
uint32_t csid_rdi_byte_cntr_ping_addr;
uint32_t csid_rdi_byte_cntr_pong_addr;
/* configuration */
uint32_t packing_format;
uint32_t ccif_violation_en;
uint32_t overflow_ctrl_en;
};
struct cam_ife_csid_udi_reg_offset {
uint32_t csid_udi_irq_status_addr;
uint32_t csid_udi_irq_mask_addr;
uint32_t csid_udi_irq_clear_addr;
uint32_t csid_udi_irq_set_addr;
/* UDI N register address */
uint32_t csid_udi_cfg0_addr;
uint32_t csid_udi_cfg1_addr;
uint32_t csid_udi_ctrl_addr;
uint32_t csid_udi_frm_drop_pattern_addr;
uint32_t csid_udi_frm_drop_period_addr;
uint32_t csid_udi_irq_subsample_pattern_addr;
uint32_t csid_udi_irq_subsample_period_addr;
uint32_t csid_udi_rpp_hcrop_addr;
uint32_t csid_udi_rpp_vcrop_addr;
uint32_t csid_udi_rpp_pix_drop_pattern_addr;
uint32_t csid_udi_rpp_pix_drop_period_addr;
uint32_t csid_udi_rpp_line_drop_pattern_addr;
uint32_t csid_udi_rpp_line_drop_period_addr;
uint32_t csid_udi_yuv_chroma_conversion_addr;
uint32_t csid_udi_rst_strobes_addr;
uint32_t csid_udi_status_addr;
uint32_t csid_udi_misr_val0_addr;
uint32_t csid_udi_misr_val1_addr;
uint32_t csid_udi_misr_val2_addr;
uint32_t csid_udi_misr_val3_addr;
uint32_t csid_udi_format_measure_cfg0_addr;
uint32_t csid_udi_format_measure_cfg1_addr;
uint32_t csid_udi_format_measure0_addr;
uint32_t csid_udi_format_measure1_addr;
uint32_t csid_udi_format_measure2_addr;
uint32_t csid_udi_timestamp_curr0_sof_addr;
uint32_t csid_udi_timestamp_curr1_sof_addr;
uint32_t csid_udi_timestamp_prev0_sof_addr;
uint32_t csid_udi_timestamp_prev1_sof_addr;
uint32_t csid_udi_timestamp_curr0_eof_addr;
uint32_t csid_udi_timestamp_curr1_eof_addr;
uint32_t csid_udi_timestamp_prev0_eof_addr;
uint32_t csid_udi_timestamp_prev1_eof_addr;
uint32_t csid_udi_err_recovery_cfg0_addr;
uint32_t csid_udi_err_recovery_cfg1_addr;
uint32_t csid_udi_err_recovery_cfg2_addr;
uint32_t csid_udi_multi_vcdt_cfg0_addr;
uint32_t csid_udi_byte_cntr_ping_addr;
uint32_t csid_udi_byte_cntr_pong_addr;
/* configuration */
uint32_t packing_format;
uint32_t ccif_violation_en;
uint32_t overflow_ctrl_en;
};
struct cam_ife_csid_csi2_rx_reg_offset {
uint32_t csid_csi2_rx_irq_status_addr;
uint32_t csid_csi2_rx_irq_mask_addr;
uint32_t csid_csi2_rx_irq_clear_addr;
uint32_t csid_csi2_rx_irq_set_addr;
uint32_t csid_csi2_rx_cfg0_addr;
uint32_t csid_csi2_rx_cfg1_addr;
uint32_t csid_csi2_rx_capture_ctrl_addr;
uint32_t csid_csi2_rx_rst_strobes_addr;
uint32_t csid_csi2_rx_de_scramble_cfg0_addr;
uint32_t csid_csi2_rx_de_scramble_cfg1_addr;
uint32_t csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr;
uint32_t csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr;
uint32_t csid_csi2_rx_captured_short_pkt_0_addr;
uint32_t csid_csi2_rx_captured_short_pkt_1_addr;
uint32_t csid_csi2_rx_captured_long_pkt_0_addr;
uint32_t csid_csi2_rx_captured_long_pkt_1_addr;
uint32_t csid_csi2_rx_captured_long_pkt_ftr_addr;
uint32_t csid_csi2_rx_captured_cphy_pkt_hdr_addr;
uint32_t csid_csi2_rx_lane0_misr_addr;
uint32_t csid_csi2_rx_lane1_misr_addr;
uint32_t csid_csi2_rx_lane2_misr_addr;
uint32_t csid_csi2_rx_lane3_misr_addr;
uint32_t csid_csi2_rx_total_pkts_rcvd_addr;
uint32_t csid_csi2_rx_stats_ecc_addr;
uint32_t csid_csi2_rx_total_crc_err_addr;
uint32_t csid_csi2_rx_de_scramble_type3_cfg0_addr;
uint32_t csid_csi2_rx_de_scramble_type3_cfg1_addr;
uint32_t csid_csi2_rx_de_scramble_type2_cfg0_addr;
uint32_t csid_csi2_rx_de_scramble_type2_cfg1_addr;
uint32_t csid_csi2_rx_de_scramble_type1_cfg0_addr;
uint32_t csid_csi2_rx_de_scramble_type1_cfg1_addr;
uint32_t csid_csi2_rx_de_scramble_type0_cfg0_addr;
uint32_t csid_csi2_rx_de_scramble_type0_cfg1_addr;
/*configurations */
uint32_t csi2_rst_srb_all;
uint32_t csi2_rst_done_shift_val;
uint32_t csi2_irq_mask_all;
uint32_t csi2_misr_enable_shift_val;
uint32_t csi2_vc_mode_shift_val;
uint32_t csi2_capture_long_pkt_en_shift;
uint32_t csi2_capture_short_pkt_en_shift;
uint32_t csi2_capture_cphy_pkt_en_shift;
uint32_t csi2_capture_long_pkt_dt_shift;
uint32_t csi2_capture_long_pkt_vc_shift;
uint32_t csi2_capture_short_pkt_vc_shift;
uint32_t csi2_capture_cphy_pkt_dt_shift;
uint32_t csi2_capture_cphy_pkt_vc_shift;
uint32_t csi2_rx_phy_num_mask;
};
struct cam_ife_csid_csi2_tpg_reg_offset {
uint32_t csid_tpg_ctrl_addr;
uint32_t csid_tpg_vc_cfg0_addr;
uint32_t csid_tpg_vc_cfg1_addr;
uint32_t csid_tpg_lfsr_seed_addr;
uint32_t csid_tpg_dt_n_cfg_0_addr;
uint32_t csid_tpg_dt_n_cfg_1_addr;
uint32_t csid_tpg_dt_n_cfg_2_addr;
uint32_t csid_tpg_color_bars_cfg_addr;
uint32_t csid_tpg_color_box_cfg_addr;
uint32_t csid_tpg_common_gen_cfg_addr;
uint32_t csid_tpg_cgen_n_cfg_addr;
uint32_t csid_tpg_cgen_n_x0_addr;
uint32_t csid_tpg_cgen_n_x1_addr;
uint32_t csid_tpg_cgen_n_x2_addr;
uint32_t csid_tpg_cgen_n_xy_addr;
uint32_t csid_tpg_cgen_n_y1_addr;
uint32_t csid_tpg_cgen_n_y2_addr;
/*configurations */
uint32_t tpg_dtn_cfg_offset;
uint32_t tpg_cgen_cfg_offset;
uint32_t tpg_cpas_ife_reg_offset;
};
struct cam_ife_csid_common_reg_offset {
/* MIPI CSID registers */
uint32_t csid_hw_version_addr;
uint32_t csid_cfg0_addr;
uint32_t csid_ctrl_addr;
uint32_t csid_reset_addr;
uint32_t csid_rst_strobes_addr;
uint32_t csid_test_bus_ctrl_addr;
uint32_t csid_top_irq_status_addr;
uint32_t csid_top_irq_mask_addr;
uint32_t csid_top_irq_clear_addr;
uint32_t csid_top_irq_set_addr;
uint32_t csid_irq_cmd_addr;
/*configurations */
uint32_t major_version;
uint32_t minor_version;
uint32_t version_incr;
uint32_t num_udis;
uint32_t num_rdis;
uint32_t num_pix;
uint32_t num_ppp;
uint32_t csid_reg_rst_stb;
uint32_t csid_rst_stb;
uint32_t csid_rst_stb_sw_all;
uint32_t path_rst_stb_all;
uint32_t path_rst_done_shift_val;
uint32_t path_en_shift_val;
uint32_t packing_fmt_shift_val;
uint32_t dt_id_shift_val;
uint32_t vc_shift_val;
uint32_t dt_shift_val;
uint32_t fmt_shift_val;
uint32_t plain_fmt_shit_val;
uint32_t crop_v_en_shift_val;
uint32_t crop_h_en_shift_val;
uint32_t drop_v_en_shift_val;
uint32_t drop_h_en_shift_val;
uint32_t crop_shift;
uint32_t ipp_irq_mask_all;
uint32_t rdi_irq_mask_all;
uint32_t ppp_irq_mask_all;
uint32_t udi_irq_mask_all;
uint32_t measure_en_hbi_vbi_cnt_mask;
uint32_t format_measure_en_val;
uint32_t num_bytes_out_shift_val;
uint32_t format_measure_width_shift_val;
uint32_t format_measure_width_mask_val;
uint32_t format_measure_height_shift_val;
uint32_t format_measure_height_mask_val;
};
/**
* struct cam_ife_csid_reg_offset- CSID instance register info
*
* @cmn_reg: csid common registers info
* @ipp_reg: ipp register offset information
* @ppp_reg: ppp register offset information
* @rdi_reg: rdi register offset information
* @udi_reg: udi register offset information
* @tpg_reg: tpg register offset information
*
*/
struct cam_ife_csid_reg_offset {
const struct cam_ife_csid_common_reg_offset *cmn_reg;
const struct cam_ife_csid_csi2_rx_reg_offset *csi2_reg;
const struct cam_ife_csid_pxl_reg_offset *ipp_reg;
const struct cam_ife_csid_pxl_reg_offset *ppp_reg;
const struct cam_ife_csid_rdi_reg_offset *rdi_reg[CAM_IFE_CSID_RDI_MAX];
const struct cam_ife_csid_udi_reg_offset *udi_reg[CAM_IFE_CSID_UDI_MAX];
const struct cam_ife_csid_csi2_tpg_reg_offset *tpg_reg;
};
/**
* struct cam_ife_csid_hw_info- CSID HW info
*
* @csid_reg: csid register offsets
* @hw_dts_version: HW DTS version
* @hw_reg_version: HW Version read from register
* @csid_max_clk: maximim csid clock
*
*/
struct cam_ife_csid_hw_info {
const struct cam_ife_csid_reg_offset *csid_reg;
uint32_t hw_dts_version;
uint32_t hw_reg_version;
uint32_t csid_max_clk;
};
/**
* struct cam_ife_csid_csi2_rx_cfg- csid csi2 rx configuration data
* @phy_sel: input resource type for sensor only
* @lane_type: lane type: c-phy or d-phy
* @lane_num : active lane number
* @lane_cfg: lane configurations: 4 bits per lane
*
*/
struct cam_ife_csid_csi2_rx_cfg {
uint32_t phy_sel;
uint32_t lane_type;
uint32_t lane_num;
uint32_t lane_cfg;
};
/**
* struct cam_ife_csid_tpg_cfg- csid tpg configuration data
* @width: width
* @height: height
* @test_pattern : pattern
* @in_format: decode format
* @usage_type: whether dual isp is required
*
*/
struct cam_ife_csid_tpg_cfg {
uint32_t width;
uint32_t height;
uint32_t test_pattern;
uint32_t in_format;
uint32_t usage_type;
};
/**
* struct cam_ife_csid_cid_data- cid configuration private data
*
* @vc: Virtual channel
* @dt: Data type
* @cnt: Cid resource reference count.
* @tpg_set: Tpg used for this cid resource
* @is_valid_vc1_dt1: Valid vc1 and dt1
*
*/
struct cam_ife_csid_cid_data {
uint32_t vc;
uint32_t dt;
uint32_t vc1;
uint32_t dt1;
uint32_t cnt;
uint32_t tpg_set;
uint32_t is_valid_vc1_dt1;
};
/**
* struct cam_ife_csid_path_cfg- csid path configuration details. It is stored
* as private data for IPP/ RDI paths
* @vc : Virtual channel number
* @dt : Data type number
* @cid cid number, it is same as DT_ID number in HW
* @in_format: input decode format
* @out_format: output format
* @crop_enable: crop is enable or disabled, if enabled
* then remaining parameters are valid.
* @drop_enable: flag to indicate pixel drop enable or disable
* @start_pixel: start pixel
* @end_pixel: end_pixel
* @width: width
* @start_line: start line
* @end_line: end_line
* @height: heigth
* @sync_mode: Applicable for IPP/RDI path reservation
* Reserving the path for master IPP or slave IPP
* master (set value 1), Slave ( set value 2)
* for RDI, set mode to none
* @master_idx: For Slave reservation, Give master IFE instance Index.
* Slave will synchronize with master Start and stop operations
* @clk_rate Clock rate
* @num_bytes_out: Number of output bytes per cycle
* @hblank_cnt: HBI count
*
*/
struct cam_ife_csid_path_cfg {
uint32_t vc;
uint32_t dt;
uint32_t vc1;
uint32_t dt1;
uint32_t is_valid_vc1_dt1;
uint32_t cid;
uint32_t in_format;
uint32_t out_format;
bool crop_enable;
bool drop_enable;
uint32_t start_pixel;
uint32_t end_pixel;
uint32_t width;
uint32_t start_line;
uint32_t end_line;
uint32_t height;
enum cam_isp_hw_sync_mode sync_mode;
uint32_t master_idx;
uint64_t clk_rate;
uint32_t horizontal_bin;
uint32_t qcfa_bin;
uint32_t num_bytes_out;
uint32_t hblank_cnt;
};
/**
* struct cam_csid_evt_payload- payload for csid hw event
* @list : list head
* @evt_type : Event type from CSID
* @irq_status : IRQ Status register
* @hw_idx : Hw index
* @priv : Private data of payload
*/
struct cam_csid_evt_payload {
struct list_head list;
uint32_t evt_type;
uint32_t irq_status[CAM_IFE_CSID_IRQ_REG_MAX];
uint32_t hw_idx;
void *priv;
};
/**
* struct cam_ife_csid_hw- csid hw device resources data
*
* @hw_intf: contain the csid hw interface information
* @hw_info: csid hw device information
* @csid_info: csid hw specific information
* @tasklet: tasklet to handle csid errors
* @priv: private data to be sent with callback
* @free_payload_list: list head for payload
* @evt_payload: Event payload to be passed to tasklet
* @res_type: CSID in resource type
* @csi2_rx_cfg: Csi2 rx decoder configuration for csid
* @tpg_cfg: TPG configuration
* @csi2_rx_reserve_cnt: CSI2 reservations count value
* @csi2_cfg_cnt: csi2 configuration count
* @tpg_start_cnt: tpg start count
* @ipp_res: image pixel path resource
* @ppp_res: phase pxl path resource
* @rdi_res: raw dump image path resources
* @udi_res: udi path resources
* @cid_res: cid resources state
* @csid_top_reset_complete: csid top reset completion
* @csid_csi2_reset_complete: csi2 reset completion
* @csid_ipp_reset_complete: ipp reset completion
* @csid_ppp_complete: ppp reset completion
* @csid_rdin_reset_complete: rdi n completion
* @csid_udin_reset_complete: udi n completion
* @csid_debug: csid debug information to enable the SOT, EOT,
* SOF, EOF, measure etc in the csid hw
* @clk_rate Clock rate
* @sof_irq_triggered: Flag is set on receiving event to enable sof irq
* incase of SOF freeze.
* @is_resetting: informs whether reset is started or not.
* @irq_debug_cnt: Counter to track sof irq's when above flag is set.
* @error_irq_count Error IRQ count, if continuous error irq comes
* need to stop the CSID and mask interrupts.
* @binning_enable Flag is set if hardware supports QCFA binning
* @binning_supported Flag is set if sensor supports QCFA binning
* @first_sof_ts first bootime stamp at the start
* @prev_qtimer_ts stores csid timestamp
* @epd_supported Flag is set if sensor supports EPD
* @fatal_err_detected flag to indicate fatal errror is reported
* @event_cb Callback to hw manager if CSID event reported
*/
struct cam_ife_csid_hw {
struct cam_hw_intf *hw_intf;
struct cam_hw_info *hw_info;
struct cam_ife_csid_hw_info *csid_info;
void *tasklet;
void *priv;
struct list_head free_payload_list;
struct cam_csid_evt_payload evt_payload[CAM_CSID_EVT_PAYLOAD_MAX];
uint32_t res_type;
struct cam_ife_csid_csi2_rx_cfg csi2_rx_cfg;
struct cam_ife_csid_tpg_cfg tpg_cfg;
uint32_t csi2_reserve_cnt;
uint32_t csi2_cfg_cnt;
uint32_t tpg_start_cnt;
struct cam_isp_resource_node ipp_res;
struct cam_isp_resource_node ppp_res;
struct cam_isp_resource_node rdi_res[CAM_IFE_CSID_RDI_MAX];
struct cam_isp_resource_node udi_res[CAM_IFE_CSID_UDI_MAX];
struct cam_isp_resource_node cid_res[CAM_IFE_CSID_CID_MAX];
struct completion csid_top_complete;
struct completion csid_csi2_complete;
struct completion csid_ipp_complete;
struct completion csid_ppp_complete;
struct completion csid_rdin_complete[CAM_IFE_CSID_RDI_MAX];
struct completion csid_udin_complete[CAM_IFE_CSID_UDI_MAX];
uint64_t csid_debug;
uint64_t clk_rate;
struct cam_isp_sensor_dimension ipp_path_config;
struct cam_isp_sensor_dimension ppp_path_config;
struct cam_isp_sensor_dimension rdi_path_config[CAM_IFE_CSID_RDI_MAX];
uint32_t hbi;
uint32_t vbi;
bool sof_irq_triggered;
bool is_resetting;
uint32_t irq_debug_cnt;
uint32_t error_irq_count;
uint32_t device_enabled;
spinlock_t lock_state;
uint32_t binning_enable;
uint32_t binning_supported;
uint64_t prev_boot_timestamp;
uint64_t prev_qtimer_ts;
uint32_t epd_supported;
bool fatal_err_detected;
cam_hw_mgr_event_cb_func event_cb;
};
int cam_ife_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf,
uint32_t csid_idx, bool is_custom);
int cam_ife_csid_hw_deinit(struct cam_ife_csid_hw *ife_csid_hw);
int cam_ife_csid_cid_reserve(struct cam_ife_csid_hw *csid_hw,
struct cam_csid_hw_reserve_resource_args *cid_reserv);
int cam_ife_csid_path_reserve(struct cam_ife_csid_hw *csid_hw,
struct cam_csid_hw_reserve_resource_args *reserve);
#endif /* _CAM_IFE_CSID_HW_H_ */

101
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_dev.c
View File

@@ -6,7 +6,7 @@
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/mod_devicetable.h> #include <linux/mod_devicetable.h>
#include <linux/of_device.h> #include <linux/of_device.h>
#include "cam_ife_csid_core.h" #include "cam_ife_csid_common.h"
#include "cam_ife_csid_dev.h" #include "cam_ife_csid_dev.h"
#include "cam_ife_csid_hw_intf.h" #include "cam_ife_csid_hw_intf.h"
#include "cam_debug_util.h" #include "cam_debug_util.h"
@@ -20,35 +20,28 @@ static char csid_dev_name[8];
static int cam_ife_csid_component_bind(struct device *dev, static int cam_ife_csid_component_bind(struct device *dev,
struct device *master_dev, void *data) struct device *master_dev, void *data)
{ {
struct cam_hw_intf *csid_hw_intf; struct cam_hw_intf *hw_intf;
struct cam_hw_info *csid_hw_info; struct cam_hw_info *hw_info;
struct cam_ife_csid_hw *csid_dev = NULL;
const struct of_device_id *match_dev = NULL; const struct of_device_id *match_dev = NULL;
struct cam_ife_csid_hw_info *csid_hw_data = NULL; struct cam_ife_csid_core_info *csid_core_info = NULL;
uint32_t csid_dev_idx; uint32_t csid_dev_idx;
int rc = 0; int rc = 0;
struct platform_device *pdev = to_platform_device(dev); struct platform_device *pdev = to_platform_device(dev);
CAM_DBG(CAM_ISP, "Binding IFE CSID component"); CAM_DBG(CAM_ISP, "Binding IFE CSID component");
csid_hw_intf = kzalloc(sizeof(*csid_hw_intf), GFP_KERNEL); hw_intf = kzalloc(sizeof(*hw_intf), GFP_KERNEL);
if (!csid_hw_intf) { if (!hw_intf) {
rc = -ENOMEM; rc = -ENOMEM;
goto err; goto err;
} }
csid_hw_info = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL); hw_info = kzalloc(sizeof(struct cam_hw_info), GFP_KERNEL);
if (!csid_hw_info) { if (!hw_info) {
rc = -ENOMEM; rc = -ENOMEM;
goto free_hw_intf; goto free_hw_intf;
} }
csid_dev = kzalloc(sizeof(struct cam_ife_csid_hw), GFP_KERNEL);
if (!csid_dev) {
rc = -ENOMEM;
goto free_hw_info;
}
/* get ife csid hw index */ /* get ife csid hw index */
of_property_read_u32(pdev->dev.of_node, "cell-index", &csid_dev_idx); of_property_read_u32(pdev->dev.of_node, "cell-index", &csid_dev_idx);
/* get ife csid hw information */ /* get ife csid hw information */
@@ -57,49 +50,49 @@ static int cam_ife_csid_component_bind(struct device *dev,
if (!match_dev) { if (!match_dev) {
CAM_ERR(CAM_ISP, "No matching table for the IFE CSID HW!"); CAM_ERR(CAM_ISP, "No matching table for the IFE CSID HW!");
rc = -EINVAL; rc = -EINVAL;
goto free_dev; goto free_hw_info;
} }
memset(csid_dev_name, 0, sizeof(csid_dev_name)); memset(csid_dev_name, 0, sizeof(csid_dev_name));
snprintf(csid_dev_name, sizeof(csid_dev_name), snprintf(csid_dev_name, sizeof(csid_dev_name),
"csid%1u", csid_dev_idx); "csid%1u", csid_dev_idx);
csid_hw_intf->hw_idx = csid_dev_idx; hw_intf->hw_idx = csid_dev_idx;
csid_hw_intf->hw_type = CAM_ISP_HW_TYPE_IFE_CSID; hw_intf->hw_type = CAM_ISP_HW_TYPE_IFE_CSID;
csid_hw_intf->hw_priv = csid_hw_info; hw_intf->hw_priv = hw_info;
csid_hw_info->core_info = csid_dev; hw_info->soc_info.pdev = pdev;
csid_hw_info->soc_info.pdev = pdev; hw_info->soc_info.dev = &pdev->dev;
csid_hw_info->soc_info.dev = &pdev->dev; hw_info->soc_info.dev_name = csid_dev_name;
csid_hw_info->soc_info.dev_name = csid_dev_name; hw_info->soc_info.index = csid_dev_idx;
csid_hw_info->soc_info.index = csid_dev_idx;
csid_hw_data = (struct cam_ife_csid_hw_info *)match_dev->data; csid_core_info = (struct cam_ife_csid_core_info *)match_dev->data;
/* need to setup the pdev before call the ife hw probe init */
csid_dev->csid_info = csid_hw_data;
rc = cam_ife_csid_hw_probe_init(csid_hw_intf, csid_dev_idx, false); /* call the driver init and fill csid_hw_info->core_info */
if (rc) rc = cam_ife_csid_hw_probe_init(hw_intf, csid_core_info, false);
goto free_dev;
platform_set_drvdata(pdev, csid_dev); if (rc) {
CAM_ERR(CAM_ISP, "CSID[%d] probe init failed",
csid_dev_idx);
goto free_hw_info;
}
platform_set_drvdata(pdev, hw_intf);
CAM_DBG(CAM_ISP, "CSID:%d component bound successfully", CAM_DBG(CAM_ISP, "CSID:%d component bound successfully",
csid_hw_intf->hw_idx); hw_intf->hw_idx);
if (csid_hw_intf->hw_idx < CAM_IFE_CSID_HW_NUM_MAX) if (hw_intf->hw_idx < CAM_IFE_CSID_HW_NUM_MAX)
cam_ife_csid_hw_list[csid_hw_intf->hw_idx] = csid_hw_intf; cam_ife_csid_hw_list[hw_intf->hw_idx] = hw_intf;
else else
goto free_dev; goto free_hw_info;
return 0; return 0;
free_dev:
kfree(csid_dev);
free_hw_info: free_hw_info:
kfree(csid_hw_info); kfree(hw_info);
free_hw_intf: free_hw_intf:
kfree(csid_hw_intf); kfree(hw_intf);
err: err:
return rc; return rc;
} }
@@ -107,24 +100,30 @@ err:
static void cam_ife_csid_component_unbind(struct device *dev, static void cam_ife_csid_component_unbind(struct device *dev,
struct device *master_dev, void *data) struct device *master_dev, void *data)
{ {
struct cam_ife_csid_hw *csid_dev = NULL; struct cam_hw_intf *hw_intf;
struct cam_hw_intf *csid_hw_intf; struct cam_hw_info *hw_info;
struct cam_hw_info *csid_hw_info; struct cam_ife_csid_core_info *core_info = NULL;
struct platform_device *pdev = to_platform_device(dev); struct platform_device *pdev = to_platform_device(dev);
const struct of_device_id *match_dev = NULL;
csid_dev = (struct cam_ife_csid_hw *)platform_get_drvdata(pdev); hw_intf = (struct cam_hw_intf *)platform_get_drvdata(pdev);
csid_hw_intf = csid_dev->hw_intf; hw_info = hw_intf->hw_priv;
csid_hw_info = csid_dev->hw_info;
CAM_DBG(CAM_ISP, "CSID:%d component unbind", CAM_DBG(CAM_ISP, "CSID:%d component unbind",
csid_dev->hw_intf->hw_idx); hw_intf->hw_idx);
match_dev = of_match_device(pdev->dev.driver->of_match_table,
&pdev->dev);
cam_ife_csid_hw_deinit(csid_dev); if (!match_dev) {
CAM_ERR(CAM_ISP, "No matching table for the IFE CSID HW!");
goto free_mem;
}
cam_ife_csid_hw_deinit(hw_intf, core_info);
free_mem:
/*release the csid device memory */ /*release the csid device memory */
kfree(csid_dev); kfree(hw_info);
kfree(csid_hw_info); kfree(hw_intf);
kfree(csid_hw_intf);
} }
const static struct component_ops cam_ife_csid_component_ops = { const static struct component_ops cam_ife_csid_component_ops = {

6
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_dev.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
*/ */
#ifndef _CAM_IFE_CSID_DEV_H_ #ifndef _CAM_IFE_CSID_DEV_H_
@@ -17,7 +17,7 @@ int cam_ife_csid_remove(struct platform_device *pdev);
* @brief : API to register CSID hw to platform framework. * @brief : API to register CSID hw to platform framework.
* @return struct platform_device pointer on on success, or ERR_PTR() on error. * @return struct platform_device pointer on on success, or ERR_PTR() on error.
*/ */
int cam_ife_csid17x_init_module(void); int cam_ife_csid_init_module(void);
/** /**
* @brief : API to register CSID Lite hw to platform framework. * @brief : API to register CSID Lite hw to platform framework.
@@ -28,7 +28,7 @@ int cam_ife_csid_lite_init_module(void);
/** /**
* @brief : API to remove CSID Hw from platform framework. * @brief : API to remove CSID Hw from platform framework.
*/ */
void cam_ife_csid17x_exit_module(void); void cam_ife_csid_exit_module(void);
/** /**
* @brief : API to remove CSID Lite Hw from platform framework. * @brief : API to remove CSID Lite Hw from platform framework.

4643
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver1.c Normal file
View File

File diff suppressed because it is too large Load Diff

457
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver1.h Normal file
View File

@@ -0,0 +1,457 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef _CAM_IFE_CSID_HW_VER1_H_
#define _CAM_IFE_CSID_HW_VER1_H_
#define IFE_CSID_VER1_RX_DL0_EOT_CAPTURED BIT(0)
#define IFE_CSID_VER1_RX_DL1_EOT_CAPTURED BIT(1)
#define IFE_CSID_VER1_RX_DL2_EOT_CAPTURED BIT(2)
#define IFE_CSID_VER1_RX_DL3_EOT_CAPTURED BIT(3)
#define IFE_CSID_VER1_RX_DL0_SOT_CAPTURED BIT(4)
#define IFE_CSID_VER1_RX_DL1_SOT_CAPTURED BIT(5)
#define IFE_CSID_VER1_RX_DL2_SOT_CAPTURED BIT(6)
#define IFE_CSID_VER1_RX_DL3_SOT_CAPTURED BIT(7)
#define IFE_CSID_VER1_RX_LONG_PKT_CAPTURED BIT(8)
#define IFE_CSID_VER1_RX_SHORT_PKT_CAPTURED BIT(9)
#define IFE_CSID_VER1_RX_CPHY_PKT_HDR_CAPTURED BIT(10)
#define IFE_CSID_VER1_RX_CPHY_EOT_RECEPTION BIT(11)
#define IFE_CSID_VER1_RX_CPHY_SOT_RECEPTION BIT(12)
#define IFE_CSID_VER1_RX_CPHY_PH_CRC BIT(13)
#define IFE_CSID_VER1_RX_WARNING_ECC BIT(14)
#define IFE_CSID_VER1_RX_LANE0_FIFO_OVERFLOW BIT(15)
#define IFE_CSID_VER1_RX_LANE1_FIFO_OVERFLOW BIT(16)
#define IFE_CSID_VER1_RX_LANE2_FIFO_OVERFLOW BIT(17)
#define IFE_CSID_VER1_RX_LANE3_FIFO_OVERFLOW BIT(18)
#define IFE_CSID_VER1_RX_CRC BIT(19)
#define IFE_CSID_VER1_RX_ERROR_ECC BIT(20)
#define IFE_CSID_VER1_RX_MMAPPED_VC_DT BIT(21)
#define IFE_CSID_VER1_RX_UNMAPPED_VC_DT BIT(22)
#define IFE_CSID_VER1_RX_STREAM_UNDERFLOW BIT(23)
#define IFE_CSID_VER1_RX_UNBOUNDED_FRAME BIT(24)
#define IFE_CSID_VER1_RX_TG_DONE BIT(25)
#define IFE_CSID_VER1_RX_TG_FIFO_OVERFLOW BIT(26)
#define IFE_CSID_VER1_RX_RST_DONE BIT(27)
#define IFE_CSID_VER1_TOP_IRQ_DONE BIT(0)
#define IFE_CSID_VER1_PATH_INFO_RST_DONE BIT(1)
#define IFE_CSID_VER1_PATH_ERROR_FIFO_OVERFLOW BIT(2)
#define IFE_CSID_VER1_PATH_INFO_SUBSAMPLED_EOF BIT(3)
#define IFE_CSID_VER1_PATH_INFO_SUBSAMPLED_SOF BIT(4)
#define IFE_CSID_VER1_PATH_INFO_FRAME_DROP_EOF BIT(5)
#define IFE_CSID_VER1_PATH_INFO_FRAME_DROP_EOL BIT(6)
#define IFE_CSID_VER1_PATH_INFO_FRAME_DROP_SOL BIT(7)
#define IFE_CSID_VER1_PATH_INFO_FRAME_DROP_SOF BIT(8)
#define IFE_CSID_VER1_PATH_INFO_INPUT_EOF BIT(9)
#define IFE_CSID_VER1_PATH_INFO_INPUT_EOL BIT(10)
#define IFE_CSID_VER1_PATH_INFO_INPUT_SOL BIT(11)
#define IFE_CSID_VER1_PATH_INFO_INPUT_SOF BIT(12)
#define IFE_CSID_VER1_PATH_ERROR_PIX_COUNT BIT(13)
#define IFE_CSID_VER1_PATH_ERROR_LINE_COUNT BIT(14)
#define IFE_CSID_VER1_PATH_ERROR_CCIF_VIOLATION BIT(15)
#define IFE_CSID_VER1_PATH_OVERFLOW_RECOVERY BIT(17)
#define CAM_IFE_CSID_VER1_EVT_PAYLOAD_MAX 256
/*
* struct cam_ife_csid_ver1_common_reg_info: Structure to hold Common info
* holds register address offsets
* shift values
* masks
*/
struct cam_ife_csid_ver1_common_reg_info {
/* MIPI CSID registers */
uint32_t hw_version_addr;
uint32_t cfg0_addr;
uint32_t ctrl_addr;
uint32_t reset_addr;
uint32_t rst_strobes_addr;
uint32_t test_bus_ctrl_addr;
uint32_t top_irq_status_addr;
uint32_t top_irq_mask_addr;
uint32_t top_irq_clear_addr;
uint32_t top_irq_set_addr;
uint32_t irq_cmd_addr;
/*Shift Bit Configurations*/
uint32_t rst_done_shift_val;
uint32_t timestamp_stb_sel_shift_val;
uint32_t decode_format_shift_val;
uint32_t path_en_shift_val;
uint32_t dt_id_shift_val;
uint32_t vc_shift_val;
uint32_t dt_shift_val;
uint32_t fmt_shift_val;
uint32_t num_bytes_out_shift_val;
uint32_t crop_shift_val;
uint32_t debug_frm_drop_rst_shift_val;
uint32_t debug_timestamp_rst_shift_val;
uint32_t debug_format_measure_rst_shift_val;
uint32_t debug_misr_rst_shift_val;
uint32_t num_padding_pixels_shift_val;
uint32_t num_padding_rows_shift_val;
uint32_t fmt_measure_num_lines_shift_val;
uint32_t num_vbi_lines_shift_val;
uint32_t num_hbi_cycles_shift_val;
uint32_t multi_vcdt_vc1_shift_val;
uint32_t multi_vcdt_dt1_shift_val;
uint32_t multi_vcdt_ts_combo_en_shift_val;
uint32_t multi_vcdt_en_shift_val;
/* config Values */
uint32_t major_version;
uint32_t minor_version;
uint32_t version_incr;
uint32_t num_udis;
uint32_t num_rdis;
uint32_t num_pix;
uint32_t num_ppp;
uint32_t rst_sw_reg_stb;
uint32_t rst_hw_reg_stb;
uint32_t rst_sw_hw_reg_stb;
uint32_t path_rst_stb_all;
uint32_t drop_supported;
uint32_t multi_vcdt_supported;
uint32_t timestamp_strobe_val;
uint32_t early_eof_supported;
uint32_t global_reset;
uint32_t rup_supported;
/* Masks */
uint32_t ipp_irq_mask_all;
uint32_t rdi_irq_mask_all;
uint32_t ppp_irq_mask_all;
uint32_t udi_irq_mask_all;
uint32_t measure_en_hbi_vbi_cnt_mask;
uint32_t measure_pixel_line_en_mask;
uint32_t fmt_measure_num_line_mask;
uint32_t fmt_measure_num_pxl_mask;
uint32_t hblank_max_mask;
uint32_t hblank_min_mask;
uint32_t crop_pix_start_mask;
uint32_t crop_pix_end_mask;
uint32_t crop_line_start_mask;
uint32_t crop_line_end_mask;
};
/*
* struct cam_ife_csid_ver1_path_reg_info: Structure to hold PXL reg info
* holds register address offsets
* shift values
* masks
*/
struct cam_ife_csid_ver1_path_reg_info {
/* Pxl path register offsets*/
uint32_t irq_status_addr;
uint32_t irq_mask_addr;
uint32_t irq_clear_addr;
uint32_t irq_set_addr;
uint32_t cfg0_addr;
uint32_t cfg1_addr;
uint32_t ctrl_addr;
uint32_t frm_drop_pattern_addr;
uint32_t frm_drop_period_addr;
uint32_t irq_subsample_pattern_addr;
uint32_t irq_subsample_period_addr;
uint32_t hcrop_addr;
uint32_t vcrop_addr;
uint32_t pix_drop_pattern_addr;
uint32_t pix_drop_period_addr;
uint32_t line_drop_pattern_addr;
uint32_t line_drop_period_addr;
uint32_t rst_strobes_addr;
uint32_t status_addr;
uint32_t misr_val_addr;
uint32_t misr_val0_addr;
uint32_t misr_val1_addr;
uint32_t misr_val2_addr;
uint32_t misr_val3_addr;
uint32_t format_measure_cfg0_addr;
uint32_t format_measure_cfg1_addr;
uint32_t format_measure0_addr;
uint32_t format_measure1_addr;
uint32_t format_measure2_addr;
uint32_t yuv_chroma_conversion_addr;
uint32_t timestamp_curr0_sof_addr;
uint32_t timestamp_curr1_sof_addr;
uint32_t timestamp_prev0_sof_addr;
uint32_t timestamp_prev1_sof_addr;
uint32_t timestamp_curr0_eof_addr;
uint32_t timestamp_curr1_eof_addr;
uint32_t timestamp_prev0_eof_addr;
uint32_t timestamp_prev1_eof_addr;
uint32_t err_recovery_cfg0_addr;
uint32_t err_recovery_cfg1_addr;
uint32_t err_recovery_cfg2_addr;
uint32_t multi_vcdt_cfg0_addr;
uint32_t byte_cntr_ping_addr;
uint32_t byte_cntr_pong_addr;
/* shift bit configuration */
uint32_t timestamp_en_shift_val;
uint32_t crop_v_en_shift_val;
uint32_t crop_h_en_shift_val;
uint32_t drop_v_en_shift_val;
uint32_t drop_h_en_shift_val;
uint32_t bin_h_en_shift_val;
uint32_t bin_v_en_shift_val;
uint32_t bin_en_shift_val;
uint32_t bin_qcfa_en_shift_val;
uint32_t halt_mode_master;
uint32_t halt_mode_internal;
uint32_t halt_mode_global;
uint32_t halt_mode_slave;
uint32_t halt_mode_shift;
uint32_t halt_master_sel_master_val;
uint32_t halt_master_sel_shift;
uint32_t halt_frame_boundary;
uint32_t resume_frame_boundary;
uint32_t halt_immediate;
uint32_t halt_cmd_shift;
uint32_t mipi_pack_supported;
uint32_t packing_fmt_shift_val;
uint32_t format_measure_en_shift_val;
uint32_t plain_fmt_shift_val;
uint32_t packing_format;
uint32_t pix_store_en_shift_val;
uint32_t early_eof_en_shift_val;
/* config Values */
uint32_t ccif_violation_en;
uint32_t binning_supported;
uint32_t overflow_ctrl_mode_val;
uint32_t overflow_ctrl_en;
uint32_t fatal_err_mask;
uint32_t non_fatal_err_mask;
};
/*
* struct struct cam_ife_csid_ver1_tpg_reg_info: Structure to hold TPG reg info
* holds register address offsets
* shift values
* masks
*/
struct cam_ife_csid_ver1_tpg_reg_info {
uint32_t ctrl_addr;
uint32_t vc_cfg0_addr;
uint32_t vc_cfg1_addr;
uint32_t lfsr_seed_addr;
uint32_t dt_n_cfg_0_addr;
uint32_t dt_n_cfg_1_addr;
uint32_t dt_n_cfg_2_addr;
uint32_t color_bars_cfg_addr;
uint32_t color_box_cfg_addr;
uint32_t common_gen_cfg_addr;
uint32_t cgen_n_cfg_addr;
uint32_t cgen_n_x0_addr;
uint32_t cgen_n_x1_addr;
uint32_t cgen_n_x2_addr;
uint32_t cgen_n_xy_addr;
uint32_t cgen_n_y1_addr;
uint32_t cgen_n_y2_addr;
/*configurations */
uint32_t dtn_cfg_offset;
uint32_t cgen_cfg_offset;
uint32_t cpas_ife_reg_offset;
uint32_t hbi;
uint32_t vbi;
uint32_t lfsr_seed;
uint32_t width_shift;
uint32_t height_shift;
uint32_t fmt_shift;
uint32_t color_bar;
uint32_t line_interleave_mode;
uint32_t payload_mode;
uint32_t num_frames;
uint32_t num_active_dt;
uint32_t ctrl_cfg;
uint32_t phy_sel;
uint32_t num_frame_shift;
uint32_t line_interleave_shift;
uint32_t num_active_dt_shift;
uint32_t vbi_shift;
uint32_t hbi_shift;
uint32_t color_bar_shift;
uint32_t num_active_lanes_mask;
};
/*
* struct cam_ife_csid_ver1_reg_info: Structure for Reg info
*
* @csi2_reg: csi2 reg info
* @ipp_reg: IPP reg
* @ppp_reg: PPP reg
* @rdi_reg: RDI reg
* @udi_reg: UDI reg
* @start_pixel: start pixel for horizontal crop
* @tpg_reg: TPG reg
* @cmn_reg: Common reg info
* @csid_cust_node_map: Customer node map
* @fused_max_width: Max width based on fuse registers
* @width_fuse_max_val: Max value of width fuse
* @used_hw_capabilities Hw capabilities
*/
struct cam_ife_csid_ver1_reg_info {
struct cam_ife_csid_csi2_rx_reg_info *csi2_reg;
struct cam_ife_csid_ver1_path_reg_info *ipp_reg;
struct cam_ife_csid_ver1_path_reg_info *ppp_reg;
struct cam_ife_csid_ver1_path_reg_info *rdi_reg
[CAM_IFE_CSID_RDI_MAX];
struct cam_ife_csid_ver1_path_reg_info *udi_reg
[CAM_IFE_CSID_UDI_MAX];
struct cam_ife_csid_ver1_tpg_reg_info *tpg_reg;
struct cam_ife_csid_ver1_common_reg_info *cmn_reg;
const uint32_t csid_cust_node_map[
CAM_IFE_CSID_HW_NUM_MAX];
const uint32_t fused_max_width[
CAM_IFE_CSID_WIDTH_FUSE_VAL_MAX];
const uint32_t width_fuse_max_val;
};
/*
* struct cam_ife_csid_ver1_path_cfg: place holder for path parameters
*
* @cid: cid value for path
* @in_format: input format
* @out_format: output format
* @start_pixel: start pixel for horizontal crop
* @end_pixel: end pixel for horizontal crop
* @start_line: start line for vertical crop
* @end_line: end line for vertical crop
* @width: width of incoming data
* @height: height of incoming data
* @master_idx: master idx
* @horizontal_bin: horizontal binning enable/disable on path
* @vertical_bin: vertical binning enable/disable on path
* @qcfa_bin : qcfa binning enable/disable on path
* @hor_ver_bin : horizontal vertical binning enable/disable on path
* @num_bytes_out: Number of bytes out
* @sync_mode : Sync mode--> master/slave/none
* @crop_enable: flag to indicate crop enable
* @drop_enable: flag to indicate drop enable
* @fmt_measure_enable: flag to indicate format measure enabled
*
*/
struct cam_ife_csid_ver1_path_cfg {
uint32_t cid;
uint32_t in_format;
uint32_t out_format;
uint32_t start_pixel;
uint32_t end_pixel;
uint32_t width;
uint32_t start_line;
uint32_t end_line;
uint32_t height;
uint32_t master_idx;
uint32_t horizontal_bin;
uint32_t vertical_bin;
uint32_t qcfa_bin;
uint32_t hor_ver_bin;
uint32_t num_bytes_out;
uint32_t sensor_width;
uint32_t sensor_height;
enum cam_isp_hw_sync_mode sync_mode;
bool crop_enable;
bool drop_enable;
bool fmt_measure_enable;
};
/**
* struct cam_csid_evt_payload- payload for csid hw event
* @list : list head
* @irq_status : IRQ Status register
* @priv : Private data of payload
* @evt_type : Event type from CSID
* @hw_idx : Hw index
*/
struct cam_ife_csid_ver1_evt_payload {
struct list_head list;
uint32_t irq_status[CAM_IFE_CSID_IRQ_REG_MAX];
void *priv;
uint32_t evt_type;
uint32_t hw_idx;
};
/**
* struct cam_ife_csid_tpg_cfg- csid tpg configuration data
* @width: width
* @height: height
* @test_pattern : pattern
* @encode_format: decode format
* @usage_type: whether dual isp is required
* @vc: virtual channel
* @dt: data type
*
*/
struct cam_ife_csid_ver1_tpg_cfg {
uint32_t width;
uint32_t height;
uint32_t test_pattern;
uint32_t encode_format;
uint32_t usage_type;
uint32_t vc;
uint32_t dt;
};
/*
* struct cam_ife_csid_ver1_hw: place holder for csid hw
*
* @hw_intf: hw intf
* @hw_info: hw info
* @core_info: csid core info
* @tasklet: tasklet to handle csid errors
* @token: private data to be sent with callback
* @counters: counters used in csid hw
* @path_res: array of path resources
* @cid_data: cid data
* @log_buf: Log Buffer to dump info
* @rx_cfg: rx configuration
* @flags: flags
* @irq_complete: complete variable for reset irq
* @debug_info: Debug info to capture debug info
* @timestamp: Timestamp to maintain evt timestamps
* @free_payload_list: List of free payload list
* @evt_payload: Event payload
* @clk_rate: clk rate for csid hw
* @res_type: cur res type for active hw
* @lock_state : spin lock
*
*/
struct cam_ife_csid_ver1_hw {
struct cam_hw_intf *hw_intf;
struct cam_hw_info *hw_info;
struct cam_ife_csid_core_info *core_info;
void *tasklet;
void *token;
struct cam_ife_csid_hw_counters counters;
struct cam_ife_csid_ver1_tpg_cfg tpg_cfg;
struct cam_isp_resource_node path_res
[CAM_IFE_PIX_PATH_RES_MAX];
struct list_head free_payload_list;
struct cam_ife_csid_ver1_evt_payload evt_payload
[CAM_IFE_CSID_VER1_EVT_PAYLOAD_MAX];
struct completion irq_complete
[CAM_IFE_CSID_IRQ_REG_MAX];
struct cam_ife_csid_cid_data cid_data
[CAM_IFE_CSID_CID_MAX];
uint8_t log_buf
[CAM_IFE_CSID_LOG_BUF_LEN];
struct cam_ife_csid_rx_cfg rx_cfg;
struct cam_ife_csid_hw_flags flags;
struct cam_ife_csid_debug_info debug_info;
struct cam_ife_csid_timestamp timestamp;
uint64_t clk_rate;
uint32_t res_type;
spinlock_t lock_state;
cam_hw_mgr_event_cb_func event_cb;
};
int cam_ife_csid_hw_ver1_init(struct cam_hw_intf *csid_hw_intf,
struct cam_ife_csid_core_info *csid_core_info,
bool is_custom);
int cam_ife_csid_hw_ver1_deinit(struct cam_hw_info *hw_priv);
#endif

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drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.c Normal file
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drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef _CAM_IFE_CSID_HW_VER2_H_
#define _CAM_IFE_CSID_HW_VER2_H_
#include "cam_hw.h"
#include "cam_ife_csid_hw_intf.h"
#include "cam_ife_csid_soc.h"
#include "cam_ife_csid_common.h"
#define IFE_CSID_VER2_RX_DL0_EOT_CAPTURED BIT(0)
#define IFE_CSID_VER2_RX_DL1_EOT_CAPTURED BIT(1)
#define IFE_CSID_VER2_RX_DL2_EOT_CAPTURED BIT(2)
#define IFE_CSID_VER2_RX_DL3_EOT_CAPTURED BIT(3)
#define IFE_CSID_VER2_RX_DL0_SOT_CAPTURED BIT(4)
#define IFE_CSID_VER2_RX_DL1_SOT_CAPTURED BIT(5)
#define IFE_CSID_VER2_RX_DL2_SOT_CAPTURED BIT(6)
#define IFE_CSID_VER2_RX_DL3_SOT_CAPTURED BIT(7)
#define IFE_CSID_VER2_RX_LONG_PKT_CAPTURED BIT(8)
#define IFE_CSID_VER2_RX_SHORT_PKT_CAPTURED BIT(9)
#define IFE_CSID_VER2_RX_CPHY_PKT_HDR_CAPTURED BIT(10)
#define IFE_CSID_VER2_RX_CPHY_EOT_RECEPTION BIT(11)
#define IFE_CSID_VER2_RX_CPHY_SOT_RECEPTION BIT(12)
#define IFE_CSID_VER2_RX_ERROR_CPHY_PH_CRC BIT(13)
#define IFE_CSID_VER2_RX_WARNING_ECC BIT(14)
#define IFE_CSID_VER2_RX_LANE0_FIFO_OVERFLOW BIT(15)
#define IFE_CSID_VER2_RX_LANE1_FIFO_OVERFLOW BIT(16)
#define IFE_CSID_VER2_RX_LANE2_FIFO_OVERFLOW BIT(17)
#define IFE_CSID_VER2_RX_LANE3_FIFO_OVERFLOW BIT(18)
#define IFE_CSID_VER2_RX_ERROR_CRC BIT(19)
#define IFE_CSID_VER2_RX_ERROR_ECC BIT(20)
#define IFE_CSID_VER2_RX_MMAPPED_VC_DT BIT(21)
#define IFE_CSID_VER2_RX_UNMAPPED_VC_DT BIT(22)
#define IFE_CSID_VER2_RX_STREAM_UNDERFLOW BIT(23)
#define IFE_CSID_VER2_RX_UNBOUNDED_FRAME BIT(24)
#define IFE_CSID_VER2_RX_RST_DONE BIT(27)
#define CAM_IFE_CSID_VER2_PAYLOAD_MAX 256
#define IFE_CSID_VER2_TOP_IRQ_DONE BIT(0)
#define IFE_CSID_VER2_PATH_INFO_RST_DONE BIT(1)
#define IFE_CSID_VER2_PATH_ERROR_FIFO_OVERFLOW BIT(2)
#define IFE_CSID_VER2_PATH_CAMIF_EOF BIT(3)
#define IFE_CSID_VER2_PATH_CAMIF_SOF BIT(4)
#define IFE_CSID_VER2_PATH_INFO_FRAME_DROP_EOF BIT(5)
#define IFE_CSID_VER2_PATH_INFO_FRAME_DROP_EOL BIT(6)
#define IFE_CSID_VER2_PATH_INFO_FRAME_DROP_SOL BIT(7)
#define IFE_CSID_VER2_PATH_INFO_FRAME_DROP_SOF BIT(8)
#define IFE_CSID_VER2_PATH_INFO_INPUT_EOF BIT(9)
#define IFE_CSID_VER2_PATH_INFO_INPUT_EOL BIT(10)
#define IFE_CSID_VER2_PATH_INFO_INPUT_SOL BIT(11)
#define IFE_CSID_VER2_PATH_INFO_INPUT_SOF BIT(12)
#define IFE_CSID_VER2_PATH_ERROR_PIX_COUNT BIT(13)
#define IFE_CSID_VER2_PATH_ERROR_LINE_COUNT BIT(14)
#define IFE_CSID_VER2_PATH_VCDT_GRP0_SEL BIT(15)
#define IFE_CSID_VER2_PATH_VCDT_GRP1_SEL BIT(16)
#define IFE_CSID_VER2_PATH_VCDT_GRP_CHANGE BIT(17)
#define IFE_CSID_VER2_PATH_FRAME_DROP BIT(18)
#define IFE_CSID_VER2_PATH_OVERFLOW BIT(19)
#define IFE_CSID_VER2_PATH_ERROR_REC_CCIF_VIOLATION BIT(20)
#define IFE_CSID_VER2_PATH_CAMIF_EPOCH0 BIT(21)
#define IFE_CSID_VER2_PATH_CAMIF_EPOCH1 BIT(22)
#define IFE_CSID_VER2_PATH_RUP_DONE BIT(23)
#define IFE_CSID_VER2_PATH_ILLEGAL_BATCH_ID BIT(24)
#define IFE_CSID_VER2_PATH_BATCH_END_MISSING_VIOLATION BIT(25)
#define IFE_CSID_VER2_PATH_HEIGHT_VIOLATION BIT(26)
#define IFE_CSID_VER2_PATH_WIDTH_VIOLATION BIT(27)
#define IFE_CSID_VER2_PATH_SENSOR_SWITCH_OUT_OF_SYNC_FRAME_DROP BIT(28)
#define IFE_CSID_VER2_PATH_CCIF_VIOLATION BIT(29)
/*Each Bit represents the index of cust node hw*/
#define IFE_CSID_VER2_CUST_NODE_IDX_0 0x1
#define IFE_CSID_VER2_CUST_NODE_IDX_1 0x2
#define IFE_CSID_VER2_CUST_NODE_IDX_2 0x4
#define IFE_CSID_VER2_TOP_IRQ_STATUS_RST BIT(0)
#define IFE_CSID_VER2_TOP_IRQ_STATUS_RX0 BIT(2)
#define IFE_CSID_VER2_TOP_IRQ_STATUS_RX1 BIT(3)
#define IFE_CSID_VER2_TOP_IRQ_STATUS_IPP0 BIT(4)
#define IFE_CSID_VER2_TOP_IRQ_STATUS_IPP1 BIT(5)
#define IFE_CSID_VER2_TOP_IRQ_STATUS_PPP0 BIT(6)
#define IFE_CSID_VER2_TOP_IRQ_STATUS_PPP1 BIT(7)
#define IFE_CSID_VER2_TOP_IRQ_STATUS_RDI0 BIT(8)
#define IFE_CSID_VER2_TOP_IRQ_STATUS_RDI1 BIT(9)
#define IFE_CSID_VER2_TOP_IRQ_STATUS_RDI2 BIT(10)
#define IFE_CSID_VER2_TOP_IRQ_STATUS_RDI3 BIT(11)
#define IFE_CSID_VER2_TOP_IRQ_STATUS_RDI4 BIT(12)
#define IFE_CSID_VER2_TOP_IRQ_STATUS_BUF_DONE BIT(13)
enum cam_ife_csid_ver2_input_core_sel {
CAM_IFE_CSID_INPUT_CORE_SEL_NONE,
CAM_IFE_CSID_INPUT_CORE_SEL_INTERNAL,
CAM_IFE_CSID_INPUT_CORE_SEL_SFE_0,
CAM_IFE_CSID_INPUT_CORE_SEL_SFE_1,
CAM_IFE_CSID_INPUT_CORE_SEL_CUST_NODE_0,
CAM_IFE_CSID_INPUT_CORE_SEL_CUST_NODE_1,
CAM_IFE_CSID_INPUT_CORE_SEL_CUST_NODE_2,
CAM_IFE_CSID_INPUT_CORE_SEL_MAX,
};
enum cam_ife_csid_ver2_csid_reset_loc {
CAM_IFE_CSID_RESET_LOC_PATH_ONLY,
CAM_IFE_CSID_RESET_LOC_COMPLETE,
CAM_IFE_CSID_RESET_LOC_MAX,
};
enum cam_ife_csid_ver2_csid_reset_cmd {
CAM_IFE_CSID_RESET_CMD_IRQ_CTRL,
CAM_IFE_CSID_RESET_CMD_SW_RST,
CAM_IFE_CSID_RESET_CMD_HW_RST,
CAM_IFE_CSID_RESET_CMD_HW_MAX,
};
struct cam_ife_csid_ver2_top_cfg {
uint32_t input_core_type;
uint32_t dual_sync_core_sel;
uint32_t master_slave_sel;
bool dual_en;
bool offline_sfe_en;
bool out_ife_en;
};
struct cam_ife_csid_ver2_evt_payload {
struct list_head list;
uint32_t irq_reg_val[CAM_IFE_CSID_IRQ_REG_MAX];
};
/*
* struct cam_ife_csid_ver2_path_cfg: place holder for path parameters
*
* @pix_pattern: Pix pattern for incoming data
* @stripe_loc: Stripe location
* @epoch0_cfg: Epoch 0 configuration value
* @epoch1_cfg: Epoch 1 configuration value
*/
struct cam_ife_csid_ver2_camif_data {
uint32_t pix_pattern;
uint32_t stripe_loc;
uint32_t epoch0;
uint32_t epoch1;
};
/*
* struct cam_ife_csid_ver2_path_cfg: place holder for path parameters
*
* @camif_data: CAMIF data
* @cid: cid value for path
* @in_format: input format
* @out_format: output format
* @start_pixel: start pixel for horizontal crop
* @end_pixel: end pixel for horizontal crop
* @start_line: start line for vertical crop
* @end_line: end line for vertical crop
* @width: width of incoming data
* @height: height of incoming data
* @master_idx: master idx
* @horizontal_bin: horizontal binning enable/disable on path
* @vertical_bin: vertical binning enable/disable on path
* @qcfa_bin : qcfa binning enable/disable on path
* @hor_ver_bin : horizontal vertical binning enable/disable on path
* @num_bytes_out: Number of bytes out
* @pix_pattern: Pixel Pattern
* @sync_mode : Sync mode--> master/slave/none
* @vfr_en : flag to indicate if variable frame rate is enabled
* @frame_id_dec_en: flag to indicate if frame id decoding is enabled
* @crop_enable: flag to indicate crop enable
* @drop_enable: flag to indicate drop enable
* @offline_mode: flag to indicate if path working in offline mode
*
*/
struct cam_ife_csid_ver2_path_cfg {
struct cam_ife_csid_ver2_camif_data camif_data;
uint32_t cid;
uint32_t in_format;
uint32_t out_format;
uint32_t start_pixel;
uint32_t end_pixel;
uint32_t width;
uint32_t start_line;
uint32_t end_line;
uint32_t height;
uint32_t master_idx;
uint64_t clk_rate;
uint32_t horizontal_bin;
uint32_t vertical_bin;
uint32_t qcfa_bin;
uint32_t hor_ver_bin;
uint32_t num_bytes_out;
uint32_t pix_pattern;
enum cam_isp_hw_sync_mode sync_mode;
bool vfr_en;
bool frame_id_dec_en;
bool crop_enable;
bool drop_enable;
bool offline_mode;
bool handle_camif_irq;
};
struct cam_ife_csid_ver2_top_reg_info {
uint32_t io_path_cfg0_addr[CAM_IFE_CSID_HW_NUM_MAX];
uint32_t dual_csid_cfg0_addr[CAM_IFE_CSID_HW_NUM_MAX];
uint32_t input_core_type_shift_val;
uint32_t sfe_offline_en_shift_val;
uint32_t out_ife_en_shift_val;
uint32_t dual_sync_sel_shift_val;
uint32_t dual_en_shift_val;
uint32_t master_slave_sel_shift_val;
uint32_t master_sel_val;
uint32_t slave_sel_val;
};
struct cam_ife_csid_ver2_rdi_reg_info {
uint32_t irq_status_addr;
uint32_t irq_mask_addr;
uint32_t irq_clear_addr;
uint32_t irq_set_addr;
uint32_t cfg0_addr;
uint32_t ctrl_addr;
uint32_t debug_clr_cmd_addr;
uint32_t multi_vcdt_cfg0_addr;
uint32_t cfg1_addr;
uint32_t err_recovery_cfg0_addr;
uint32_t err_recovery_cfg1_addr;
uint32_t err_recovery_cfg2_addr;
uint32_t debug_byte_cntr_ping_addr;
uint32_t debug_byte_cntr_pong_addr;
uint32_t camif_frame_cfg_addr;
uint32_t epoch_irq_cfg_addr;
uint32_t epoch0_subsample_ptrn_addr;
uint32_t epoch1_subsample_ptrn_addr;
uint32_t debug_camif_1_addr;
uint32_t debug_camif_0_addr;
uint32_t frm_drop_pattern_addr;
uint32_t frm_drop_period_addr;
uint32_t irq_subsample_pattern_addr;
uint32_t irq_subsample_period_addr;
uint32_t hcrop_addr;
uint32_t vcrop_addr;
uint32_t pix_drop_pattern_addr;
uint32_t pix_drop_period_addr;
uint32_t line_drop_pattern_addr;
uint32_t line_drop_period_addr;
uint32_t debug_halt_status_addr;
uint32_t debug_misr_val0_addr;
uint32_t debug_misr_val1_addr;
uint32_t debug_misr_val2_addr;
uint32_t debug_misr_val3_addr;
uint32_t format_measure_cfg0_addr;
uint32_t format_measure_cfg1_addr;
uint32_t format_measure0_addr;
uint32_t format_measure1_addr;
uint32_t format_measure2_addr;
uint32_t timestamp_curr0_sof_addr;
uint32_t timestamp_curr1_sof_addr;
uint32_t timestamp_perv0_sof_addr;
uint32_t timestamp_perv1_sof_addr;
uint32_t timestamp_curr0_eof_addr;
uint32_t timestamp_curr1_eof_addr;
uint32_t timestamp_perv0_eof_addr;
uint32_t timestamp_perv1_eof_addr;
uint32_t batch_id_cfg0_addr;
uint32_t batch_id_cfg1_addr;
uint32_t batch_period_cfg_addr;
uint32_t batch_stream_id_cfg_addr;
uint32_t epoch0_cfg_batch_id0_addr;
uint32_t epoch1_cfg_batch_id0_addr;
uint32_t epoch0_cfg_batch_id1_addr;
uint32_t epoch1_cfg_batch_id1_addr;
uint32_t epoch0_cfg_batch_id2_addr;
uint32_t epoch1_cfg_batch_id2_addr;
uint32_t epoch0_cfg_batch_id3_addr;
uint32_t epoch1_cfg_batch_id3_addr;
uint32_t epoch0_cfg_batch_id4_addr;
uint32_t epoch1_cfg_batch_id4_addr;
uint32_t epoch0_cfg_batch_id5_addr;
uint32_t epoch1_cfg_batch_id5_addr;
/*Shift Bit Configurations*/
uint32_t resume_frame_boundary;
uint32_t offline_mode_supported;
uint32_t mipi_pack_supported;
uint32_t packing_fmt_shift_val;
uint32_t plain_fmt_shift_val;
uint32_t plain_alignment_shift_val;
uint32_t crop_v_en_shift_val;
uint32_t crop_h_en_shift_val;
uint32_t drop_v_en_shift_val;
uint32_t drop_h_en_shift_val;
uint32_t early_eof_en_shift_val;
uint32_t format_measure_en_shift_val;
uint32_t timestamp_en_shift_val;
uint32_t byte_cntr_en_shift_val;
uint32_t offline_mode_en_shift_val;
uint32_t debug_byte_cntr_rst_shift_val;
uint32_t stripe_loc_shift_val;
uint32_t pix_pattern_shift_val;
uint32_t ccif_violation_en;
uint32_t overflow_ctrl_mode_val;
uint32_t overflow_ctrl_en;
uint32_t fatal_err_mask;
uint32_t non_fatal_err_mask;
uint32_t pix_pattern_shift;
uint32_t camif_irq_mask;
uint32_t rup_aup_mask;
uint32_t epoch0_cfg_val;
uint32_t epoch1_cfg_val;
};
struct cam_ife_csid_ver2_pxl_reg_info {
uint32_t irq_status_addr;
uint32_t irq_mask_addr;
uint32_t irq_clear_addr;
uint32_t irq_set_addr;
uint32_t cfg0_addr;
uint32_t ctrl_addr;
uint32_t debug_clr_cmd_addr;
uint32_t multi_vcdt_cfg0_addr;
uint32_t cfg1_addr;
uint32_t sparse_pd_extractor_cfg_addr;
uint32_t err_recovery_cfg0_addr;
uint32_t err_recovery_cfg1_addr;
uint32_t err_recovery_cfg2_addr;
uint32_t bin_pd_detect_cfg0_addr;
uint32_t bin_pd_detect_cfg1_addr;
uint32_t bin_pd_detect_cfg2_addr;
uint32_t camif_frame_cfg_addr;
uint32_t epoch_irq_cfg_addr;
uint32_t epoch0_subsample_ptrn_addr;
uint32_t epoch1_subsample_ptrn_addr;
uint32_t debug_camif_1_addr;
uint32_t debug_camif_0_addr;
uint32_t debug_halt_status_addr;
uint32_t debug_misr_val0_addr;
uint32_t debug_misr_val1_addr;
uint32_t debug_misr_val2_addr;
uint32_t debug_misr_val3_addr;
uint32_t hcrop_addr;
uint32_t vcrop_addr;
uint32_t pix_drop_pattern_addr;
uint32_t pix_drop_period_addr;
uint32_t line_drop_pattern_addr;
uint32_t line_drop_period_addr;
uint32_t frm_drop_pattern_addr;
uint32_t frm_drop_period_addr;
uint32_t irq_subsample_pattern_addr;
uint32_t irq_subsample_period_addr;
uint32_t format_measure_cfg0_addr;
uint32_t format_measure_cfg1_addr;
uint32_t format_measure0_addr;
uint32_t format_measure1_addr;
uint32_t format_measure2_addr;
uint32_t timestamp_curr0_sof_addr;
uint32_t timestamp_curr1_sof_addr;
uint32_t timestamp_perv0_sof_addr;
uint32_t timestamp_perv1_sof_addr;
uint32_t timestamp_curr0_eof_addr;
uint32_t timestamp_curr1_eof_addr;
uint32_t timestamp_perv0_eof_addr;
uint32_t timestamp_perv1_eof_addr;
uint32_t lut_bank_cfg_addr;
uint32_t batch_id_cfg0_addr;
uint32_t batch_id_cfg1_addr;
uint32_t batch_period_cfg_addr;
uint32_t batch_stream_id_cfg_addr;
uint32_t epoch0_cfg_batch_id0_addr;
uint32_t epoch1_cfg_batch_id0_addr;
uint32_t epoch0_cfg_batch_id1_addr;
uint32_t epoch1_cfg_batch_id1_addr;
uint32_t epoch0_cfg_batch_id2_addr;
uint32_t epoch1_cfg_batch_id2_addr;
uint32_t epoch0_cfg_batch_id3_addr;
uint32_t epoch1_cfg_batch_id3_addr;
uint32_t epoch0_cfg_batch_id4_addr;
uint32_t epoch1_cfg_batch_id4_addr;
uint32_t epoch0_cfg_batch_id5_addr;
uint32_t epoch1_cfg_batch_id5_addr;
/*Shift Bit Configurations*/
uint32_t start_mode_master;
uint32_t start_mode_internal;
uint32_t start_mode_global;
uint32_t start_mode_slave;
uint32_t start_mode_shift;
uint32_t start_master_sel_val;
uint32_t start_master_sel_shift;
uint32_t crop_v_en_shift_val;
uint32_t crop_h_en_shift_val;
uint32_t drop_v_en_shift_val;
uint32_t drop_h_en_shift_val;
uint32_t pix_store_en_shift_val;
uint32_t early_eof_en_shift_val;
uint32_t bin_h_en_shift_val;
uint32_t bin_v_en_shift_val;
uint32_t bin_en_shift_val;
uint32_t bin_qcfa_en_shift_val;
uint32_t format_measure_en_shift_val;
uint32_t timestamp_en_shift_val;
uint32_t min_hbi_shift_val;
uint32_t start_master_sel_shift_val;
uint32_t bin_pd_en_shift_val;
uint32_t bin_pd_blk_w_shift_val;
uint32_t bin_pd_blk_h_shift_val;
uint32_t bin_pd_detect_x_offset_shift_val;
uint32_t bin_pd_detect_x_end_shift_val;
uint32_t bin_pd_detect_y_offset_shift_val;
uint32_t bin_pd_detect_y_end_shift_val;
uint32_t stripe_loc_shift_val;
uint32_t pix_pattern_shift_val;
uint32_t epoch0_cfg_val;
uint32_t epoch1_cfg_val;
/* config Values */
uint32_t resume_frame_boundary;
uint32_t overflow_ctrl_mode_val;
uint32_t overflow_ctrl_en;
uint32_t lut_bank_0_sel_val;
uint32_t lut_bank_1_sel_val;
uint32_t ccif_violation_en;
uint32_t binning_supported;
uint32_t fatal_err_mask;
uint32_t non_fatal_err_mask;
uint32_t camif_irq_mask;
uint32_t rup_aup_mask;
};
struct cam_ife_csid_ver2_common_reg_info {
uint32_t hw_version_addr;
uint32_t cfg0_addr;
uint32_t global_cmd_addr;
uint32_t reset_cfg_addr;
uint32_t reset_cmd_addr;
uint32_t rup_aup_cmd_addr;
uint32_t offline_cmd_addr;
uint32_t shdr_master_slave_cfg_addr;
uint32_t top_irq_status_addr;
uint32_t top_irq_mask_addr;
uint32_t top_irq_clear_addr;
uint32_t top_irq_set_addr;
uint32_t irq_cmd_addr;
uint32_t buf_done_irq_status_addr;
uint32_t buf_done_irq_mask_addr;
uint32_t buf_done_irq_clear_addr;
uint32_t buf_done_irq_set_addr;
/*Shift Bit Configurations*/
uint32_t rst_done_shift_val;
uint32_t rst_location_shift_val;
uint32_t rst_mode_shift_val;
uint32_t timestamp_stb_sel_shift_val;
uint32_t frame_id_decode_en_shift_val;
uint32_t vfr_en_shift_val;
uint32_t decode_format_shift_val;
uint32_t start_mode_shift_val;
uint32_t start_cmd_shift_val;
uint32_t path_en_shift_val;
uint32_t dt_id_shift_val;
uint32_t vc_shift_val;
uint32_t dt_shift_val;
uint32_t crop_shift_val;
uint32_t debug_frm_drop_rst_shift_val;
uint32_t debug_timestamp_rst_shift_val;
uint32_t debug_format_measure_rst_shift_val;
uint32_t debug_misr_rst_shift_val;
uint32_t num_padding_pixels_shift_val;
uint32_t num_padding_rows_shift_val;
uint32_t num_vbi_lines_shift_val;
uint32_t num_hbi_cycles_shift_val;
uint32_t camif_stripe_loc_shift_val;
uint32_t camif_pix_pattern_shift_val;
uint32_t epoch0_line_shift_val;
uint32_t epoch1_line_shift_val;
uint32_t camif_width_shift_val;
uint32_t camif_height_shift_val;
uint32_t batch_id0_shift_val;
uint32_t batch_id1_shift_val;
uint32_t batch_id2_shift_val;
uint32_t batch_id3_shift_val;
uint32_t batch_id4_shift_val;
uint32_t batch_id5_shift_val;
uint32_t batch_id0_period_shift_val;
uint32_t batch_id1_period_shift_val;
uint32_t batch_id2_period_shift_val;
uint32_t batch_id3_period_shift_val;
uint32_t batch_id4_period_shift_val;
uint32_t batch_id5_period_shift_val;
uint32_t stream_id_len_shift_val;
uint32_t stream_id_x_offset_shift_val;
uint32_t stream_id_y_offset_shift_val;
uint32_t multi_vcdt_vc1_shift_val;
uint32_t multi_vcdt_dt1_shift_val;
uint32_t multi_vcdt_ts_combo_en_shift_val;
uint32_t multi_vcdt_en_shift_val;
uint32_t mup_shift_val;
uint32_t shdr_slave_rdi2_shift;
uint32_t shdr_slave_rdi1_shift;
uint32_t shdr_master_rdi0_shift;
uint32_t shdr_master_slave_en_shift;
/* config Values */
uint32_t major_version;
uint32_t minor_version;
uint32_t version_incr;
uint32_t num_udis;
uint32_t num_rdis;
uint32_t num_pix;
uint32_t num_ppp;
uint32_t rst_loc_path_only_val;
uint32_t rst_loc_complete_csid_val;
uint32_t rst_mode_frame_boundary_val;
uint32_t rst_mode_immediate_val;
uint32_t rst_cmd_irq_ctrl_only_val;
uint32_t rst_cmd_sw_reset_complete_val;
uint32_t rst_cmd_hw_reset_complete_val;
uint32_t vfr_supported;
uint32_t frame_id_dec_supported;
uint32_t drop_supported;
uint32_t multi_vcdt_supported;
uint32_t timestamp_strobe_val;
uint32_t overflow_ctrl_mode_val;
uint32_t overflow_ctrl_en;
uint32_t early_eof_supported;
uint32_t global_reset;
uint32_t rup_supported;
/* Masks */
uint32_t pxl_cnt_mask;
uint32_t line_cnt_mask;
uint32_t hblank_max_mask;
uint32_t hblank_min_mask;
uint32_t epoch0_line_mask;
uint32_t epoch1_line_mask;
uint32_t camif_width_mask;
uint32_t camif_height_mask;
uint32_t crop_pix_start_mask;
uint32_t crop_pix_end_mask;
uint32_t crop_line_start_mask;
uint32_t crop_line_end_mask;
uint32_t measure_en_hbi_vbi_cnt_mask;
uint32_t measure_pixel_line_en_mask;
uint32_t ipp_irq_mask_all;
uint32_t rdi_irq_mask_all;
uint32_t ppp_irq_mask_all;
uint32_t udi_irq_mask_all;
uint32_t top_reset_irq_shift_val;
uint32_t epoch_div_factor;
};
struct cam_ife_csid_ver2_reg_info {
struct cam_irq_controller_reg_info *irq_reg_info;
struct cam_irq_controller_reg_info *buf_done_irq_reg_info;
const struct cam_ife_csid_ver2_common_reg_info *cmn_reg;
const struct cam_ife_csid_csi2_rx_reg_info *csi2_reg;
const struct cam_ife_csid_ver2_pxl_reg_info *ipp_reg;
const struct cam_ife_csid_ver2_pxl_reg_info *ppp_reg;
const struct cam_ife_csid_ver2_rdi_reg_info *rdi_reg
[CAM_IFE_CSID_RDI_MAX];
const struct cam_ife_csid_ver2_top_reg_info *top_reg;
const uint32_t need_top_cfg;
const uint32_t csid_cust_node_map[
CAM_IFE_CSID_HW_NUM_MAX];
const int input_core_sel[
CAM_IFE_CSID_HW_NUM_MAX][CAM_IFE_CSID_INPUT_CORE_SEL_MAX];
};
/*
* struct cam_ife_csid_ver2_hw: place holder for csid hw
*
* @path_res: array of path resources
* @cid_data: cid data
* @rx_cfg: rx configuration
* @flags: flags
* @irq_complete: complete variable for reset irq
* @debug_info: Debug info to capture debug info
* @timestamp: Timestamp info
* @timestamp: Timestamp info
* @rx_evt_payload Payload for rx events
* @path_evt_payload Payload for path events
* @rx_free_payload_list: Free Payload list for rx events
* @free_payload_list: Free Payload list for rx events
* @lock_state : spin lock
* @payload_lock: spin lock for path payload
* @rx_payload_lock: spin lock for rx payload
* @csid_irq_controller: common csid irq controller
* @buf_done_irq_controller: buf done irq controller
* @hw_info: hw info
* @core_info: csid core info
* @token: Context private of ife hw manager
* @event_cb: Event cb to ife hw manager
* @irq_handle: Array of irq handle for events
* @err_irq_handle: Array of irq handle for error events
* @counters: counters used in csid hw
* @log_buf: Log Buffer to dump info
* @clk_rate: clk rate for csid hw
* @res_type: cur res type for active hw
* @dual_core_idx: core idx in case of dual csid
* @tasklet: Tasklet for irq events
* @reset_irq_handle: Reset irq handle
* @buf_done_irq_handle: Buf done irq handle
* @sync_mode: Master/Slave modes
*
*/
struct cam_ife_csid_ver2_hw {
struct cam_isp_resource_node path_res
[CAM_IFE_PIX_PATH_RES_MAX];
struct cam_ife_csid_cid_data cid_data[CAM_IFE_CSID_CID_MAX];
struct cam_ife_csid_ver2_top_cfg top_cfg;
struct cam_ife_csid_rx_cfg rx_cfg;
struct cam_ife_csid_hw_counters counters;
struct cam_ife_csid_hw_flags flags;
struct completion irq_complete
[CAM_IFE_CSID_IRQ_REG_MAX];
struct cam_ife_csid_debug_info debug_info;
struct cam_ife_csid_timestamp timestamp;
struct cam_ife_csid_ver2_evt_payload rx_evt_payload[
CAM_IFE_CSID_VER2_PAYLOAD_MAX];
struct cam_ife_csid_ver2_evt_payload path_evt_payload[
CAM_IFE_CSID_VER2_PAYLOAD_MAX];
struct list_head rx_free_payload_list;
struct list_head path_free_payload_list;
spinlock_t lock_state;
spinlock_t path_payload_lock;
spinlock_t rx_payload_lock;
void *csid_irq_controller;
void *buf_done_irq_controller;
struct cam_hw_intf *hw_intf;
struct cam_hw_info *hw_info;
struct cam_ife_csid_core_info *core_info;
void *token;
cam_hw_mgr_event_cb_func event_cb;
int irq_handle[
CAM_IFE_CSID_IRQ_REG_MAX];
int err_irq_handle[
CAM_IFE_CSID_IRQ_REG_MAX];
uint8_t log_buf
[CAM_IFE_CSID_LOG_BUF_LEN];
uint64_t clk_rate;
uint32_t res_type;
uint32_t dual_core_idx;
void *tasklet;
int reset_irq_handle;
int buf_done_irq_handle;
enum cam_isp_hw_sync_mode sync_mode;
};
int cam_ife_csid_hw_ver2_init(struct cam_hw_intf *csid_hw_intf,
struct cam_ife_csid_core_info *csid_core_info,
bool is_custom);
int cam_ife_csid_hw_ver2_deinit(struct cam_hw_info *hw_priv);
#endif

630
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite17x.h
View File

@@ -1,316 +1,398 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
*/ */
#ifndef _CAM_IFE_CSID_LITE17X_H_ #ifndef _CAM_IFE_CSID_LITE17X_H_
#define _CAM_IFE_CSID_LITE17X_H_ #define _CAM_IFE_CSID_LITE17X_H_
#include "cam_ife_csid_core.h"
static const struct cam_ife_csid_rdi_reg_offset #include "cam_ife_csid_dev.h"
cam_ife_csid_lite_17x_rdi_0_reg_offset = { #include "cam_ife_csid_common.h"
#include "cam_ife_csid_hw_ver1.h"
.csid_rdi_irq_status_addr = 0x30, #define CAM_CSID_LITE_DRV_NAME "csid_lite"
.csid_rdi_irq_mask_addr = 0x34,
.csid_rdi_irq_clear_addr = 0x38, static struct cam_ife_csid_ver1_path_reg_info
.csid_rdi_irq_set_addr = 0x3c, cam_ife_csid_lite_17x_rdi_0_reg_info = {
.csid_rdi_cfg0_addr = 0x200,
.csid_rdi_cfg1_addr = 0x204, .irq_status_addr = 0x30,
.csid_rdi_ctrl_addr = 0x208, .irq_mask_addr = 0x34,
.csid_rdi_frm_drop_pattern_addr = 0x20c, .irq_clear_addr = 0x38,
.csid_rdi_frm_drop_period_addr = 0x210, .irq_set_addr = 0x3c,
.csid_rdi_irq_subsample_pattern_addr = 0x214, .cfg0_addr = 0x200,
.csid_rdi_irq_subsample_period_addr = 0x218, .cfg1_addr = 0x204,
.csid_rdi_rpp_hcrop_addr = 0x21c, .ctrl_addr = 0x208,
.csid_rdi_rpp_vcrop_addr = 0x220, .frm_drop_pattern_addr = 0x20c,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x224, .frm_drop_period_addr = 0x210,
.csid_rdi_rpp_pix_drop_period_addr = 0x228, .irq_subsample_pattern_addr = 0x214,
.csid_rdi_rpp_line_drop_pattern_addr = 0x22c, .irq_subsample_period_addr = 0x218,
.csid_rdi_rpp_line_drop_period_addr = 0x230, .hcrop_addr = 0x21c,
.csid_rdi_rst_strobes_addr = 0x240, .vcrop_addr = 0x220,
.csid_rdi_status_addr = 0x250, .pix_drop_pattern_addr = 0x224,
.csid_rdi_misr_val0_addr = 0x254, .pix_drop_period_addr = 0x228,
.csid_rdi_misr_val1_addr = 0x258, .line_drop_pattern_addr = 0x22c,
.csid_rdi_misr_val2_addr = 0x25c, .line_drop_period_addr = 0x230,
.csid_rdi_misr_val3_addr = 0x260, .rst_strobes_addr = 0x240,
.csid_rdi_format_measure_cfg0_addr = 0x270, .status_addr = 0x250,
.csid_rdi_format_measure_cfg1_addr = 0x274, .misr_val0_addr = 0x254,
.csid_rdi_format_measure0_addr = 0x278, .misr_val1_addr = 0x258,
.csid_rdi_format_measure1_addr = 0x27c, .misr_val2_addr = 0x25c,
.csid_rdi_format_measure2_addr = 0x280, .misr_val3_addr = 0x260,
.csid_rdi_timestamp_curr0_sof_addr = 0x290, .format_measure_cfg0_addr = 0x270,
.csid_rdi_timestamp_curr1_sof_addr = 0x294, .format_measure_cfg1_addr = 0x274,
.csid_rdi_timestamp_prev0_sof_addr = 0x298, .format_measure0_addr = 0x278,
.csid_rdi_timestamp_prev1_sof_addr = 0x29c, .format_measure1_addr = 0x27c,
.csid_rdi_timestamp_curr0_eof_addr = 0x2a0, .format_measure2_addr = 0x280,
.csid_rdi_timestamp_curr1_eof_addr = 0x2a4, .timestamp_curr0_sof_addr = 0x290,
.csid_rdi_timestamp_prev0_eof_addr = 0x2a8, .timestamp_curr1_sof_addr = 0x294,
.csid_rdi_timestamp_prev1_eof_addr = 0x2ac, .timestamp_prev0_sof_addr = 0x298,
.csid_rdi_byte_cntr_ping_addr = 0x2e0, .timestamp_prev1_sof_addr = 0x29c,
.csid_rdi_byte_cntr_pong_addr = 0x2e4, .timestamp_curr0_eof_addr = 0x2a0,
.timestamp_curr1_eof_addr = 0x2a4,
.timestamp_prev0_eof_addr = 0x2a8,
.timestamp_prev1_eof_addr = 0x2ac,
.byte_cntr_ping_addr = 0x2e0,
.byte_cntr_pong_addr = 0x2e4,
.halt_mode_internal = 0,
.halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.packing_fmt_shift_val = 30,
.plain_fmt_shift_val = 10,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.timestamp_en_shift_val = 2,
.format_measure_en_shift_val = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x8000,
}; };
static const struct cam_ife_csid_rdi_reg_offset static struct cam_ife_csid_ver1_path_reg_info
cam_ife_csid_lite_17x_rdi_1_reg_offset = { cam_ife_csid_lite_17x_rdi_1_reg_info = {
.csid_rdi_irq_status_addr = 0x40, .irq_status_addr = 0x40,
.csid_rdi_irq_mask_addr = 0x44, .irq_mask_addr = 0x44,
.csid_rdi_irq_clear_addr = 0x48, .irq_clear_addr = 0x48,
.csid_rdi_irq_set_addr = 0x4c, .irq_set_addr = 0x4c,
.csid_rdi_cfg0_addr = 0x300, .cfg0_addr = 0x300,
.csid_rdi_cfg1_addr = 0x304, .cfg1_addr = 0x304,
.csid_rdi_ctrl_addr = 0x308, .ctrl_addr = 0x308,
.csid_rdi_frm_drop_pattern_addr = 0x30c, .frm_drop_pattern_addr = 0x30c,
.csid_rdi_frm_drop_period_addr = 0x310, .frm_drop_period_addr = 0x310,
.csid_rdi_irq_subsample_pattern_addr = 0x314, .irq_subsample_pattern_addr = 0x314,
.csid_rdi_irq_subsample_period_addr = 0x318, .irq_subsample_period_addr = 0x318,
.csid_rdi_rpp_hcrop_addr = 0x31c, .hcrop_addr = 0x31c,
.csid_rdi_rpp_vcrop_addr = 0x320, .vcrop_addr = 0x320,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x324, .pix_drop_pattern_addr = 0x324,
.csid_rdi_rpp_pix_drop_period_addr = 0x328, .pix_drop_period_addr = 0x328,
.csid_rdi_rpp_line_drop_pattern_addr = 0x32c, .line_drop_pattern_addr = 0x32c,
.csid_rdi_rpp_line_drop_period_addr = 0x330, .line_drop_period_addr = 0x330,
.csid_rdi_rst_strobes_addr = 0x340, .rst_strobes_addr = 0x340,
.csid_rdi_status_addr = 0x350, .status_addr = 0x350,
.csid_rdi_misr_val0_addr = 0x354, .misr_val0_addr = 0x354,
.csid_rdi_misr_val1_addr = 0x358, .misr_val1_addr = 0x358,
.csid_rdi_misr_val2_addr = 0x35c, .misr_val2_addr = 0x35c,
.csid_rdi_misr_val3_addr = 0x360, .misr_val3_addr = 0x360,
.csid_rdi_format_measure_cfg0_addr = 0x370, .format_measure_cfg0_addr = 0x370,
.csid_rdi_format_measure_cfg1_addr = 0x374, .format_measure_cfg1_addr = 0x374,
.csid_rdi_format_measure0_addr = 0x378, .format_measure0_addr = 0x378,
.csid_rdi_format_measure1_addr = 0x37c, .format_measure1_addr = 0x37c,
.csid_rdi_format_measure2_addr = 0x380, .format_measure2_addr = 0x380,
.csid_rdi_timestamp_curr0_sof_addr = 0x390, .timestamp_curr0_sof_addr = 0x390,
.csid_rdi_timestamp_curr1_sof_addr = 0x394, .timestamp_curr1_sof_addr = 0x394,
.csid_rdi_timestamp_prev0_sof_addr = 0x398, .timestamp_prev0_sof_addr = 0x398,
.csid_rdi_timestamp_prev1_sof_addr = 0x39c, .timestamp_prev1_sof_addr = 0x39c,
.csid_rdi_timestamp_curr0_eof_addr = 0x3a0, .timestamp_curr0_eof_addr = 0x3a0,
.csid_rdi_timestamp_curr1_eof_addr = 0x3a4, .timestamp_curr1_eof_addr = 0x3a4,
.csid_rdi_timestamp_prev0_eof_addr = 0x3a8, .timestamp_prev0_eof_addr = 0x3a8,
.csid_rdi_timestamp_prev1_eof_addr = 0x3ac, .timestamp_prev1_eof_addr = 0x3ac,
.csid_rdi_byte_cntr_ping_addr = 0x3e0, .byte_cntr_ping_addr = 0x3e0,
.csid_rdi_byte_cntr_pong_addr = 0x3e4, .byte_cntr_pong_addr = 0x3e4,
.halt_mode_internal = 0,
.halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.plain_fmt_shift_val = 10,
.packing_fmt_shift_val = 30,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.timestamp_en_shift_val = 2,
.format_measure_en_shift_val = 1,
}; };
static const struct cam_ife_csid_rdi_reg_offset static struct cam_ife_csid_ver1_path_reg_info
cam_ife_csid_lite_17x_rdi_2_reg_offset = { cam_ife_csid_lite_17x_rdi_2_reg_info = {
.csid_rdi_irq_status_addr = 0x50, .irq_status_addr = 0x50,
.csid_rdi_irq_mask_addr = 0x54, .irq_mask_addr = 0x54,
.csid_rdi_irq_clear_addr = 0x58, .irq_clear_addr = 0x58,
.csid_rdi_irq_set_addr = 0x5c, .irq_set_addr = 0x5c,
.csid_rdi_cfg0_addr = 0x400, .cfg0_addr = 0x400,
.csid_rdi_cfg1_addr = 0x404, .cfg1_addr = 0x404,
.csid_rdi_ctrl_addr = 0x408, .ctrl_addr = 0x408,
.csid_rdi_frm_drop_pattern_addr = 0x40c, .frm_drop_pattern_addr = 0x40c,
.csid_rdi_frm_drop_period_addr = 0x410, .frm_drop_period_addr = 0x410,
.csid_rdi_irq_subsample_pattern_addr = 0x414, .irq_subsample_pattern_addr = 0x414,
.csid_rdi_irq_subsample_period_addr = 0x418, .irq_subsample_period_addr = 0x418,
.csid_rdi_rpp_hcrop_addr = 0x41c, .hcrop_addr = 0x41c,
.csid_rdi_rpp_vcrop_addr = 0x420, .vcrop_addr = 0x420,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x424, .pix_drop_pattern_addr = 0x424,
.csid_rdi_rpp_pix_drop_period_addr = 0x428, .pix_drop_period_addr = 0x428,
.csid_rdi_rpp_line_drop_pattern_addr = 0x42c, .line_drop_pattern_addr = 0x42c,
.csid_rdi_rpp_line_drop_period_addr = 0x430, .line_drop_period_addr = 0x430,
.csid_rdi_yuv_chroma_conversion_addr = 0x434, .yuv_chroma_conversion_addr = 0x434,
.csid_rdi_rst_strobes_addr = 0x440, .rst_strobes_addr = 0x440,
.csid_rdi_status_addr = 0x450, .status_addr = 0x450,
.csid_rdi_misr_val0_addr = 0x454, .misr_val0_addr = 0x454,
.csid_rdi_misr_val1_addr = 0x458, .misr_val1_addr = 0x458,
.csid_rdi_misr_val2_addr = 0x45c, .misr_val2_addr = 0x45c,
.csid_rdi_misr_val3_addr = 0x460, .misr_val3_addr = 0x460,
.csid_rdi_format_measure_cfg0_addr = 0x470, .format_measure_cfg0_addr = 0x470,
.csid_rdi_format_measure_cfg1_addr = 0x474, .format_measure_cfg1_addr = 0x474,
.csid_rdi_format_measure0_addr = 0x478, .format_measure0_addr = 0x478,
.csid_rdi_format_measure1_addr = 0x47c, .format_measure1_addr = 0x47c,
.csid_rdi_format_measure2_addr = 0x480, .format_measure2_addr = 0x480,
.csid_rdi_timestamp_curr0_sof_addr = 0x490, .timestamp_curr0_sof_addr = 0x490,
.csid_rdi_timestamp_curr1_sof_addr = 0x494, .timestamp_curr1_sof_addr = 0x494,
.csid_rdi_timestamp_prev0_sof_addr = 0x498, .timestamp_prev0_sof_addr = 0x498,
.csid_rdi_timestamp_prev1_sof_addr = 0x49c, .timestamp_prev1_sof_addr = 0x49c,
.csid_rdi_timestamp_curr0_eof_addr = 0x4a0, .timestamp_curr0_eof_addr = 0x4a0,
.csid_rdi_timestamp_curr1_eof_addr = 0x4a4, .timestamp_curr1_eof_addr = 0x4a4,
.csid_rdi_timestamp_prev0_eof_addr = 0x4a8, .timestamp_prev0_eof_addr = 0x4a8,
.csid_rdi_timestamp_prev1_eof_addr = 0x4ac, .timestamp_prev1_eof_addr = 0x4ac,
.csid_rdi_byte_cntr_ping_addr = 0x4e0, .byte_cntr_ping_addr = 0x4e0,
.csid_rdi_byte_cntr_pong_addr = 0x4e4, .byte_cntr_pong_addr = 0x4e4,
.halt_mode_internal = 0,
.halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.plain_fmt_shift_val = 10,
.packing_fmt_shift_val = 30,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.timestamp_en_shift_val = 2,
.format_measure_en_shift_val = 1,
}; };
static const struct cam_ife_csid_rdi_reg_offset static struct cam_ife_csid_ver1_path_reg_info
cam_ife_csid_lite_17x_rdi_3_reg_offset = { cam_ife_csid_lite_17x_rdi_3_reg_info = {
.csid_rdi_irq_status_addr = 0x60, .irq_status_addr = 0x60,
.csid_rdi_irq_mask_addr = 0x64, .irq_mask_addr = 0x64,
.csid_rdi_irq_clear_addr = 0x68, .irq_clear_addr = 0x68,
.csid_rdi_irq_set_addr = 0x6c, .irq_set_addr = 0x6c,
.csid_rdi_cfg0_addr = 0x500, .cfg0_addr = 0x500,
.csid_rdi_cfg1_addr = 0x504, .cfg1_addr = 0x504,
.csid_rdi_ctrl_addr = 0x508, .ctrl_addr = 0x508,
.csid_rdi_frm_drop_pattern_addr = 0x50c, .frm_drop_pattern_addr = 0x50c,
.csid_rdi_frm_drop_period_addr = 0x510, .frm_drop_period_addr = 0x510,
.csid_rdi_irq_subsample_pattern_addr = 0x514, .irq_subsample_pattern_addr = 0x514,
.csid_rdi_irq_subsample_period_addr = 0x518, .irq_subsample_period_addr = 0x518,
.csid_rdi_rpp_hcrop_addr = 0x51c, .hcrop_addr = 0x51c,
.csid_rdi_rpp_vcrop_addr = 0x520, .vcrop_addr = 0x520,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x524, .pix_drop_pattern_addr = 0x524,
.csid_rdi_rpp_pix_drop_period_addr = 0x528, .pix_drop_period_addr = 0x528,
.csid_rdi_rpp_line_drop_pattern_addr = 0x52c, .line_drop_pattern_addr = 0x52c,
.csid_rdi_rpp_line_drop_period_addr = 0x530, .line_drop_period_addr = 0x530,
.csid_rdi_yuv_chroma_conversion_addr = 0x534, .yuv_chroma_conversion_addr = 0x534,
.csid_rdi_rst_strobes_addr = 0x540, .rst_strobes_addr = 0x540,
.csid_rdi_status_addr = 0x550, .status_addr = 0x550,
.csid_rdi_misr_val0_addr = 0x554, .misr_val0_addr = 0x554,
.csid_rdi_misr_val1_addr = 0x558, .misr_val1_addr = 0x558,
.csid_rdi_misr_val2_addr = 0x55c, .misr_val2_addr = 0x55c,
.csid_rdi_misr_val3_addr = 0x560, .misr_val3_addr = 0x560,
.csid_rdi_format_measure_cfg0_addr = 0x570, .format_measure_cfg0_addr = 0x570,
.csid_rdi_format_measure_cfg1_addr = 0x574, .format_measure_cfg1_addr = 0x574,
.csid_rdi_format_measure0_addr = 0x578, .format_measure0_addr = 0x578,
.csid_rdi_format_measure1_addr = 0x57c, .format_measure1_addr = 0x57c,
.csid_rdi_format_measure2_addr = 0x580, .format_measure2_addr = 0x580,
.csid_rdi_timestamp_curr0_sof_addr = 0x590, .timestamp_curr0_sof_addr = 0x590,
.csid_rdi_timestamp_curr1_sof_addr = 0x594, .timestamp_curr1_sof_addr = 0x594,
.csid_rdi_timestamp_prev0_sof_addr = 0x598, .timestamp_prev0_sof_addr = 0x598,
.csid_rdi_timestamp_prev1_sof_addr = 0x59c, .timestamp_prev1_sof_addr = 0x59c,
.csid_rdi_timestamp_curr0_eof_addr = 0x5a0, .timestamp_curr0_eof_addr = 0x5a0,
.csid_rdi_timestamp_curr1_eof_addr = 0x5a4, .timestamp_curr1_eof_addr = 0x5a4,
.csid_rdi_timestamp_prev0_eof_addr = 0x5a8, .timestamp_prev0_eof_addr = 0x5a8,
.csid_rdi_timestamp_prev1_eof_addr = 0x5ac, .timestamp_prev1_eof_addr = 0x5ac,
.csid_rdi_byte_cntr_ping_addr = 0x5e0, .byte_cntr_ping_addr = 0x5e0,
.csid_rdi_byte_cntr_pong_addr = 0x5e4, .byte_cntr_pong_addr = 0x5e4,
.halt_mode_internal = 0,
.halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.plain_fmt_shift_val = 10,
.packing_fmt_shift_val = 30,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.timestamp_en_shift_val = 2,
.format_measure_en_shift_val = 1,
}; };
static const struct cam_ife_csid_csi2_rx_reg_offset static struct cam_ife_csid_csi2_rx_reg_info
cam_ife_csid_lite_17x_csi2_reg_offset = { cam_ife_csid_lite_17x_csi2_reg_info = {
.csid_csi2_rx_irq_status_addr = 0x20, .irq_status_addr = 0x20,
.csid_csi2_rx_irq_mask_addr = 0x24, .irq_mask_addr = 0x24,
.csid_csi2_rx_irq_clear_addr = 0x28, .irq_clear_addr = 0x28,
.csid_csi2_rx_irq_set_addr = 0x2c, .irq_set_addr = 0x2c,
/*CSI2 rx control */ /*CSI2 rx control */
.csid_csi2_rx_cfg0_addr = 0x100, .cfg0_addr = 0x100,
.csid_csi2_rx_cfg1_addr = 0x104, .cfg1_addr = 0x104,
.csid_csi2_rx_capture_ctrl_addr = 0x108, .capture_ctrl_addr = 0x108,
.csid_csi2_rx_rst_strobes_addr = 0x110, .rst_strobes_addr = 0x110,
.csid_csi2_rx_de_scramble_cfg0_addr = 0x114, .de_scramble_cfg0_addr = 0x114,
.csid_csi2_rx_de_scramble_cfg1_addr = 0x118, .de_scramble_cfg1_addr = 0x118,
.csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr = 0x120, .cap_unmap_long_pkt_hdr_0_addr = 0x120,
.csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr = 0x124, .cap_unmap_long_pkt_hdr_1_addr = 0x124,
.csid_csi2_rx_captured_short_pkt_0_addr = 0x128, .captured_short_pkt_0_addr = 0x128,
.csid_csi2_rx_captured_short_pkt_1_addr = 0x12c, .captured_short_pkt_1_addr = 0x12c,
.csid_csi2_rx_captured_long_pkt_0_addr = 0x130, .captured_long_pkt_0_addr = 0x130,
.csid_csi2_rx_captured_long_pkt_1_addr = 0x134, .captured_long_pkt_1_addr = 0x134,
.csid_csi2_rx_captured_long_pkt_ftr_addr = 0x138, .captured_long_pkt_ftr_addr = 0x138,
.csid_csi2_rx_captured_cphy_pkt_hdr_addr = 0x13c, .captured_cphy_pkt_hdr_addr = 0x13c,
.csid_csi2_rx_lane0_misr_addr = 0x150, .lane0_misr_addr = 0x150,
.csid_csi2_rx_lane1_misr_addr = 0x154, .lane1_misr_addr = 0x154,
.csid_csi2_rx_lane2_misr_addr = 0x158, .lane2_misr_addr = 0x158,
.csid_csi2_rx_lane3_misr_addr = 0x15c, .lane3_misr_addr = 0x15c,
.csid_csi2_rx_total_pkts_rcvd_addr = 0x160, .total_pkts_rcvd_addr = 0x160,
.csid_csi2_rx_stats_ecc_addr = 0x164, .stats_ecc_addr = 0x164,
.csid_csi2_rx_total_crc_err_addr = 0x168, .total_crc_err_addr = 0x168,
.csi2_rst_srb_all = 0x3FFF, .rst_srb_all = 0x3FFF,
.csi2_rst_done_shift_val = 27, .rst_done_shift_val = 27,
.csi2_irq_mask_all = 0xFFFFFFF, .irq_mask_all = 0xFFFFFFF,
.csi2_misr_enable_shift_val = 6, .misr_enable_shift_val = 6,
.csi2_vc_mode_shift_val = 2, .vc_mode_shift_val = 2,
.csi2_capture_long_pkt_en_shift = 0, .capture_long_pkt_en_shift = 0,
.csi2_capture_short_pkt_en_shift = 1, .capture_short_pkt_en_shift = 1,
.csi2_capture_cphy_pkt_en_shift = 2, .capture_cphy_pkt_en_shift = 2,
.csi2_capture_long_pkt_dt_shift = 4, .capture_long_pkt_dt_shift = 4,
.csi2_capture_long_pkt_vc_shift = 10, .capture_long_pkt_vc_shift = 10,
.csi2_capture_short_pkt_vc_shift = 15, .capture_short_pkt_vc_shift = 15,
.csi2_capture_cphy_pkt_dt_shift = 20, .capture_cphy_pkt_dt_shift = 20,
.csi2_capture_cphy_pkt_vc_shift = 26, .capture_cphy_pkt_vc_shift = 26,
.csi2_rx_phy_num_mask = 0x3, .phy_num_mask = 0x3,
.fatal_err_mask = 0x78000,
.part_fatal_err_mask = 0x1801800,
.non_fatal_err_mask = 0x380000,
}; };
static const struct cam_ife_csid_csi2_tpg_reg_offset static struct cam_ife_csid_ver1_tpg_reg_info
cam_ife_csid_lite_17x_tpg_reg_offset = { cam_ife_csid_lite_17x_tpg_reg_info = {
/*CSID TPG control */ /*CSID TPG control */
.csid_tpg_ctrl_addr = 0x600, .ctrl_addr = 0x600,
.csid_tpg_vc_cfg0_addr = 0x604, .vc_cfg0_addr = 0x604,
.csid_tpg_vc_cfg1_addr = 0x608, .vc_cfg1_addr = 0x608,
.csid_tpg_lfsr_seed_addr = 0x60c, .lfsr_seed_addr = 0x60c,
.csid_tpg_dt_n_cfg_0_addr = 0x610, .dt_n_cfg_0_addr = 0x610,
.csid_tpg_dt_n_cfg_1_addr = 0x614, .dt_n_cfg_1_addr = 0x614,
.csid_tpg_dt_n_cfg_2_addr = 0x618, .dt_n_cfg_2_addr = 0x618,
.csid_tpg_color_bars_cfg_addr = 0x640, .color_bars_cfg_addr = 0x640,
.csid_tpg_color_box_cfg_addr = 0x644, .color_box_cfg_addr = 0x644,
.csid_tpg_common_gen_cfg_addr = 0x648, .common_gen_cfg_addr = 0x648,
.csid_tpg_cgen_n_cfg_addr = 0x650, .cgen_n_cfg_addr = 0x650,
.csid_tpg_cgen_n_x0_addr = 0x654, .cgen_n_x0_addr = 0x654,
.csid_tpg_cgen_n_x1_addr = 0x658, .cgen_n_x1_addr = 0x658,
.csid_tpg_cgen_n_x2_addr = 0x65c, .cgen_n_x2_addr = 0x65c,
.csid_tpg_cgen_n_xy_addr = 0x660, .cgen_n_xy_addr = 0x660,
.csid_tpg_cgen_n_y1_addr = 0x664, .cgen_n_y1_addr = 0x664,
.csid_tpg_cgen_n_y2_addr = 0x668, .cgen_n_y2_addr = 0x668,
/*configurations */ /* configurations */
.tpg_dtn_cfg_offset = 0xc, .dtn_cfg_offset = 0xc,
.tpg_cgen_cfg_offset = 0x20, .cgen_cfg_offset = 0x20,
.tpg_cpas_ife_reg_offset = 0x28, .cpas_ife_reg_offset = 0x28,
.hbi = 0x740,
.vbi = 0x3FF,
.ctrl_cfg = 0x408007,
.lfsr_seed = 0x12345678,
.color_bar = 1,
.num_frames = 0,
.line_interleave_mode = 0x1,
.payload_mode = 0x8,
.num_active_lanes_mask = 0x30,
.num_active_dt = 0,
.fmt_shift = 16,
.num_frame_shift = 16,
.width_shift = 16,
.vbi_shift = 12,
.line_interleave_shift = 10,
.num_active_dt_shift = 8,
.color_bar_shift = 5,
.height_shift = 0,
.hbi_shift = 0,
}; };
static const struct cam_ife_csid_common_reg_offset static struct cam_ife_csid_ver1_common_reg_info
cam_csid_lite_17x_cmn_reg_offset = { cam_csid_lite_17x_cmn_reg_info = {
.csid_hw_version_addr = 0x0, .hw_version_addr = 0x0,
.csid_cfg0_addr = 0x4, .cfg0_addr = 0x4,
.csid_ctrl_addr = 0x8, .ctrl_addr = 0x8,
.csid_reset_addr = 0xc, .reset_addr = 0xc,
.csid_rst_strobes_addr = 0x10, .rst_strobes_addr = 0x10,
.csid_test_bus_ctrl_addr = 0x14, .test_bus_ctrl_addr = 0x14,
.csid_top_irq_status_addr = 0x70, .top_irq_status_addr = 0x70,
.csid_top_irq_mask_addr = 0x74, .top_irq_mask_addr = 0x74,
.csid_top_irq_clear_addr = 0x78, .top_irq_clear_addr = 0x78,
.csid_top_irq_set_addr = 0x7c, .top_irq_set_addr = 0x7c,
.csid_irq_cmd_addr = 0x80, .irq_cmd_addr = 0x80,
/*configurations */ /*configurations */
.major_version = 1, .major_version = 1,
.minor_version = 7, .minor_version = 7,
.version_incr = 0, .version_incr = 0,
.num_rdis = 4, .num_rdis = 4,
.num_pix = 0, .num_pix = 0,
.csid_reg_rst_stb = 1, .timestamp_strobe_val = 0x2,
.csid_rst_stb = 0x1e, .timestamp_stb_sel_shift_val = 0,
.csid_rst_stb_sw_all = 0x1f, .rst_sw_reg_stb = 1,
.path_rst_stb_all = 0x7f, .rst_hw_reg_stb = 0x1e,
.path_rst_done_shift_val = 1, .rst_sw_hw_reg_stb = 0x1f,
.path_en_shift_val = 31, .path_rst_stb_all = 0x7f,
.packing_fmt_shift_val = 30, .rst_done_shift_val = 1,
.dt_id_shift_val = 27, .path_en_shift_val = 31,
.vc_shift_val = 22, .dt_id_shift_val = 27,
.dt_shift_val = 16, .vc_shift_val = 22,
.fmt_shift_val = 12, .dt_shift_val = 16,
.plain_fmt_shit_val = 10, .fmt_shift_val = 12,
.crop_v_en_shift_val = 6, .crop_shift_val = 16,
.crop_h_en_shift_val = 5, .decode_format_shift_val = 12,
.crop_shift = 16, .crop_pix_start_mask = 0x3fff,
.ipp_irq_mask_all = 0x7FFF, .crop_pix_end_mask = 0xffff,
.rdi_irq_mask_all = 0x7FFF, .crop_line_start_mask = 0x3fff,
.ppp_irq_mask_all = 0xFFFF, .crop_line_end_mask = 0xffff,
.ipp_irq_mask_all = 0x7FFF,
.rdi_irq_mask_all = 0x7FFF,
.ppp_irq_mask_all = 0xFFFF,
}; };
static const struct cam_ife_csid_reg_offset cam_ife_csid_lite_17x_reg_offset = { static struct cam_ife_csid_ver1_reg_info cam_ife_csid_lite_17x_reg_info = {
.cmn_reg = &cam_csid_lite_17x_cmn_reg_offset, .cmn_reg = &cam_csid_lite_17x_cmn_reg_info,
.csi2_reg = &cam_ife_csid_lite_17x_csi2_reg_offset, .csi2_reg = &cam_ife_csid_lite_17x_csi2_reg_info,
.ipp_reg = NULL, .ipp_reg = NULL,
.rdi_reg = { .rdi_reg = {
&cam_ife_csid_lite_17x_rdi_0_reg_offset, &cam_ife_csid_lite_17x_rdi_0_reg_info,
&cam_ife_csid_lite_17x_rdi_1_reg_offset, &cam_ife_csid_lite_17x_rdi_1_reg_info,
&cam_ife_csid_lite_17x_rdi_2_reg_offset, &cam_ife_csid_lite_17x_rdi_2_reg_info,
&cam_ife_csid_lite_17x_rdi_3_reg_offset, &cam_ife_csid_lite_17x_rdi_3_reg_info,
}, },
.tpg_reg = &cam_ife_csid_lite_17x_tpg_reg_offset, .tpg_reg = &cam_ife_csid_lite_17x_tpg_reg_info,
}; };
#endif /*_CAM_IFE_CSID_LITE17X_H_ */ #endif /*_CAM_IFE_CSID_LITE17X_H_ */

698
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite480.h
View File

@@ -1,340 +1,434 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* Copyright (c) 2019, The Linux Foundation. All rights reserved. * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
*/ */
#ifndef _CAM_IFE_CSID_LITE_480_H_ #ifndef _CAM_IFE_CSID_LITE_480_H_
#define _CAM_IFE_CSID_LITE_480_H_ #define _CAM_IFE_CSID_LITE_480_H_
#include "cam_ife_csid_core.h" #include "cam_ife_csid_common.h"
#include "cam_ife_csid_dev.h"
#include "cam_ife_csid_hw_ver1.h"
static struct cam_ife_csid_rdi_reg_offset static struct cam_ife_csid_ver1_path_reg_info
cam_ife_csid_lite_480_rdi_0_reg_offset = { cam_ife_csid_lite_480_rdi_0_reg_info = {
.csid_rdi_irq_status_addr = 0x30, .irq_status_addr = 0x30,
.csid_rdi_irq_mask_addr = 0x34, .irq_mask_addr = 0x34,
.csid_rdi_irq_clear_addr = 0x38, .irq_clear_addr = 0x38,
.csid_rdi_irq_set_addr = 0x3c, .irq_set_addr = 0x3c,
.csid_rdi_cfg0_addr = 0x200, .cfg0_addr = 0x200,
.csid_rdi_cfg1_addr = 0x204, .cfg1_addr = 0x204,
.csid_rdi_ctrl_addr = 0x208, .ctrl_addr = 0x208,
.csid_rdi_frm_drop_pattern_addr = 0x20c, .frm_drop_pattern_addr = 0x20c,
.csid_rdi_frm_drop_period_addr = 0x210, .frm_drop_period_addr = 0x210,
.csid_rdi_irq_subsample_pattern_addr = 0x214, .irq_subsample_pattern_addr = 0x214,
.csid_rdi_irq_subsample_period_addr = 0x218, .irq_subsample_period_addr = 0x218,
.csid_rdi_rpp_hcrop_addr = 0x21c, .hcrop_addr = 0x21c,
.csid_rdi_rpp_vcrop_addr = 0x220, .vcrop_addr = 0x220,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x224, .pix_drop_pattern_addr = 0x224,
.csid_rdi_rpp_pix_drop_period_addr = 0x228, .pix_drop_period_addr = 0x228,
.csid_rdi_rpp_line_drop_pattern_addr = 0x22c, .line_drop_pattern_addr = 0x22c,
.csid_rdi_rpp_line_drop_period_addr = 0x230, .line_drop_period_addr = 0x230,
.csid_rdi_rst_strobes_addr = 0x240, .rst_strobes_addr = 0x240,
.csid_rdi_status_addr = 0x250, .status_addr = 0x250,
.csid_rdi_misr_val0_addr = 0x254, .misr_val0_addr = 0x254,
.csid_rdi_misr_val1_addr = 0x258, .misr_val1_addr = 0x258,
.csid_rdi_misr_val2_addr = 0x25c, .misr_val2_addr = 0x25c,
.csid_rdi_misr_val3_addr = 0x260, .misr_val3_addr = 0x260,
.csid_rdi_format_measure_cfg0_addr = 0x270, .format_measure_cfg0_addr = 0x270,
.csid_rdi_format_measure_cfg1_addr = 0x274, .format_measure_cfg1_addr = 0x274,
.csid_rdi_format_measure0_addr = 0x278, .format_measure0_addr = 0x278,
.csid_rdi_format_measure1_addr = 0x27c, .format_measure1_addr = 0x27c,
.csid_rdi_format_measure2_addr = 0x280, .format_measure2_addr = 0x280,
.csid_rdi_timestamp_curr0_sof_addr = 0x290, .timestamp_curr0_sof_addr = 0x290,
.csid_rdi_timestamp_curr1_sof_addr = 0x294, .timestamp_curr1_sof_addr = 0x294,
.csid_rdi_timestamp_prev0_sof_addr = 0x298, .timestamp_prev0_sof_addr = 0x298,
.csid_rdi_timestamp_prev1_sof_addr = 0x29c, .timestamp_prev1_sof_addr = 0x29c,
.csid_rdi_timestamp_curr0_eof_addr = 0x2a0, .timestamp_curr0_eof_addr = 0x2a0,
.csid_rdi_timestamp_curr1_eof_addr = 0x2a4, .timestamp_curr1_eof_addr = 0x2a4,
.csid_rdi_timestamp_prev0_eof_addr = 0x2a8, .timestamp_prev0_eof_addr = 0x2a8,
.csid_rdi_timestamp_prev1_eof_addr = 0x2ac, .timestamp_prev1_eof_addr = 0x2ac,
.csid_rdi_err_recovery_cfg0_addr = 0x2b0, .err_recovery_cfg0_addr = 0x2b0,
.csid_rdi_err_recovery_cfg1_addr = 0x2b4, .err_recovery_cfg1_addr = 0x2b4,
.csid_rdi_err_recovery_cfg2_addr = 0x2b8, .err_recovery_cfg2_addr = 0x2b8,
.csid_rdi_multi_vcdt_cfg0_addr = 0x2bc, .multi_vcdt_cfg0_addr = 0x2bc,
.csid_rdi_byte_cntr_ping_addr = 0x2e0, .byte_cntr_ping_addr = 0x2e0,
.csid_rdi_byte_cntr_pong_addr = 0x2e4, .byte_cntr_pong_addr = 0x2e4,
/* configurations */ /* configurations */
.ccif_violation_en = 1, .halt_mode_internal = 0,
.overflow_ctrl_en = 1, .halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.drop_v_en_shift_val = 4,
.drop_h_en_shift_val = 3,
.plain_fmt_shift_val = 10,
.packing_fmt_shift_val = 30,
.mipi_pack_supported = 1,
.ccif_violation_en = 1,
.overflow_ctrl_en = 1,
.timestamp_en_shift_val = 2,
.format_measure_en_shift_val = 1,
.overflow_ctrl_mode_val = 0x8,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x28000,
}; };
static struct cam_ife_csid_rdi_reg_offset static struct cam_ife_csid_ver1_path_reg_info
cam_ife_csid_lite_480_rdi_1_reg_offset = { cam_ife_csid_lite_480_rdi_1_reg_info = {
.csid_rdi_irq_status_addr = 0x40, .irq_status_addr = 0x40,
.csid_rdi_irq_mask_addr = 0x44, .irq_mask_addr = 0x44,
.csid_rdi_irq_clear_addr = 0x48, .irq_clear_addr = 0x48,
.csid_rdi_irq_set_addr = 0x4c, .irq_set_addr = 0x4c,
.csid_rdi_cfg0_addr = 0x300, .cfg0_addr = 0x300,
.csid_rdi_cfg1_addr = 0x304, .cfg1_addr = 0x304,
.csid_rdi_ctrl_addr = 0x308, .ctrl_addr = 0x308,
.csid_rdi_frm_drop_pattern_addr = 0x30c, .frm_drop_pattern_addr = 0x30c,
.csid_rdi_frm_drop_period_addr = 0x310, .frm_drop_period_addr = 0x310,
.csid_rdi_irq_subsample_pattern_addr = 0x314, .irq_subsample_pattern_addr = 0x314,
.csid_rdi_irq_subsample_period_addr = 0x318, .irq_subsample_period_addr = 0x318,
.csid_rdi_rpp_hcrop_addr = 0x31c, .hcrop_addr = 0x31c,
.csid_rdi_rpp_vcrop_addr = 0x320, .vcrop_addr = 0x320,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x324, .pix_drop_pattern_addr = 0x324,
.csid_rdi_rpp_pix_drop_period_addr = 0x328, .pix_drop_period_addr = 0x328,
.csid_rdi_rpp_line_drop_pattern_addr = 0x32c, .line_drop_pattern_addr = 0x32c,
.csid_rdi_rpp_line_drop_period_addr = 0x330, .line_drop_period_addr = 0x330,
.csid_rdi_rst_strobes_addr = 0x340, .rst_strobes_addr = 0x340,
.csid_rdi_status_addr = 0x350, .status_addr = 0x350,
.csid_rdi_misr_val0_addr = 0x354, .misr_val0_addr = 0x354,
.csid_rdi_misr_val1_addr = 0x358, .misr_val1_addr = 0x358,
.csid_rdi_misr_val2_addr = 0x35c, .misr_val2_addr = 0x35c,
.csid_rdi_misr_val3_addr = 0x360, .misr_val3_addr = 0x360,
.csid_rdi_format_measure_cfg0_addr = 0x370, .format_measure_cfg0_addr = 0x370,
.csid_rdi_format_measure_cfg1_addr = 0x374, .format_measure_cfg1_addr = 0x374,
.csid_rdi_format_measure0_addr = 0x378, .format_measure0_addr = 0x378,
.csid_rdi_format_measure1_addr = 0x37c, .format_measure1_addr = 0x37c,
.csid_rdi_format_measure2_addr = 0x380, .format_measure2_addr = 0x380,
.csid_rdi_timestamp_curr0_sof_addr = 0x390, .timestamp_curr0_sof_addr = 0x390,
.csid_rdi_timestamp_curr1_sof_addr = 0x394, .timestamp_curr1_sof_addr = 0x394,
.csid_rdi_timestamp_prev0_sof_addr = 0x398, .timestamp_prev0_sof_addr = 0x398,
.csid_rdi_timestamp_prev1_sof_addr = 0x39c, .timestamp_prev1_sof_addr = 0x39c,
.csid_rdi_timestamp_curr0_eof_addr = 0x3a0, .timestamp_curr0_eof_addr = 0x3a0,
.csid_rdi_timestamp_curr1_eof_addr = 0x3a4, .timestamp_curr1_eof_addr = 0x3a4,
.csid_rdi_timestamp_prev0_eof_addr = 0x3a8, .timestamp_prev0_eof_addr = 0x3a8,
.csid_rdi_timestamp_prev1_eof_addr = 0x3ac, .timestamp_prev1_eof_addr = 0x3ac,
.csid_rdi_err_recovery_cfg0_addr = 0x3b0, .err_recovery_cfg0_addr = 0x3b0,
.csid_rdi_err_recovery_cfg1_addr = 0x3b4, .err_recovery_cfg1_addr = 0x3b4,
.csid_rdi_err_recovery_cfg2_addr = 0x3b8, .err_recovery_cfg2_addr = 0x3b8,
.csid_rdi_multi_vcdt_cfg0_addr = 0x3bc, .multi_vcdt_cfg0_addr = 0x3bc,
.csid_rdi_byte_cntr_ping_addr = 0x3e0, .byte_cntr_ping_addr = 0x3e0,
.csid_rdi_byte_cntr_pong_addr = 0x3e4, .byte_cntr_pong_addr = 0x3e4,
/* configurations */ /* configurations */
.ccif_violation_en = 1, .halt_mode_internal = 0,
.overflow_ctrl_en = 1, .halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.drop_v_en_shift_val = 4,
.drop_h_en_shift_val = 3,
.packing_fmt_shift_val = 30,
.plain_fmt_shift_val = 10,
.ccif_violation_en = 1,
.overflow_ctrl_en = 1,
.timestamp_en_shift_val = 2,
.format_measure_en_shift_val = 1,
.overflow_ctrl_mode_val = 0x8,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x28000,
}; };
static struct cam_ife_csid_rdi_reg_offset static struct cam_ife_csid_ver1_path_reg_info
cam_ife_csid_lite_480_rdi_2_reg_offset = { cam_ife_csid_lite_480_rdi_2_reg_info = {
.csid_rdi_irq_status_addr = 0x50, .irq_status_addr = 0x50,
.csid_rdi_irq_mask_addr = 0x54, .irq_mask_addr = 0x54,
.csid_rdi_irq_clear_addr = 0x58, .irq_clear_addr = 0x58,
.csid_rdi_irq_set_addr = 0x5c, .irq_set_addr = 0x5c,
.csid_rdi_cfg0_addr = 0x400, .cfg0_addr = 0x400,
.csid_rdi_cfg1_addr = 0x404, .cfg1_addr = 0x404,
.csid_rdi_ctrl_addr = 0x408, .ctrl_addr = 0x408,
.csid_rdi_frm_drop_pattern_addr = 0x40c, .frm_drop_pattern_addr = 0x40c,
.csid_rdi_frm_drop_period_addr = 0x410, .frm_drop_period_addr = 0x410,
.csid_rdi_irq_subsample_pattern_addr = 0x414, .irq_subsample_pattern_addr = 0x414,
.csid_rdi_irq_subsample_period_addr = 0x418, .irq_subsample_period_addr = 0x418,
.csid_rdi_rpp_hcrop_addr = 0x41c, .hcrop_addr = 0x41c,
.csid_rdi_rpp_vcrop_addr = 0x420, .vcrop_addr = 0x420,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x424, .pix_drop_pattern_addr = 0x424,
.csid_rdi_rpp_pix_drop_period_addr = 0x428, .pix_drop_period_addr = 0x428,
.csid_rdi_rpp_line_drop_pattern_addr = 0x42c, .line_drop_pattern_addr = 0x42c,
.csid_rdi_rpp_line_drop_period_addr = 0x430, .line_drop_period_addr = 0x430,
.csid_rdi_rst_strobes_addr = 0x440, .rst_strobes_addr = 0x440,
.csid_rdi_status_addr = 0x450, .status_addr = 0x450,
.csid_rdi_misr_val0_addr = 0x454, .misr_val0_addr = 0x454,
.csid_rdi_misr_val1_addr = 0x458, .misr_val1_addr = 0x458,
.csid_rdi_misr_val2_addr = 0x45c, .misr_val2_addr = 0x45c,
.csid_rdi_misr_val3_addr = 0x460, .misr_val3_addr = 0x460,
.csid_rdi_format_measure_cfg0_addr = 0x470, .format_measure_cfg0_addr = 0x470,
.csid_rdi_format_measure_cfg1_addr = 0x474, .format_measure_cfg1_addr = 0x474,
.csid_rdi_format_measure0_addr = 0x478, .format_measure0_addr = 0x478,
.csid_rdi_format_measure1_addr = 0x47c, .format_measure1_addr = 0x47c,
.csid_rdi_format_measure2_addr = 0x480, .format_measure2_addr = 0x480,
.csid_rdi_timestamp_curr0_sof_addr = 0x490, .timestamp_curr0_sof_addr = 0x490,
.csid_rdi_timestamp_curr1_sof_addr = 0x494, .timestamp_curr1_sof_addr = 0x494,
.csid_rdi_timestamp_prev0_sof_addr = 0x498, .timestamp_prev0_sof_addr = 0x498,
.csid_rdi_timestamp_prev1_sof_addr = 0x49c, .timestamp_prev1_sof_addr = 0x49c,
.csid_rdi_timestamp_curr0_eof_addr = 0x4a0, .timestamp_curr0_eof_addr = 0x4a0,
.csid_rdi_timestamp_curr1_eof_addr = 0x4a4, .timestamp_curr1_eof_addr = 0x4a4,
.csid_rdi_timestamp_prev0_eof_addr = 0x4a8, .timestamp_prev0_eof_addr = 0x4a8,
.csid_rdi_timestamp_prev1_eof_addr = 0x4ac, .timestamp_prev1_eof_addr = 0x4ac,
.csid_rdi_err_recovery_cfg0_addr = 0x4b0, .err_recovery_cfg0_addr = 0x4b0,
.csid_rdi_err_recovery_cfg1_addr = 0x4b4, .err_recovery_cfg1_addr = 0x4b4,
.csid_rdi_err_recovery_cfg2_addr = 0x4b8, .err_recovery_cfg2_addr = 0x4b8,
.csid_rdi_multi_vcdt_cfg0_addr = 0x4bc, .multi_vcdt_cfg0_addr = 0x4bc,
.csid_rdi_byte_cntr_ping_addr = 0x4e0, .byte_cntr_ping_addr = 0x4e0,
.csid_rdi_byte_cntr_pong_addr = 0x4e4, .byte_cntr_pong_addr = 0x4e4,
/* configurations */ /* configurations */
.ccif_violation_en = 1, .halt_mode_internal = 0,
.overflow_ctrl_en = 1, .halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.drop_v_en_shift_val = 4,
.drop_h_en_shift_val = 3,
.plain_fmt_shift_val = 10,
.packing_fmt_shift_val = 30,
.ccif_violation_en = 1,
.overflow_ctrl_en = 1,
.overflow_ctrl_mode_val = 0x8,
.timestamp_en_shift_val = 2,
.format_measure_en_shift_val = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x28000,
}; };
static struct cam_ife_csid_rdi_reg_offset static struct cam_ife_csid_ver1_path_reg_info
cam_ife_csid_lite_480_rdi_3_reg_offset = { cam_ife_csid_lite_480_rdi_3_reg_info = {
.csid_rdi_irq_status_addr = 0x60, .irq_status_addr = 0x60,
.csid_rdi_irq_mask_addr = 0x64, .irq_mask_addr = 0x64,
.csid_rdi_irq_clear_addr = 0x68, .irq_clear_addr = 0x68,
.csid_rdi_irq_set_addr = 0x6c, .irq_set_addr = 0x6c,
.csid_rdi_cfg0_addr = 0x500, .cfg0_addr = 0x500,
.csid_rdi_cfg1_addr = 0x504, .cfg1_addr = 0x504,
.csid_rdi_ctrl_addr = 0x508, .ctrl_addr = 0x508,
.csid_rdi_frm_drop_pattern_addr = 0x50c, .frm_drop_pattern_addr = 0x50c,
.csid_rdi_frm_drop_period_addr = 0x510, .frm_drop_period_addr = 0x510,
.csid_rdi_irq_subsample_pattern_addr = 0x514, .irq_subsample_pattern_addr = 0x514,
.csid_rdi_irq_subsample_period_addr = 0x518, .irq_subsample_period_addr = 0x518,
.csid_rdi_rpp_hcrop_addr = 0x51c, .hcrop_addr = 0x51c,
.csid_rdi_rpp_vcrop_addr = 0x520, .vcrop_addr = 0x520,
.csid_rdi_rpp_pix_drop_pattern_addr = 0x524, .pix_drop_pattern_addr = 0x524,
.csid_rdi_rpp_pix_drop_period_addr = 0x528, .pix_drop_period_addr = 0x528,
.csid_rdi_rpp_line_drop_pattern_addr = 0x52c, .line_drop_pattern_addr = 0x52c,
.csid_rdi_rpp_line_drop_period_addr = 0x530, .line_drop_period_addr = 0x530,
.csid_rdi_rst_strobes_addr = 0x540, .rst_strobes_addr = 0x540,
.csid_rdi_status_addr = 0x550, .status_addr = 0x550,
.csid_rdi_misr_val0_addr = 0x554, .misr_val0_addr = 0x554,
.csid_rdi_misr_val1_addr = 0x558, .misr_val1_addr = 0x558,
.csid_rdi_misr_val2_addr = 0x55c, .misr_val2_addr = 0x55c,
.csid_rdi_misr_val3_addr = 0x560, .misr_val3_addr = 0x560,
.csid_rdi_format_measure_cfg0_addr = 0x570, .format_measure_cfg0_addr = 0x570,
.csid_rdi_format_measure_cfg1_addr = 0x574, .format_measure_cfg1_addr = 0x574,
.csid_rdi_format_measure0_addr = 0x578, .format_measure0_addr = 0x578,
.csid_rdi_format_measure1_addr = 0x57c, .format_measure1_addr = 0x57c,
.csid_rdi_format_measure2_addr = 0x580, .format_measure2_addr = 0x580,
.csid_rdi_timestamp_curr0_sof_addr = 0x590, .timestamp_curr0_sof_addr = 0x590,
.csid_rdi_timestamp_curr1_sof_addr = 0x594, .timestamp_curr1_sof_addr = 0x594,
.csid_rdi_timestamp_prev0_sof_addr = 0x598, .timestamp_prev0_sof_addr = 0x598,
.csid_rdi_timestamp_prev1_sof_addr = 0x59c, .timestamp_prev1_sof_addr = 0x59c,
.csid_rdi_timestamp_curr0_eof_addr = 0x5a0, .timestamp_curr0_eof_addr = 0x5a0,
.csid_rdi_timestamp_curr1_eof_addr = 0x5a4, .timestamp_curr1_eof_addr = 0x5a4,
.csid_rdi_timestamp_prev0_eof_addr = 0x5a8, .timestamp_prev0_eof_addr = 0x5a8,
.csid_rdi_timestamp_prev1_eof_addr = 0x5ac, .timestamp_prev1_eof_addr = 0x5ac,
.csid_rdi_err_recovery_cfg0_addr = 0x5b0, .err_recovery_cfg0_addr = 0x5b0,
.csid_rdi_err_recovery_cfg1_addr = 0x5b4, .err_recovery_cfg1_addr = 0x5b4,
.csid_rdi_err_recovery_cfg2_addr = 0x5b8, .err_recovery_cfg2_addr = 0x5b8,
.csid_rdi_multi_vcdt_cfg0_addr = 0x5bc, .multi_vcdt_cfg0_addr = 0x5bc,
.csid_rdi_byte_cntr_ping_addr = 0x5e0, .byte_cntr_ping_addr = 0x5e0,
.csid_rdi_byte_cntr_pong_addr = 0x5e4, .byte_cntr_pong_addr = 0x5e4,
/* configurations */ /* configurations */
.ccif_violation_en = 1, .halt_mode_internal = 0,
.overflow_ctrl_en = 1, .halt_mode_global = 1,
.halt_mode_shift = 2,
.halt_frame_boundary = 0,
.resume_frame_boundary = 1,
.halt_immediate = 2,
.halt_cmd_shift = 0,
.crop_v_en_shift_val = 6,
.crop_h_en_shift_val = 5,
.drop_v_en_shift_val = 4,
.drop_h_en_shift_val = 3,
.plain_fmt_shift_val = 10,
.packing_fmt_shift_val = 30,
.ccif_violation_en = 1,
.overflow_ctrl_en = 1,
.timestamp_en_shift_val = 2,
.format_measure_en_shift_val = 1,
.overflow_ctrl_mode_val = 0x8,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x28000,
}; };
static struct cam_ife_csid_csi2_rx_reg_offset static struct cam_ife_csid_csi2_rx_reg_info
cam_ife_csid_lite_480_csi2_reg_offset = { cam_ife_csid_lite_480_csi2_reg_info = {
.csid_csi2_rx_irq_status_addr = 0x20, .irq_status_addr = 0x20,
.csid_csi2_rx_irq_mask_addr = 0x24, .irq_mask_addr = 0x24,
.csid_csi2_rx_irq_clear_addr = 0x28, .irq_clear_addr = 0x28,
.csid_csi2_rx_irq_set_addr = 0x2c, .irq_set_addr = 0x2c,
/*CSI2 rx control */ /*CSI2 rx control */
.csid_csi2_rx_cfg0_addr = 0x100, .cfg0_addr = 0x100,
.csid_csi2_rx_cfg1_addr = 0x104, .cfg1_addr = 0x104,
.csid_csi2_rx_capture_ctrl_addr = 0x108, .capture_ctrl_addr = 0x108,
.csid_csi2_rx_rst_strobes_addr = 0x110, .rst_strobes_addr = 0x110,
.csid_csi2_rx_de_scramble_cfg0_addr = 0x114, .de_scramble_cfg0_addr = 0x114,
.csid_csi2_rx_de_scramble_cfg1_addr = 0x118, .de_scramble_cfg1_addr = 0x118,
.csid_csi2_rx_cap_unmap_long_pkt_hdr_0_addr = 0x120, .cap_unmap_long_pkt_hdr_0_addr = 0x120,
.csid_csi2_rx_cap_unmap_long_pkt_hdr_1_addr = 0x124, .cap_unmap_long_pkt_hdr_1_addr = 0x124,
.csid_csi2_rx_captured_short_pkt_0_addr = 0x128, .captured_short_pkt_0_addr = 0x128,
.csid_csi2_rx_captured_short_pkt_1_addr = 0x12c, .captured_short_pkt_1_addr = 0x12c,
.csid_csi2_rx_captured_long_pkt_0_addr = 0x130, .captured_long_pkt_0_addr = 0x130,
.csid_csi2_rx_captured_long_pkt_1_addr = 0x134, .captured_long_pkt_1_addr = 0x134,
.csid_csi2_rx_captured_long_pkt_ftr_addr = 0x138, .captured_long_pkt_ftr_addr = 0x138,
.csid_csi2_rx_captured_cphy_pkt_hdr_addr = 0x13c, .captured_cphy_pkt_hdr_addr = 0x13c,
.csid_csi2_rx_lane0_misr_addr = 0x150, .lane0_misr_addr = 0x150,
.csid_csi2_rx_lane1_misr_addr = 0x154, .lane1_misr_addr = 0x154,
.csid_csi2_rx_lane2_misr_addr = 0x158, .lane2_misr_addr = 0x158,
.csid_csi2_rx_lane3_misr_addr = 0x15c, .lane3_misr_addr = 0x15c,
.csid_csi2_rx_total_pkts_rcvd_addr = 0x160, .total_pkts_rcvd_addr = 0x160,
.csid_csi2_rx_stats_ecc_addr = 0x164, .stats_ecc_addr = 0x164,
.csid_csi2_rx_total_crc_err_addr = 0x168, .total_crc_err_addr = 0x168,
.csi2_rst_srb_all = 0x3FFF, .rst_srb_all = 0x3FFF,
.csi2_rst_done_shift_val = 27, .rst_done_shift_val = 27,
.csi2_irq_mask_all = 0xFFFFFFF, .irq_mask_all = 0xFFFFFFF,
.csi2_misr_enable_shift_val = 6, .misr_enable_shift_val = 6,
.csi2_vc_mode_shift_val = 2, .vc_mode_shift_val = 2,
.csi2_capture_long_pkt_en_shift = 0, .capture_long_pkt_en_shift = 0,
.csi2_capture_short_pkt_en_shift = 1, .capture_short_pkt_en_shift = 1,
.csi2_capture_cphy_pkt_en_shift = 2, .capture_cphy_pkt_en_shift = 2,
.csi2_capture_long_pkt_dt_shift = 4, .capture_long_pkt_dt_shift = 4,
.csi2_capture_long_pkt_vc_shift = 10, .capture_long_pkt_vc_shift = 10,
.csi2_capture_short_pkt_vc_shift = 15, .capture_short_pkt_vc_shift = 15,
.csi2_capture_cphy_pkt_dt_shift = 20, .capture_cphy_pkt_dt_shift = 20,
.csi2_capture_cphy_pkt_vc_shift = 26, .capture_cphy_pkt_vc_shift = 26,
.csi2_rx_phy_num_mask = 0x7, .phy_num_mask = 0x7,
.fatal_err_mask = 0x78000,
.part_fatal_err_mask = 0x1801800,
.non_fatal_err_mask = 0x380000,
}; };
static struct cam_ife_csid_csi2_tpg_reg_offset static struct cam_ife_csid_ver1_tpg_reg_info
cam_ife_csid_lite_480_tpg_reg_offset = { cam_ife_csid_lite_480_tpg_reg_info = {
/*CSID TPG control */ /*CSID TPG control */
.csid_tpg_ctrl_addr = 0x600, .ctrl_addr = 0x600,
.csid_tpg_vc_cfg0_addr = 0x604, .vc_cfg0_addr = 0x604,
.csid_tpg_vc_cfg1_addr = 0x608, .vc_cfg1_addr = 0x608,
.csid_tpg_lfsr_seed_addr = 0x60c, .lfsr_seed_addr = 0x60c,
.csid_tpg_dt_n_cfg_0_addr = 0x610, .dt_n_cfg_0_addr = 0x610,
.csid_tpg_dt_n_cfg_1_addr = 0x614, .dt_n_cfg_1_addr = 0x614,
.csid_tpg_dt_n_cfg_2_addr = 0x618, .dt_n_cfg_2_addr = 0x618,
.csid_tpg_color_bars_cfg_addr = 0x640, .color_bars_cfg_addr = 0x640,
.csid_tpg_color_box_cfg_addr = 0x644, .color_box_cfg_addr = 0x644,
.csid_tpg_common_gen_cfg_addr = 0x648, .common_gen_cfg_addr = 0x648,
.csid_tpg_cgen_n_cfg_addr = 0x650, .cgen_n_cfg_addr = 0x650,
.csid_tpg_cgen_n_x0_addr = 0x654, .cgen_n_x0_addr = 0x654,
.csid_tpg_cgen_n_x1_addr = 0x658, .cgen_n_x1_addr = 0x658,
.csid_tpg_cgen_n_x2_addr = 0x65c, .cgen_n_x2_addr = 0x65c,
.csid_tpg_cgen_n_xy_addr = 0x660, .cgen_n_xy_addr = 0x660,
.csid_tpg_cgen_n_y1_addr = 0x664, .cgen_n_y1_addr = 0x664,
.csid_tpg_cgen_n_y2_addr = 0x668, .cgen_n_y2_addr = 0x668,
/* configurations */ /* configurations */
.tpg_dtn_cfg_offset = 0xc, .dtn_cfg_offset = 0xc,
.tpg_cgen_cfg_offset = 0x20, .cgen_cfg_offset = 0x20,
.tpg_cpas_ife_reg_offset = 0x28, .cpas_ife_reg_offset = 0x28,
.hbi = 0x740,
.vbi = 0x3FF,
.lfsr_seed = 0x12345678,
.ctrl_cfg = 0x408007,
.color_bar = 1,
.num_frames = 0,
.line_interleave_mode = 0x1,
.payload_mode = 0x8,
.num_active_lanes_mask = 0x30,
.num_active_dt = 0,
.fmt_shift = 16,
.num_frame_shift = 16,
.width_shift = 16,
.vbi_shift = 12,
.line_interleave_shift = 10,
.num_active_dt_shift = 8,
.color_bar_shift = 5,
.height_shift = 0,
.hbi_shift = 0,
}; };
static struct cam_ife_csid_common_reg_offset static struct cam_ife_csid_ver1_common_reg_info
cam_ife_csid_lite_480_cmn_reg_offset = { cam_ife_csid_lite_480_cmn_reg_info = {
.csid_hw_version_addr = 0x0, .hw_version_addr = 0x0,
.csid_cfg0_addr = 0x4, .cfg0_addr = 0x4,
.csid_ctrl_addr = 0x8, .ctrl_addr = 0x8,
.csid_reset_addr = 0xc, .reset_addr = 0xc,
.csid_rst_strobes_addr = 0x10, .rst_strobes_addr = 0x10,
.test_bus_ctrl_addr = 0x14,
.csid_test_bus_ctrl_addr = 0x14, .top_irq_status_addr = 0x70,
.csid_top_irq_status_addr = 0x70, .top_irq_mask_addr = 0x74,
.csid_top_irq_mask_addr = 0x74, .top_irq_clear_addr = 0x78,
.csid_top_irq_clear_addr = 0x78, .top_irq_set_addr = 0x7c,
.csid_top_irq_set_addr = 0x7c, .irq_cmd_addr = 0x80,
.csid_irq_cmd_addr = 0x80,
/*configurations */ /*configurations */
.major_version = 4, .major_version = 4,
.minor_version = 8, .minor_version = 8,
.version_incr = 0, .version_incr = 0,
.num_rdis = 4, .num_rdis = 4,
.num_pix = 0, .num_pix = 0,
.num_ppp = 0, .num_ppp = 0,
.csid_reg_rst_stb = 1, .rst_sw_reg_stb = 1,
.csid_rst_stb = 0x1e, .rst_hw_reg_stb = 0x1e,
.csid_rst_stb_sw_all = 0x1f, .rst_sw_hw_reg_stb = 0x1f,
.path_rst_stb_all = 0x7f, .path_rst_stb_all = 0x7f,
.path_rst_done_shift_val = 1, .rst_done_shift_val = 1,
.path_en_shift_val = 31, .path_en_shift_val = 31,
.packing_fmt_shift_val = 30, .dt_id_shift_val = 27,
.dt_id_shift_val = 27, .vc_shift_val = 22,
.vc_shift_val = 22, .dt_shift_val = 16,
.dt_shift_val = 16, .fmt_shift_val = 12,
.fmt_shift_val = 12, .crop_shift_val = 16,
.plain_fmt_shit_val = 10, .decode_format_shift_val = 12,
.crop_v_en_shift_val = 6, .crop_pix_start_mask = 0x3fff,
.crop_h_en_shift_val = 5, .crop_pix_end_mask = 0xffff,
.drop_v_en_shift_val = 4, .crop_line_start_mask = 0x3fff,
.drop_h_en_shift_val = 3, .crop_line_end_mask = 0xffff,
.crop_shift = 16, .ipp_irq_mask_all = 0x7FFF,
.ipp_irq_mask_all = 0x7FFF, .rdi_irq_mask_all = 0x7FFF,
.rdi_irq_mask_all = 0x7FFF, .ppp_irq_mask_all = 0xFFFF,
.ppp_irq_mask_all = 0xFFFF, .measure_en_hbi_vbi_cnt_mask = 0xC,
.measure_en_hbi_vbi_cnt_mask = 0xC, .timestamp_strobe_val = 0x2,
.format_measure_en_val = 1, .timestamp_stb_sel_shift_val = 0,
}; };
static struct cam_ife_csid_reg_offset cam_ife_csid_lite_480_reg_offset = { static struct cam_ife_csid_ver1_reg_info cam_ife_csid_lite_480_reg_info = {
.cmn_reg = &cam_ife_csid_lite_480_cmn_reg_offset, .cmn_reg = &cam_ife_csid_lite_480_cmn_reg_info,
.csi2_reg = &cam_ife_csid_lite_480_csi2_reg_offset, .csi2_reg = &cam_ife_csid_lite_480_csi2_reg_info,
.ipp_reg = NULL, .ipp_reg = NULL,
.ppp_reg = NULL, .ppp_reg = NULL,
.rdi_reg = { .rdi_reg = {
&cam_ife_csid_lite_480_rdi_0_reg_offset, &cam_ife_csid_lite_480_rdi_0_reg_info,
&cam_ife_csid_lite_480_rdi_1_reg_offset, &cam_ife_csid_lite_480_rdi_1_reg_info,
&cam_ife_csid_lite_480_rdi_2_reg_offset, &cam_ife_csid_lite_480_rdi_2_reg_info,
&cam_ife_csid_lite_480_rdi_3_reg_offset, &cam_ife_csid_lite_480_rdi_3_reg_info,
}, },
.tpg_reg = &cam_ife_csid_lite_480_tpg_reg_offset, .tpg_reg = &cam_ife_csid_lite_480_tpg_reg_info,
}; };
#endif /*_CAM_IFE_CSID_LITE_480_H_ */
#endif /*_CAM_IFE_CSID_LITE480_H_ */

585
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite680.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#ifndef _CAM_IFE_CSID_LITE_680_H_
#define _CAM_IFE_CSID_LITE_680_H_
#include "cam_ife_csid_common.h"
#include "cam_ife_csid_dev.h"
#include "cam_ife_csid_hw_ver2.h"
static struct cam_ife_csid_ver2_common_reg_info
cam_ife_csid_lite_680_cmn_reg_info = {
.hw_version_addr = 0x0,
.cfg0_addr = 0x4,
.global_cmd_addr = 0x8,
.reset_cfg_addr = 0xc,
.reset_cmd_addr = 0x10,
.irq_cmd_addr = 0x14,
.rup_aup_cmd_addr = 0x18,
.offline_cmd_addr = 0x1C,
.shdr_master_slave_cfg_addr = 0x20,
.top_irq_status_addr = 0x7C,
.top_irq_mask_addr = 0x80,
.top_irq_clear_addr = 0x84,
.top_irq_set_addr = 0x88,
.buf_done_irq_status_addr = 0x8C,
.buf_done_irq_mask_addr = 0x90,
.buf_done_irq_clear_addr = 0x94,
.buf_done_irq_set_addr = 0x98,
/*configurations */
.major_version = 6,
.minor_version = 8,
.version_incr = 0,
.num_rdis = 4,
.num_pix = 1,
.num_ppp = 0,
.rst_done_shift_val = 1,
.path_en_shift_val = 31,
.dt_id_shift_val = 27,
.vc_shift_val = 22,
.dt_shift_val = 16,
.crop_shift_val = 16,
.decode_format_shift_val = 12,
.frame_id_decode_en_shift_val = 1,
.multi_vcdt_vc1_shift_val = 2,
.multi_vcdt_dt1_shift_val = 7,
.multi_vcdt_en_shift_val = 0,
.timestamp_stb_sel_shift_val = 0,
.vfr_en_shift_val = 0,
.early_eof_supported = 1,
.vfr_supported = 1,
.multi_vcdt_supported = 1,
.frame_id_dec_supported = 1,
.measure_en_hbi_vbi_cnt_mask = 0xc,
.measure_pixel_line_en_mask = 0x3,
.crop_pix_start_mask = 0x3fff,
.crop_pix_end_mask = 0xffff,
.crop_line_start_mask = 0x3fff,
.crop_line_end_mask = 0xffff,
.drop_supported = 1,
.ipp_irq_mask_all = 0x7FFF,
.rdi_irq_mask_all = 0x7FFF,
.rst_loc_path_only_val = 0x0,
.rst_loc_complete_csid_val = 0x1,
.rst_mode_frame_boundary_val = 0x0,
.rst_mode_immediate_val = 0x1,
.rst_cmd_hw_reset_complete_val = 0x0,
.rst_cmd_sw_reset_complete_val = 0x1,
.rst_cmd_irq_ctrl_only_val = 0x2,
.timestamp_strobe_val = 0x2,
.top_reset_irq_shift_val = 0,
.global_reset = 1,
.rup_supported = 1,
};
static struct cam_ife_csid_csi2_rx_reg_info
cam_ife_csid_lite_680_csi2_reg_info = {
.irq_status_addr = 0x9C,
.irq_mask_addr = 0xA0,
.irq_clear_addr = 0xA4,
.irq_set_addr = 0xA8,
/*CSI2 rx control */
.cfg0_addr = 0x200,
.cfg1_addr = 0x204,
.capture_ctrl_addr = 0x208,
.rst_strobes_addr = 0x20C,
.cap_unmap_long_pkt_hdr_0_addr = 0x210,
.cap_unmap_long_pkt_hdr_1_addr = 0x214,
.captured_short_pkt_0_addr = 0x218,
.captured_short_pkt_1_addr = 0x21c,
.captured_long_pkt_0_addr = 0x220,
.captured_long_pkt_1_addr = 0x224,
.captured_long_pkt_ftr_addr = 0x228,
.captured_cphy_pkt_hdr_addr = 0x22c,
.lane0_misr_addr = 0x230,
.lane1_misr_addr = 0x234,
.lane2_misr_addr = 0x238,
.lane3_misr_addr = 0x23c,
.total_pkts_rcvd_addr = 0x240,
.stats_ecc_addr = 0x244,
.total_crc_err_addr = 0x248,
.de_scramble_type3_cfg0_addr = 0x24C,
.de_scramble_type3_cfg1_addr = 0x250,
.de_scramble_type2_cfg0_addr = 0x254,
.de_scramble_type2_cfg1_addr = 0x258,
.de_scramble_type1_cfg0_addr = 0x25C,
.de_scramble_type1_cfg1_addr = 0x260,
.de_scramble_type0_cfg0_addr = 0x264,
.de_scramble_type0_cfg1_addr = 0x268,
.rst_done_shift_val = 27,
.irq_mask_all = 0xFFFFFFF,
.misr_enable_shift_val = 6,
.vc_mode_shift_val = 2,
.capture_long_pkt_en_shift = 0,
.capture_short_pkt_en_shift = 1,
.capture_cphy_pkt_en_shift = 2,
.capture_long_pkt_dt_shift = 4,
.capture_long_pkt_vc_shift = 10,
.capture_short_pkt_vc_shift = 15,
.capture_cphy_pkt_dt_shift = 20,
.capture_cphy_pkt_vc_shift = 26,
.phy_num_mask = 0xf,
.vc_mask = 0x7C00000,
.dt_mask = 0x3f0000,
.wc_mask = 0xffff0000,
.calc_crc_mask = 0xffff,
.expected_crc_mask = 0xffff,
.ecc_correction_shift_en = 0,
.lane_num_shift = 0,
.lane_cfg_shift = 4,
.phy_type_shift = 24,
.phy_num_shift = 20,
.tpg_mux_en_shift = 27,
.phy_bist_shift_en = 7,
.epd_mode_shift_en = 8,
.eotp_shift_en = 9,
.dyn_sensor_switch_shift_en = 10,
.fatal_err_mask = 0x78000,
.part_fatal_err_mask = 0x1801800,
.non_fatal_err_mask = 0x380000,
};
static struct cam_ife_csid_ver2_pxl_reg_info
cam_ife_csid_lite_680_ipp_reg_info = {
.irq_status_addr = 0xAC,
.irq_mask_addr = 0xB0,
.irq_clear_addr = 0xB4,
.irq_set_addr = 0xB8,
.cfg0_addr = 0x300,
.ctrl_addr = 0x304,
.debug_clr_cmd_addr = 0x308,
.multi_vcdt_cfg0_addr = 0x30c,
.cfg1_addr = 0x310,
.err_recovery_cfg0_addr = 0x318,
.err_recovery_cfg1_addr = 0x31C,
.err_recovery_cfg2_addr = 0x320,
.camif_frame_cfg_addr = 0x330,
.epoch_irq_cfg_addr = 0x334,
.epoch0_subsample_ptrn_addr = 0x338,
.epoch1_subsample_ptrn_addr = 0x33C,
.debug_camif_1_addr = 0x340,
.debug_camif_0_addr = 0x344,
.debug_halt_status_addr = 0x348,
.debug_misr_val0_addr = 0x34C,
.debug_misr_val1_addr = 0x350,
.debug_misr_val2_addr = 0x354,
.debug_misr_val3_addr = 0x358,
.hcrop_addr = 0x35c,
.vcrop_addr = 0x360,
.pix_drop_pattern_addr = 0x364,
.pix_drop_period_addr = 0x368,
.line_drop_pattern_addr = 0x36C,
.line_drop_period_addr = 0x370,
.frm_drop_pattern_addr = 0x374,
.frm_drop_period_addr = 0x378,
.irq_subsample_pattern_addr = 0x37C,
.irq_subsample_period_addr = 0x380,
.format_measure_cfg0_addr = 0x384,
.format_measure_cfg1_addr = 0x388,
.format_measure0_addr = 0x38C,
.format_measure1_addr = 0x390,
.format_measure2_addr = 0x394,
.timestamp_curr0_sof_addr = 0x398,
.timestamp_curr1_sof_addr = 0x39C,
.timestamp_perv0_sof_addr = 0x3A0,
.timestamp_perv1_sof_addr = 0x3A4,
.timestamp_curr0_eof_addr = 0x3A8,
.timestamp_curr1_eof_addr = 0x3AC,
.timestamp_perv0_eof_addr = 0x3B0,
.timestamp_perv1_eof_addr = 0x3B4,
.batch_period_cfg_addr = 0x3C4,
.batch_stream_id_cfg_addr = 0x3C8,
.epoch0_cfg_batch_id0_addr = 0x3CC,
.epoch1_cfg_batch_id0_addr = 0x3D0,
.epoch0_cfg_batch_id1_addr = 0x3D4,
.epoch1_cfg_batch_id1_addr = 0x3D8,
.epoch0_cfg_batch_id2_addr = 0x3DC,
.epoch1_cfg_batch_id2_addr = 0x3E0,
.epoch0_cfg_batch_id3_addr = 0x3E4,
.epoch1_cfg_batch_id3_addr = 0x3E8,
.epoch0_cfg_batch_id4_addr = 0x3EC,
.epoch1_cfg_batch_id4_addr = 0x3F0,
.epoch0_cfg_batch_id5_addr = 0x3F4,
.epoch1_cfg_batch_id5_addr = 0x3F8,
/* configurations */
.start_mode_internal = 0x0,
.start_mode_global = 0x1,
.start_mode_master = 0x2,
.start_mode_slave = 0x3,
.start_mode_shift = 2,
.start_master_sel_val = 0,
.start_master_sel_shift = 4,
.resume_frame_boundary = 1,
.crop_v_en_shift_val = 13,
.crop_h_en_shift_val = 12,
.drop_v_en_shift_val = 11,
.drop_h_en_shift_val = 10,
.pix_store_en_shift_val = 14,
.early_eof_en_shift_val = 16,
.format_measure_en_shift_val = 8,
.timestamp_en_shift_val = 9,
.overflow_ctrl_en = 1,
.overflow_ctrl_mode_val = 0x8,
.min_hbi_shift_val = 4,
.start_master_sel_shift_val = 4,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x28000,
};
static struct cam_ife_csid_ver2_rdi_reg_info
cam_ife_csid_lite_680_rdi_0_reg_info = {
.irq_status_addr = 0xEC,
.irq_mask_addr = 0xF0,
.irq_clear_addr = 0xF4,
.irq_set_addr = 0xF8,
.cfg0_addr = 0x500,
.ctrl_addr = 0x504,
.debug_clr_cmd_addr = 0x508,
.multi_vcdt_cfg0_addr = 0x50c,
.cfg1_addr = 0x510,
.err_recovery_cfg0_addr = 0x514,
.err_recovery_cfg1_addr = 0x518,
.err_recovery_cfg2_addr = 0x51C,
.debug_byte_cntr_ping_addr = 0x520,
.debug_byte_cntr_pong_addr = 0x524,
.camif_frame_cfg_addr = 0x528,
.epoch_irq_cfg_addr = 0x52C,
.epoch0_subsample_ptrn_addr = 0x530,
.epoch1_subsample_ptrn_addr = 0x534,
.debug_camif_1_addr = 0x538,
.debug_camif_0_addr = 0x53C,
.frm_drop_pattern_addr = 0x540,
.frm_drop_period_addr = 0x540,
.irq_subsample_pattern_addr = 0x548,
.irq_subsample_period_addr = 0x54C,
.hcrop_addr = 0x550,
.vcrop_addr = 0x554,
.pix_drop_pattern_addr = 0x558,
.pix_drop_period_addr = 0x55C,
.line_drop_pattern_addr = 0x560,
.line_drop_period_addr = 0x564,
.debug_halt_status_addr = 0x568,
.debug_misr_val0_addr = 0x570,
.debug_misr_val1_addr = 0x574,
.debug_misr_val2_addr = 0x578,
.debug_misr_val3_addr = 0x57C,
.format_measure_cfg0_addr = 0x580,
.format_measure_cfg1_addr = 0x584,
.format_measure0_addr = 0x588,
.format_measure1_addr = 0x58C,
.format_measure2_addr = 0x590,
.timestamp_curr0_sof_addr = 0x594,
.timestamp_curr1_sof_addr = 0x598,
.timestamp_perv0_sof_addr = 0x59C,
.timestamp_perv1_sof_addr = 0x5A0,
.timestamp_curr0_eof_addr = 0x5A4,
.timestamp_curr1_eof_addr = 0x5A8,
.timestamp_perv0_eof_addr = 0x5AC,
.timestamp_perv1_eof_addr = 0x5B0,
.batch_period_cfg_addr = 0x5BC,
.batch_stream_id_cfg_addr = 0x5C0,
.epoch0_cfg_batch_id0_addr = 0x5C4,
.epoch1_cfg_batch_id0_addr = 0x5C8,
.epoch0_cfg_batch_id1_addr = 0x5CC,
.epoch1_cfg_batch_id1_addr = 0x5D0,
.epoch0_cfg_batch_id2_addr = 0x5D4,
.epoch1_cfg_batch_id2_addr = 0x5D8,
.epoch0_cfg_batch_id3_addr = 0x5DC,
.epoch1_cfg_batch_id3_addr = 0x5E0,
.epoch0_cfg_batch_id4_addr = 0x5E4,
.epoch1_cfg_batch_id4_addr = 0x5E8,
.epoch0_cfg_batch_id5_addr = 0x5EC,
.epoch1_cfg_batch_id5_addr = 0x5F0,
/* configurations */
.resume_frame_boundary = 1,
.overflow_ctrl_en = 1,
.overflow_ctrl_mode_val = 0x8,
.mipi_pack_supported = 1,
.packing_fmt_shift_val = 15,
.plain_alignment_shift_val = 11,
.plain_fmt_shift_val = 12,
.crop_v_en_shift_val = 8,
.crop_h_en_shift_val = 7,
.drop_v_en_shift_val = 6,
.drop_h_en_shift_val = 5,
.early_eof_en_shift_val = 14,
.format_measure_en_shift_val = 3,
.timestamp_en_shift_val = 4,
.debug_byte_cntr_rst_shift_val = 2,
.ccif_violation_en = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x28000,
};
static struct cam_ife_csid_ver2_rdi_reg_info
cam_ife_csid_lite_680_rdi_1_reg_info = {
.irq_status_addr = 0xFC,
.irq_mask_addr = 0x100,
.irq_clear_addr = 0x104,
.irq_set_addr = 0x108,
.cfg0_addr = 0x600,
.ctrl_addr = 0x604,
.debug_clr_cmd_addr = 0x608,
.multi_vcdt_cfg0_addr = 0x60c,
.cfg1_addr = 0x610,
.err_recovery_cfg0_addr = 0x614,
.err_recovery_cfg1_addr = 0x618,
.err_recovery_cfg2_addr = 0x61C,
.debug_byte_cntr_ping_addr = 0x620,
.debug_byte_cntr_pong_addr = 0x624,
.camif_frame_cfg_addr = 0x628,
.epoch_irq_cfg_addr = 0x62C,
.epoch0_subsample_ptrn_addr = 0x630,
.epoch1_subsample_ptrn_addr = 0x634,
.debug_camif_1_addr = 0x638,
.debug_camif_0_addr = 0x63C,
.frm_drop_pattern_addr = 0x640,
.frm_drop_period_addr = 0x644,
.irq_subsample_pattern_addr = 0x648,
.irq_subsample_period_addr = 0x64C,
.hcrop_addr = 0x650,
.vcrop_addr = 0x654,
.pix_drop_pattern_addr = 0x658,
.pix_drop_period_addr = 0x65C,
.line_drop_pattern_addr = 0x660,
.line_drop_period_addr = 0x664,
.debug_halt_status_addr = 0x66C,
.debug_misr_val0_addr = 0x670,
.debug_misr_val1_addr = 0x674,
.debug_misr_val2_addr = 0x678,
.debug_misr_val3_addr = 0x67C,
.format_measure_cfg0_addr = 0x680,
.format_measure_cfg1_addr = 0x684,
.format_measure0_addr = 0x688,
.format_measure1_addr = 0x68C,
.format_measure2_addr = 0x690,
.timestamp_curr0_sof_addr = 0x694,
.timestamp_curr1_sof_addr = 0x698,
.timestamp_perv0_sof_addr = 0x69C,
.timestamp_perv1_sof_addr = 0x6A0,
.timestamp_curr0_eof_addr = 0x6A4,
.timestamp_curr1_eof_addr = 0x6A8,
.timestamp_perv0_eof_addr = 0x6AC,
.timestamp_perv1_eof_addr = 0x6B0,
.batch_period_cfg_addr = 0x6BC,
.batch_stream_id_cfg_addr = 0x6C0,
.epoch0_cfg_batch_id0_addr = 0x6C4,
.epoch1_cfg_batch_id0_addr = 0x6C8,
.epoch0_cfg_batch_id1_addr = 0x6CC,
.epoch1_cfg_batch_id1_addr = 0x6D0,
.epoch0_cfg_batch_id2_addr = 0x6D4,
.epoch1_cfg_batch_id2_addr = 0x6D8,
.epoch0_cfg_batch_id3_addr = 0x6DC,
.epoch1_cfg_batch_id3_addr = 0x6E0,
.epoch0_cfg_batch_id4_addr = 0x6E4,
.epoch1_cfg_batch_id4_addr = 0x6E8,
.epoch0_cfg_batch_id5_addr = 0x6EC,
.epoch1_cfg_batch_id5_addr = 0x6F0,
/* configurations */
.resume_frame_boundary = 1,
.overflow_ctrl_en = 1,
.overflow_ctrl_mode_val = 0x8,
.packing_fmt_shift_val = 15,
.plain_alignment_shift_val = 11,
.plain_fmt_shift_val = 12,
.crop_v_en_shift_val = 8,
.crop_h_en_shift_val = 7,
.drop_v_en_shift_val = 6,
.drop_h_en_shift_val = 5,
.early_eof_en_shift_val = 14,
.format_measure_en_shift_val = 3,
.timestamp_en_shift_val = 4,
.debug_byte_cntr_rst_shift_val = 2,
.ccif_violation_en = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x28000,
};
static struct cam_ife_csid_ver2_rdi_reg_info
cam_ife_csid_lite_680_rdi_2_reg_info = {
.irq_status_addr = 0x10C,
.irq_mask_addr = 0x110,
.irq_clear_addr = 0x114,
.irq_set_addr = 0x118,
.cfg0_addr = 0x700,
.ctrl_addr = 0x704,
.debug_clr_cmd_addr = 0x708,
.multi_vcdt_cfg0_addr = 0x70c,
.cfg1_addr = 0x710,
.err_recovery_cfg0_addr = 0x714,
.err_recovery_cfg1_addr = 0x718,
.err_recovery_cfg2_addr = 0x71C,
.debug_byte_cntr_ping_addr = 0x720,
.debug_byte_cntr_pong_addr = 0x724,
.camif_frame_cfg_addr = 0x728,
.epoch_irq_cfg_addr = 0x72C,
.epoch0_subsample_ptrn_addr = 0x730,
.epoch1_subsample_ptrn_addr = 0x734,
.debug_camif_1_addr = 0x738,
.debug_camif_0_addr = 0x73C,
.frm_drop_pattern_addr = 0x740,
.frm_drop_period_addr = 0x744,
.irq_subsample_pattern_addr = 0x748,
.irq_subsample_period_addr = 0x74C,
.hcrop_addr = 0x750,
.vcrop_addr = 0x754,
.pix_drop_pattern_addr = 0x758,
.pix_drop_period_addr = 0x75C,
.line_drop_pattern_addr = 0x760,
.line_drop_period_addr = 0x764,
.debug_halt_status_addr = 0x76C,
.debug_misr_val0_addr = 0x770,
.debug_misr_val1_addr = 0x774,
.debug_misr_val2_addr = 0x778,
.debug_misr_val3_addr = 0x77C,
.format_measure_cfg0_addr = 0x780,
.format_measure_cfg1_addr = 0x784,
.format_measure0_addr = 0x788,
.format_measure1_addr = 0x78C,
.format_measure2_addr = 0x790,
.timestamp_curr0_sof_addr = 0x794,
.timestamp_curr1_sof_addr = 0x798,
.timestamp_perv0_sof_addr = 0x79C,
.timestamp_perv1_sof_addr = 0x7A0,
.timestamp_curr0_eof_addr = 0x7A4,
.timestamp_curr1_eof_addr = 0x7A8,
.timestamp_perv0_eof_addr = 0x7AC,
.timestamp_perv1_eof_addr = 0x7B0,
.batch_period_cfg_addr = 0x7BC,
.batch_stream_id_cfg_addr = 0x7C0,
.epoch0_cfg_batch_id0_addr = 0x7C4,
.epoch1_cfg_batch_id0_addr = 0x7C8,
.epoch0_cfg_batch_id1_addr = 0x7CC,
.epoch1_cfg_batch_id1_addr = 0x7D0,
.epoch0_cfg_batch_id2_addr = 0x7D4,
.epoch1_cfg_batch_id2_addr = 0x7D8,
.epoch0_cfg_batch_id3_addr = 0x7DC,
.epoch1_cfg_batch_id3_addr = 0x7E0,
.epoch0_cfg_batch_id4_addr = 0x7E4,
.epoch1_cfg_batch_id4_addr = 0x7E8,
.epoch0_cfg_batch_id5_addr = 0x7EC,
.epoch1_cfg_batch_id5_addr = 0x7F0,
/* configurations */
.resume_frame_boundary = 1,
.overflow_ctrl_en = 1,
.overflow_ctrl_mode_val = 0x8,
.packing_fmt_shift_val = 15,
.plain_alignment_shift_val = 11,
.plain_fmt_shift_val = 12,
.crop_v_en_shift_val = 8,
.crop_h_en_shift_val = 7,
.drop_v_en_shift_val = 6,
.drop_h_en_shift_val = 5,
.early_eof_en_shift_val = 14,
.format_measure_en_shift_val = 3,
.timestamp_en_shift_val = 4,
.debug_byte_cntr_rst_shift_val = 2,
.ccif_violation_en = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x28000,
};
static struct cam_ife_csid_ver2_rdi_reg_info
cam_ife_csid_lite_680_rdi_3_reg_info = {
.irq_status_addr = 0x11C,
.irq_mask_addr = 0x120,
.irq_clear_addr = 0x124,
.irq_set_addr = 0x128,
.cfg0_addr = 0x800,
.ctrl_addr = 0x804,
.debug_clr_cmd_addr = 0x808,
.multi_vcdt_cfg0_addr = 0x80c,
.cfg1_addr = 0x810,
.err_recovery_cfg0_addr = 0x814,
.err_recovery_cfg1_addr = 0x818,
.err_recovery_cfg2_addr = 0x81C,
.debug_byte_cntr_ping_addr = 0x820,
.debug_byte_cntr_pong_addr = 0x824,
.camif_frame_cfg_addr = 0x828,
.epoch_irq_cfg_addr = 0x82C,
.epoch0_subsample_ptrn_addr = 0x830,
.epoch1_subsample_ptrn_addr = 0x834,
.debug_camif_1_addr = 0x838,
.debug_camif_0_addr = 0x83C,
.frm_drop_pattern_addr = 0x840,
.frm_drop_period_addr = 0x840,
.irq_subsample_pattern_addr = 0x848,
.irq_subsample_period_addr = 0x84C,
.hcrop_addr = 0x850,
.vcrop_addr = 0x854,
.pix_drop_pattern_addr = 0x858,
.pix_drop_period_addr = 0x85C,
.line_drop_pattern_addr = 0x860,
.line_drop_period_addr = 0x864,
.debug_halt_status_addr = 0x868,
.debug_misr_val0_addr = 0x870,
.debug_misr_val1_addr = 0x874,
.debug_misr_val2_addr = 0x878,
.debug_misr_val3_addr = 0x87C,
.format_measure_cfg0_addr = 0x880,
.format_measure_cfg1_addr = 0x884,
.format_measure0_addr = 0x888,
.format_measure1_addr = 0x88C,
.format_measure2_addr = 0x890,
.timestamp_curr0_sof_addr = 0x894,
.timestamp_curr1_sof_addr = 0x898,
.timestamp_perv0_sof_addr = 0x89C,
.timestamp_perv1_sof_addr = 0x8A0,
.timestamp_curr0_eof_addr = 0x8A4,
.timestamp_curr1_eof_addr = 0x8A8,
.timestamp_perv0_eof_addr = 0x8AC,
.timestamp_perv1_eof_addr = 0x8B0,
.batch_period_cfg_addr = 0x8BC,
.batch_stream_id_cfg_addr = 0x8C0,
.epoch0_cfg_batch_id0_addr = 0x8C4,
.epoch1_cfg_batch_id0_addr = 0x8C8,
.epoch0_cfg_batch_id1_addr = 0x8CC,
.epoch1_cfg_batch_id1_addr = 0x8D0,
.epoch0_cfg_batch_id2_addr = 0x8D4,
.epoch1_cfg_batch_id2_addr = 0x8D8,
.epoch0_cfg_batch_id3_addr = 0x8DC,
.epoch1_cfg_batch_id3_addr = 0x8E0,
.epoch0_cfg_batch_id4_addr = 0x8E4,
.epoch1_cfg_batch_id4_addr = 0x8E8,
.epoch0_cfg_batch_id5_addr = 0x8EC,
.epoch1_cfg_batch_id5_addr = 0x8F0,
/* configurations */
.resume_frame_boundary = 1,
.overflow_ctrl_en = 1,
.overflow_ctrl_mode_val = 0x8,
.packing_fmt_shift_val = 15,
.plain_alignment_shift_val = 11,
.plain_fmt_shift_val = 12,
.crop_v_en_shift_val = 8,
.crop_h_en_shift_val = 7,
.drop_v_en_shift_val = 6,
.drop_h_en_shift_val = 5,
.early_eof_en_shift_val = 14,
.format_measure_en_shift_val = 3,
.timestamp_en_shift_val = 4,
.debug_byte_cntr_rst_shift_val = 2,
.ccif_violation_en = 1,
.fatal_err_mask = 0x4,
.non_fatal_err_mask = 0x28000,
};
static struct cam_ife_csid_ver2_reg_info cam_ife_csid_lite_680_reg_info = {
.cmn_reg = &cam_ife_csid_lite_680_cmn_reg_info,
.csi2_reg = &cam_ife_csid_lite_680_csi2_reg_info,
.ipp_reg = &cam_ife_csid_lite_680_ipp_reg_info,
.ppp_reg = NULL,
.rdi_reg = {
&cam_ife_csid_lite_680_rdi_0_reg_info,
&cam_ife_csid_lite_680_rdi_1_reg_info,
&cam_ife_csid_lite_680_rdi_2_reg_info,
&cam_ife_csid_lite_680_rdi_3_reg_info,
},
.need_top_cfg = 0,
};
#endif /* _CAM_IFE_CSID_LITE_680_H_ */

34
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite17x.c → drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite_mod.c
View File

@@ -1,23 +1,32 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/ */
#include <linux/module.h> #include <linux/module.h>
#include "camera_main.h"
#include "cam_ife_csid_dev.h"
#include "cam_ife_csid_common.h"
#include "cam_ife_csid_hw_ver1.h"
#include "cam_ife_csid_lite17x.h" #include "cam_ife_csid_lite17x.h"
#include "cam_ife_csid_lite480.h" #include "cam_ife_csid_lite480.h"
#include "cam_ife_csid_core.h" #include "cam_ife_csid_lite680.h"
#include "cam_ife_csid_dev.h"
#include "camera_main.h"
#define CAM_CSID_LITE_DRV_NAME "csid_lite" #define CAM_CSID_LITE_DRV_NAME "csid_lite"
static struct cam_ife_csid_hw_info cam_ife_csid_lite_17x_hw_info = { static struct cam_ife_csid_core_info cam_ife_csid_lite_17x_hw_info = {
.csid_reg = &cam_ife_csid_lite_17x_reg_offset, .csid_reg = &cam_ife_csid_lite_17x_reg_info,
.sw_version = CAM_IFE_CSID_VER_1_0,
}; };
static struct cam_ife_csid_hw_info cam_ife_csid_lite_480_hw_info = { static struct cam_ife_csid_core_info cam_ife_csid_lite_480_hw_info = {
.csid_reg = &cam_ife_csid_lite_480_reg_offset, .csid_reg = &cam_ife_csid_lite_480_reg_info,
.sw_version = CAM_IFE_CSID_VER_1_0,
};
static struct cam_ife_csid_core_info cam_ife_csid_lite_680_hw_info = {
.csid_reg = &cam_ife_csid_lite_680_reg_info,
.sw_version = CAM_IFE_CSID_VER_2_0,
}; };
static const struct of_device_id cam_ife_csid_lite_dt_match[] = { static const struct of_device_id cam_ife_csid_lite_dt_match[] = {
@@ -29,6 +38,10 @@ static const struct of_device_id cam_ife_csid_lite_dt_match[] = {
.compatible = "qcom,csid-lite175", .compatible = "qcom,csid-lite175",
.data = &cam_ife_csid_lite_17x_hw_info, .data = &cam_ife_csid_lite_17x_hw_info,
}, },
{
.compatible = "qcom,csid-lite165",
.data = &cam_ife_csid_lite_17x_hw_info,
},
{ {
.compatible = "qcom,csid-lite480", .compatible = "qcom,csid-lite480",
.data = &cam_ife_csid_lite_480_hw_info, .data = &cam_ife_csid_lite_480_hw_info,
@@ -37,8 +50,13 @@ static const struct of_device_id cam_ife_csid_lite_dt_match[] = {
.compatible = "qcom,csid-lite580", .compatible = "qcom,csid-lite580",
.data = &cam_ife_csid_lite_480_hw_info, .data = &cam_ife_csid_lite_480_hw_info,
}, },
{
.compatible = "qcom,csid-lite680",
.data = &cam_ife_csid_lite_680_hw_info,
},
{} {}
}; };
MODULE_DEVICE_TABLE(of, cam_ife_csid_lite_dt_match); MODULE_DEVICE_TABLE(of, cam_ife_csid_lite_dt_match);
struct platform_driver cam_ife_csid_lite_driver = { struct platform_driver cam_ife_csid_lite_driver = {

123
drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_mod.c Normal file
View File

@@ -0,0 +1,123 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
#include <linux/module.h>
#include "cam_ife_csid_dev.h"
#include "camera_main.h"
#include "cam_ife_csid_common.h"
#include "cam_ife_csid_hw_ver1.h"
#include "cam_ife_csid_hw_ver2.h"
#include "cam_ife_csid170.h"
#include "cam_ife_csid170_200.h"
#include "cam_ife_csid175.h"
#include "cam_ife_csid175_200.h"
#include "cam_ife_csid480.h"
#include "cam_ife_csid580.h"
#include "cam_ife_csid680.h"
#define CAM_CSID_DRV_NAME "csid"
static struct cam_ife_csid_core_info cam_ife_csid170_hw_info = {
.csid_reg = &cam_ife_csid_170_reg_info,
.sw_version = CAM_IFE_CSID_VER_1_0,
};
static struct cam_ife_csid_core_info cam_ife_csid170_200_hw_info = {
.csid_reg = &cam_ife_csid_170_200_reg_info,
.sw_version = CAM_IFE_CSID_VER_1_0,
};
static struct cam_ife_csid_core_info cam_ife_csid175_hw_info = {
.csid_reg = &cam_ife_csid_175_reg_info,
.sw_version = CAM_IFE_CSID_VER_1_0,
};
static struct cam_ife_csid_core_info cam_ife_csid175_200_hw_info = {
.csid_reg = &cam_ife_csid_175_200_reg_info,
.sw_version = CAM_IFE_CSID_VER_1_0,
};
static struct cam_ife_csid_core_info cam_ife_csid165_204_hw_info = {
.csid_reg = &cam_ife_csid_175_200_reg_info,
.sw_version = CAM_IFE_CSID_VER_1_0,
};
static struct cam_ife_csid_core_info cam_ife_csid480_hw_info = {
.csid_reg = &cam_ife_csid_480_reg_info,
.sw_version = CAM_IFE_CSID_VER_1_0,
};
static struct cam_ife_csid_core_info cam_ife_csid580_hw_info = {
.csid_reg = &cam_ife_csid_580_reg_info,
.sw_version = CAM_IFE_CSID_VER_1_0,
};
static struct cam_ife_csid_core_info cam_ife_csid680_hw_info = {
.csid_reg = &cam_ife_csid_680_reg_info,
.sw_version = CAM_IFE_CSID_VER_2_0,
};
static const struct of_device_id cam_ife_csid_dt_match[] = {
{
.compatible = "qcom,csid170",
.data = &cam_ife_csid170_hw_info,
},
{
.compatible = "qcom,csid170_200",
.data = &cam_ife_csid170_200_hw_info,
},
{
.compatible = "qcom,csid175",
.data = &cam_ife_csid175_hw_info,
},
{
.compatible = "qcom,csid175_200",
.data = &cam_ife_csid175_200_hw_info,
},
{
.compatible = "qcom,csid165_204",
.data = &cam_ife_csid165_204_hw_info,
},
{
.compatible = "qcom,csid480",
.data = &cam_ife_csid480_hw_info,
},
{
.compatible = "qcom,csid580",
.data = &cam_ife_csid580_hw_info,
},
{
.compatible = "qcom,csid680",
.data = &cam_ife_csid680_hw_info,
},
{},
};
MODULE_DEVICE_TABLE(of, cam_ife_csid_dt_match);
struct platform_driver cam_ife_csid_driver = {
.probe = cam_ife_csid_probe,
.remove = cam_ife_csid_remove,
.driver = {
.name = CAM_CSID_DRV_NAME,
.owner = THIS_MODULE,
.of_match_table = cam_ife_csid_dt_match,
.suppress_bind_attrs = true,
},
};
int cam_ife_csid_init_module(void)
{
return platform_driver_register(&cam_ife_csid_driver);
}
void cam_ife_csid_exit_module(void)
{
platform_driver_unregister(&cam_ife_csid_driver);
}
MODULE_DESCRIPTION("CAM IFE_CSID driver");
MODULE_LICENSE("GPL v2");

150
drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_ife_csid_hw_intf.h
View File

@@ -11,9 +11,19 @@
/* MAX IFE CSID instance */ /* MAX IFE CSID instance */
#define CAM_IFE_CSID_HW_NUM_MAX 7 #define CAM_IFE_CSID_HW_NUM_MAX 7
#define CAM_IFE_CSID_RDI_MAX 4
#define CAM_IFE_CSID_UDI_MAX 3 #define CAM_IFE_CSID_UDI_MAX 3
/**
* enum cam_ife_csid_input_core_type - Specify the csid input core
*/
enum cam_ife_csid_input_core_type {
CAM_IFE_CSID_INPUT_CORE_NONE,
CAM_IFE_CSID_INPUT_CORE_IFE,
CAM_IFE_CSID_INPUT_CORE_SFE_IFE,
CAM_IFE_CSID_INPUT_CORE_SFE,
CAM_IFE_CSID_INPUT_CORE_CUST_IFE,
};
/** /**
* enum cam_ife_pix_path_res_id - Specify the csid patch * enum cam_ife_pix_path_res_id - Specify the csid patch
*/ */
@@ -22,6 +32,7 @@ enum cam_ife_pix_path_res_id {
CAM_IFE_PIX_PATH_RES_RDI_1, CAM_IFE_PIX_PATH_RES_RDI_1,
CAM_IFE_PIX_PATH_RES_RDI_2, CAM_IFE_PIX_PATH_RES_RDI_2,
CAM_IFE_PIX_PATH_RES_RDI_3, CAM_IFE_PIX_PATH_RES_RDI_3,
CAM_IFE_PIX_PATH_RES_RDI_4,
CAM_IFE_PIX_PATH_RES_IPP, CAM_IFE_PIX_PATH_RES_IPP,
CAM_IFE_PIX_PATH_RES_PPP, CAM_IFE_PIX_PATH_RES_PPP,
CAM_IFE_PIX_PATH_RES_UDI_0, CAM_IFE_PIX_PATH_RES_UDI_0,
@@ -43,13 +54,15 @@ enum cam_ife_cid_res_id {
/** /**
* struct cam_ife_csid_hw_caps- get the CSID hw capability * struct cam_ife_csid_hw_caps- get the CSID hw capability
* @num_rdis: number of rdis supported by CSID HW device * @num_rdis: number of rdis supported by CSID HW device
* @num_pix: number of pxl paths supported by CSID HW device * @num_pix: number of pxl paths supported by CSID HW device
* @num_ppp: number of ppp paths supported by CSID HW device * @num_ppp: number of ppp paths supported by CSID HW device
* @major_version : major version * @major_version : major version
* @minor_version: minor version * @minor_version: minor version
* @version_incr: version increment * @version_incr: version increment
* @is_lite: is the ife_csid lite * @is_lite: is the ife_csid lite
* @global_reset_en: flag to indicate if global reset is enabled
* @rup_en: flag to indicate if rup is on csid side
*/ */
struct cam_ife_csid_hw_caps { struct cam_ife_csid_hw_caps {
uint32_t num_rdis; uint32_t num_rdis;
@@ -59,6 +72,8 @@ struct cam_ife_csid_hw_caps {
uint32_t minor_version; uint32_t minor_version;
uint32_t version_incr; uint32_t version_incr;
bool is_lite; bool is_lite;
bool global_reset_en;
bool rup_en;
}; };
struct cam_isp_out_port_generic_info { struct cam_isp_out_port_generic_info {
@@ -115,26 +130,33 @@ struct cam_isp_in_port_generic_info {
/** /**
* struct cam_csid_hw_reserve_resource- hw reserve * struct cam_csid_hw_reserve_resource- hw reserve
* @res_type : Reource type CID or PATH * @res_type : Reource type CID or PATH
* if type is CID, then res_id is not required, * if type is CID, then res_id is not required,
* if type is path then res id need to be filled * if type is path then res id need to be filled
* @res_id : Resource id to be reserved * @res_id : Resource id to be reserved
* @in_port : Input port resource info * @in_port : Input port resource info
* @out_port: Output port resource info, used for RDI path only * @out_port: Output port resource info, used for RDI path only
* @sync_mode: Sync mode * @sync_mode: Sync mode
* Sync mode could be master, slave or none * Sync mode could be master, slave or none
* @master_idx: Master device index to be configured in the slave path * @master_idx: Master device index to be configured in the
* for master path, this value is not required. * slave path
* only slave need to configure the master index value * for master path, this value is not required.
* @cid: cid (DT_ID) value for path, this is applicable for CSID path * only slave need to configure the master index value
* reserve * @dual_core_id: In case of dual csid, core id of another hw
* @node_res : Reserved resource structure pointer * reserve
* @crop_enable : Flag to indicate CSID crop enable * @node_res : Reserved resource structure pointer
* @drop_enable : Flag to indicate CSID drop enable * @crop_enable : Flag to indicate CSID crop enable
* @priv: private data to be sent in callback * @drop_enable : Flag to indicate CSID drop enable
* @event_cb: CSID event callback to hw manager * @sfe_inline_shdr: Flag to indicate if sfe is inline shdr
* @phy_sel: Phy selection number if tpg is enabled from userspace * @need_top_cfg: Flag to indicate if top cfg is needed
* @can_use_lite: Flag to indicate if current call qualifies for acquire lite * @tasklet: Tasklet to schedule bottom halves
* @buf_done_controller: IRQ controller for buf done for version 680 hw
* @cdm_ops: CDM Ops
* @event_cb: Callback function to hw mgr in case of hw events
* @cb_priv: Private pointer to return to callback
* @phy_sel: Phy selection number if tpg is enabled from userspace
* @can_use_lite: Flag to indicate if current call qualifies for
* acquire lite
* *
*/ */
struct cam_csid_hw_reserve_resource_args { struct cam_csid_hw_reserve_resource_args {
@@ -144,14 +166,19 @@ struct cam_csid_hw_reserve_resource_args {
struct cam_isp_out_port_generic_info *out_port; struct cam_isp_out_port_generic_info *out_port;
enum cam_isp_hw_sync_mode sync_mode; enum cam_isp_hw_sync_mode sync_mode;
uint32_t master_idx; uint32_t master_idx;
uint32_t cid; uint32_t dual_core_id;
struct cam_isp_resource_node *node_res; struct cam_isp_resource_node *node_res;
bool crop_enable; bool crop_enable;
bool drop_enable; bool drop_enable;
void *priv; bool sfe_inline_shdr;
bool need_top_cfg;
void *tasklet;
void *buf_done_controller;
void *cdm_ops;
cam_hw_mgr_event_cb_func event_cb; cam_hw_mgr_event_cb_func event_cb;
uint32_t phy_sel; uint32_t phy_sel;
bool can_use_lite; bool can_use_lite;
void *cb_priv;
}; };
/** /**
@@ -240,19 +267,6 @@ struct cam_csid_get_time_stamp_args {
uint64_t boot_timestamp; uint64_t boot_timestamp;
}; };
/**
* enum cam_ife_csid_cmd_type - Specify the csid command
*/
enum cam_ife_csid_cmd_type {
CAM_IFE_CSID_CMD_GET_TIME_STAMP,
CAM_IFE_CSID_SET_CSID_DEBUG,
CAM_IFE_CSID_SOF_IRQ_DEBUG,
CAM_IFE_CSID_SET_CONFIG,
CAM_IFE_CSID_SET_SENSOR_DIMENSION_CFG,
CAM_IFE_CSID_LOG_ACQUIRE_DATA,
CAM_IFE_CSID_CMD_MAX,
};
/** /**
* cam_ife_csid_hw_init() * cam_ife_csid_hw_init()
* *
@@ -276,9 +290,11 @@ struct cam_ife_csid_clock_update_args {
/* /*
* struct cam_ife_csid_qcfa_update_args: * struct cam_ife_csid_qcfa_update_args:
* *
* @res: Res node pointer
* @qcfa_binning: QCFA binning supported * @qcfa_binning: QCFA binning supported
*/ */
struct cam_ife_csid_qcfa_update_args { struct cam_ife_csid_qcfa_update_args {
struct cam_isp_resource_node *res;
uint32_t qcfa_binning; uint32_t qcfa_binning;
}; };
@@ -294,14 +310,50 @@ struct cam_ife_csid_epd_update_args {
/* /*
* struct cam_ife_sensor_dim_update_args: * struct cam_ife_sensor_dim_update_args:
* *
* @ppp_path: expected ppp path configuration * @res: Resource for which data is updated
* @ipp_path: expected ipp path configuration * @sensor_data: expected path configuration
* @rdi_path: expected rdi path configuration
*/ */
struct cam_ife_sensor_dimension_update_args { struct cam_ife_sensor_dimension_update_args {
struct cam_isp_sensor_dimension ppp_path; struct cam_isp_resource_node *res;
struct cam_isp_sensor_dimension ipp_path; struct cam_isp_sensor_dimension sensor_data;
struct cam_isp_sensor_dimension rdi_path[CAM_IFE_CSID_RDI_MAX];
}; };
/* struct cam_ife_csid_top_config_args:
*
* @input_core_type: Input core type for CSID
* @core_idx: Core idx for out core
* @is_sfe_offline: flag to indicate if sfe is offline
*/
struct cam_ife_csid_top_config_args {
uint32_t input_core_type;
uint32_t core_idx;
bool is_sfe_offline;
};
/*
* struct cam_ife_csid_dual_sync_args:
*
* @sync_mode: Sync mode for dual csid master/slave
* @dual_core_id: Core idx for another core in case of dual isp
*
*/
struct cam_ife_csid_dual_sync_args {
enum cam_isp_hw_sync_mode sync_mode;
uint32_t dual_core_id;
};
/*
* struct cam_ife_csid_get_cmd_reg_update:
*
* @cmd: cmd buf update args
* @node_res: Node res pointer
* @num_res: Num of resources
* @is_mup_update: Flag to indicate if mup update
*/
struct cam_ife_csid_reg_update_args {
struct cam_isp_hw_cmd_buf_update cmd;
struct cam_isp_resource_node *res[CAM_IFE_PIX_PATH_RES_MAX];
uint32_t num_res;
bool is_mup_update;
};
#endif /* _CAM_CSID_HW_INTF_H_ */ #endif /* _CAM_CSID_HW_INTF_H_ */

20
drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h
View File

@@ -18,6 +18,7 @@
#define CAM_ISP_HW_DUMP_TAG_MAX_LEN 32 #define CAM_ISP_HW_DUMP_TAG_MAX_LEN 32
/* Max isp hw pid values number */ /* Max isp hw pid values number */
#define CAM_ISP_HW_MAX_PID_VAL 4 #define CAM_ISP_HW_MAX_PID_VAL 4
/* /*
* struct cam_isp_timestamp: * struct cam_isp_timestamp:
* *
@@ -136,6 +137,15 @@ enum cam_isp_hw_cmd_type {
CAM_ISP_HW_CMD_DISABLE_UBWC_COMP, CAM_ISP_HW_CMD_DISABLE_UBWC_COMP,
CAM_ISP_HW_CMD_SET_SFE_DEBUG_CFG, CAM_ISP_HW_CMD_SET_SFE_DEBUG_CFG,
CAM_ISP_HW_CMD_QUERY_BUS_CAP, CAM_ISP_HW_CMD_QUERY_BUS_CAP,
CAM_IFE_CSID_CMD_GET_TIME_STAMP,
CAM_IFE_CSID_SET_CSID_DEBUG,
CAM_IFE_CSID_SOF_IRQ_DEBUG,
CAM_IFE_CSID_SET_CONFIG,
CAM_IFE_CSID_SET_SENSOR_DIMENSION_CFG,
CAM_IFE_CSID_LOG_ACQUIRE_DATA,
CAM_IFE_CSID_TOP_CONFIG,
CAM_IFE_CSID_PROGRAM_OFFLINE_CMD,
CAM_IFE_CSID_SET_DUAL_SYNC_CONFIG,
CAM_ISP_HW_CMD_MAX, CAM_ISP_HW_CMD_MAX,
}; };
@@ -289,13 +299,18 @@ struct cam_isp_hw_get_res_for_mid {
/* /*
* struct cam_isp_hw_get_cmd_update: * struct cam_isp_hw_get_cmd_update:
* *
* @Brief: Get cmd buffer update for different CMD types * @Brief: Get cmd buffer update for different CMD types
* *
* @res: Resource node * @res: Resource node
* @cmd_type: Command type for which to get update * @cmd_type: Command type for which to get update
* @cdm_id: CDM id * @cdm_id : CDM id
* @cmd: Command buffer information
* @res: Resource node
* @cmd_type: Command type for which to get update
* @cmd: Command buffer information * @cmd: Command buffer information
* @use_scratch_cfg: To indicate if it's scratch buffer config * @use_scratch_cfg: To indicate if it's scratch buffer config
* @trigger_cdm_en: Flag to indicate if cdm is trigger
* @is_mup_update: Flag to indicate if MUP is updated
* *
*/ */
struct cam_isp_hw_get_cmd_update { struct cam_isp_hw_get_cmd_update {
@@ -310,6 +325,7 @@ struct cam_isp_hw_get_cmd_update {
struct cam_isp_hw_get_wm_update *rm_update; struct cam_isp_hw_get_wm_update *rm_update;
}; };
bool trigger_cdm_en; bool trigger_cdm_en;
bool is_mup_update;
}; };
/* /*

2
drivers/camera_main.c
View File

@@ -89,7 +89,7 @@ static const struct camera_submodule_component camera_tfe[] = {
static const struct camera_submodule_component camera_isp[] = { static const struct camera_submodule_component camera_isp[] = {
#ifdef CONFIG_SPECTRA_ISP #ifdef CONFIG_SPECTRA_ISP
{&cam_top_tpg_init_module, &cam_top_tpg_exit_module}, {&cam_top_tpg_init_module, &cam_top_tpg_exit_module},
{&cam_ife_csid17x_init_module, &cam_ife_csid17x_exit_module}, {&cam_ife_csid_init_module, &cam_ife_csid_exit_module},
{&cam_ife_csid_lite_init_module, &cam_ife_csid_lite_exit_module}, {&cam_ife_csid_lite_init_module, &cam_ife_csid_lite_exit_module},
{&cam_vfe_init_module, &cam_vfe_exit_module}, {&cam_vfe_init_module, &cam_vfe_exit_module},
#ifdef CONFIG_SPECTRA_SFE #ifdef CONFIG_SPECTRA_SFE

4
drivers/camera_main.h
View File

@@ -16,7 +16,7 @@ extern struct platform_driver cam_cdm_intf_driver;
extern struct platform_driver cam_hw_cdm_driver; extern struct platform_driver cam_hw_cdm_driver;
#ifdef CONFIG_SPECTRA_ISP #ifdef CONFIG_SPECTRA_ISP
extern struct platform_driver cam_top_tpg_driver; extern struct platform_driver cam_top_tpg_driver;
extern struct platform_driver cam_ife_csid17x_driver; extern struct platform_driver cam_ife_csid_driver;
extern struct platform_driver cam_ife_csid_lite_driver; extern struct platform_driver cam_ife_csid_lite_driver;
extern struct platform_driver cam_vfe_driver; extern struct platform_driver cam_vfe_driver;
#ifdef CONFIG_SPECTRA_SFE #ifdef CONFIG_SPECTRA_SFE
@@ -89,7 +89,7 @@ static struct platform_driver *const cam_component_drivers[] = {
#endif #endif
#ifdef CONFIG_SPECTRA_ISP #ifdef CONFIG_SPECTRA_ISP
&cam_top_tpg_driver, &cam_top_tpg_driver,
&cam_ife_csid17x_driver, &cam_ife_csid_driver,
&cam_ife_csid_lite_driver, &cam_ife_csid_lite_driver,
&cam_vfe_driver, &cam_vfe_driver,
#ifdef CONFIG_SPECTRA_SFE #ifdef CONFIG_SPECTRA_SFE

2
include/uapi/camera/media/cam_isp.h
View File

@@ -163,7 +163,7 @@
#define CAM_ISP_ACQ_CUSTOM_PRIMARY 1 #define CAM_ISP_ACQ_CUSTOM_PRIMARY 1
#define CAM_ISP_ACQ_CUSTOM_SECONDARY 2 #define CAM_ISP_ACQ_CUSTOM_SECONDARY 2
#define CAM_IFE_CSID_RDI_MAX 4 #define CAM_IFE_CSID_RDI_MAX 5
/* Feature Flag indicators */ /* Feature Flag indicators */
#define CAM_ISP_PARAM_FETCH_SECURITY_MODE BIT(0) #define CAM_ISP_PARAM_FETCH_SECURITY_MODE BIT(0)