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@@ -1,6 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0-only
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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/*
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* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
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+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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*/
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#include "cam_cci_dev.h"
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#include "cam_cci_dev.h"
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@@ -289,18 +290,28 @@ irqreturn_t cam_cci_irq(int irq_num, void *data)
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if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_ERROR_BMSK) {
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if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_ERROR_BMSK) {
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cci_dev->cci_master_info[MASTER_0].status = -EINVAL;
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cci_dev->cci_master_info[MASTER_0].status = -EINVAL;
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if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERROR_BMSK) {
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if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERROR_BMSK) {
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- CAM_ERR(CAM_CCI,
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- "Base:%pK,cci: %d, M0_Q0 NACK ERROR: 0x%x",
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- base, cci_dev->soc_info.index, irq_status0);
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+ if (cci_dev->is_probing)
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+ CAM_INFO(CAM_CCI,
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+ "Base:%pK,cci: %d, M0_Q0 NACK ERROR: 0x%x",
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+ base, cci_dev->soc_info.index, irq_status0);
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+ else
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+ CAM_ERR(CAM_CCI,
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+ "Base:%pK,cci: %d, M0_Q0 NACK ERROR: 0x%x",
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+ base, cci_dev->soc_info.index, irq_status0);
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cam_cci_dump_registers(cci_dev, MASTER_0,
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cam_cci_dump_registers(cci_dev, MASTER_0,
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QUEUE_0);
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QUEUE_0);
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complete_all(&cci_dev->cci_master_info[MASTER_0]
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complete_all(&cci_dev->cci_master_info[MASTER_0]
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.report_q[QUEUE_0]);
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.report_q[QUEUE_0]);
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}
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}
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if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERROR_BMSK) {
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if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERROR_BMSK) {
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- CAM_ERR(CAM_CCI,
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- "Base:%pK,cci: %d, M0_Q1 NACK ERROR: 0x%x",
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- base, cci_dev->soc_info.index, irq_status0);
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+ if (cci_dev->is_probing)
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+ CAM_INFO(CAM_CCI,
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+ "Base:%pK,cci: %d, M0_Q1 NACK ERROR: 0x%x",
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+ base, cci_dev->soc_info.index, irq_status0);
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+ else
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+ CAM_ERR(CAM_CCI,
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+ "Base:%pK,cci: %d, M0_Q1 NACK ERROR: 0x%x",
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+ base, cci_dev->soc_info.index, irq_status0);
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cam_cci_dump_registers(cci_dev, MASTER_0,
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cam_cci_dump_registers(cci_dev, MASTER_0,
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QUEUE_1);
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QUEUE_1);
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complete_all(&cci_dev->cci_master_info[MASTER_0]
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complete_all(&cci_dev->cci_master_info[MASTER_0]
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@@ -321,18 +332,28 @@ irqreturn_t cam_cci_irq(int irq_num, void *data)
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if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_ERROR_BMSK) {
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if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_ERROR_BMSK) {
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cci_dev->cci_master_info[MASTER_1].status = -EINVAL;
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cci_dev->cci_master_info[MASTER_1].status = -EINVAL;
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if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERROR_BMSK) {
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if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERROR_BMSK) {
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- CAM_ERR(CAM_CCI,
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- "Base:%pK, cci: %d, M1_Q0 NACK ERROR: 0x%x",
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- base, cci_dev->soc_info.index, irq_status0);
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+ if (cci_dev->is_probing)
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+ CAM_INFO(CAM_CCI,
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+ "Base:%pK, cci: %d, M1_Q0 NACK ERROR: 0x%x",
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+ base, cci_dev->soc_info.index, irq_status0);
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+ else
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+ CAM_ERR(CAM_CCI,
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+ "Base:%pK, cci: %d, M1_Q0 NACK ERROR: 0x%x",
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+ base, cci_dev->soc_info.index, irq_status0);
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cam_cci_dump_registers(cci_dev, MASTER_1,
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cam_cci_dump_registers(cci_dev, MASTER_1,
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QUEUE_0);
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QUEUE_0);
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complete_all(&cci_dev->cci_master_info[MASTER_1]
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complete_all(&cci_dev->cci_master_info[MASTER_1]
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.report_q[QUEUE_0]);
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.report_q[QUEUE_0]);
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}
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}
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if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERROR_BMSK) {
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if (irq_status0 & CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERROR_BMSK) {
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- CAM_ERR(CAM_CCI,
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- "Base:%pK, cci: %d, M1_Q1 NACK ERROR: 0x%x",
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- base, cci_dev->soc_info.index, irq_status0);
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+ if (cci_dev->is_probing)
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+ CAM_INFO(CAM_CCI,
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+ "Base:%pK, cci: %d, M1_Q1 NACK ERROR: 0x%x",
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+ base, cci_dev->soc_info.index, irq_status0);
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+ else
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+ CAM_ERR(CAM_CCI,
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+ "Base:%pK, cci: %d, M1_Q1 NACK ERROR: 0x%x",
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+ base, cci_dev->soc_info.index, irq_status0);
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cam_cci_dump_registers(cci_dev, MASTER_1,
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cam_cci_dump_registers(cci_dev, MASTER_1,
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QUEUE_1);
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QUEUE_1);
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complete_all(&cci_dev->cci_master_info[MASTER_1]
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complete_all(&cci_dev->cci_master_info[MASTER_1]
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