msm: ipa: Updating the con pipe TRE structure as per uc

Updating the consumer pipe TRE structure as per uc.

Also, saving the virtual addresses during  allocation of uc producer
transfer or event rings, and its consumer transfer rings separately
to free them in failure scenarios.

Change-Id: I928c97c8f65418628d1bc7c1662d9e6a03f9d610
Signed-off-by: Prasad Arepalli <[email protected]>

drivers/platform/msm/ipa/ipa_v3/ipa_uc_rtp.c

@@ -25,8 +25,6 @@
 #define MAX_UC_PROD_PIPES_ER_INDEX (MAX_UC_PROD_PIPES_TR_INDEX + MAX_UC_PROD_PIPES)
 #define MAX_UC_CONS_PIPES_TR_INDEX (MAX_UC_PROD_PIPES_ER_INDEX + MAX_UC_CONS_PIPES)
 
-#define ER_TR_UC_BUFFS (MAX_UC_PROD_PIPES + MAX_UC_PROD_PIPES + MAX_UC_CONS_PIPES)
-
 #define MAX_SYNX_FENCE_SESSION_NAME  64
 #define DMA_DIR DMA_BIDIRECTIONAL
 
@@ -105,17 +103,15 @@ struct prod_pipe_tre {
 } __packed;
 
 struct con_pipe_tre {
-	uint64_t buffer_ptr;
-	uint16_t buf_len;
-	uint16_t resvd1;
-	uint16_t chain:1;
-	uint16_t resvd4:7;
-	uint16_t ieob:1;
-	uint16_t ieot:1;
-	uint16_t bei:1;
-	uint16_t resvd3:5;
-	uint8_t re_type;
-	uint8_t resvd2;
+	uint16_t bufferIndex;
+	uint16_t offset2Payload;
+	uint16_t payloadSize:16;
+	uint8_t  valid:1;
+	uint8_t  ieot:1;
+	uint8_t  tre_type:2;
+	uint8_t  reserved0:4;
+	uint8_t  last_tre:1;
+	uint8_t  reserved1:7;
 } __packed;
 
 struct temp_buff_info {
@@ -147,9 +143,13 @@ struct uc_temp_buffer_info {
 } __packed;
 
 struct er_tr_to_free {
-	void *cpu_address[ER_TR_UC_BUFFS];
+	void *cpu_address_prod_tr[MAX_UC_PROD_PIPES];
+	void *cpu_address_prod_er[MAX_UC_PROD_PIPES];
+	void *cpu_address_cons_tr[MAX_UC_CONS_PIPES];
 	struct rtp_pipe_setup_cmd_data rtp_tr_er;
-	uint16_t no_buffs;
+	uint8_t prod_tr_no_buffs;
+	uint8_t prod_er_no_buffs;
+	uint8_t cons_tr_no_buffs;
 } __packed;
 
 struct er_tr_to_free er_tr_cpu_addresses;
@@ -513,8 +513,8 @@ static int ipa3_uc_setup_prod_pipe_transfer_ring(
 
 	rtp_cmd_data->uc_prod_tr[idx].temp_buff_pa = ring.phys_base;
 	rtp_cmd_data->uc_prod_tr[idx].temp_buff_size = ring.size;
-	er_tr_cpu_addresses.cpu_address[er_tr_cpu_addresses.no_buffs] = ring.base;
-	er_tr_cpu_addresses.no_buffs += 1;
+	er_tr_cpu_addresses.cpu_address_prod_tr[idx] = ring.base;
+	er_tr_cpu_addresses.prod_tr_no_buffs += 1;
 	IPADBG("prod pipe transfer ring setup done\n");
 	return 0;
 }
@@ -539,8 +539,8 @@ static int ipa3_uc_setup_prod_pipe_event_ring(
 
 	rtp_cmd_data->uc_prod_er[index].temp_buff_pa = ring.phys_base;
 	rtp_cmd_data->uc_prod_er[index].temp_buff_size = ring.size;
-	er_tr_cpu_addresses.cpu_address[er_tr_cpu_addresses.no_buffs] = ring.base;
-	er_tr_cpu_addresses.no_buffs += 1;
+	er_tr_cpu_addresses.cpu_address_prod_er[index] = ring.base;
+	er_tr_cpu_addresses.prod_er_no_buffs += 1;
 	IPADBG("prod pipe event ring setup done\n");
 	return 0;
 }
@@ -565,45 +565,35 @@ static int ipa3_uc_setup_con_pipe_transfer_ring(
 
 	rtp_cmd_data->uc_cons_tr[index].temp_buff_pa = ring.phys_base;
 	rtp_cmd_data->uc_cons_tr[index].temp_buff_size = ring.size;
-	er_tr_cpu_addresses.cpu_address[er_tr_cpu_addresses.no_buffs] = ring.base;
-	er_tr_cpu_addresses.no_buffs += 1;
+	er_tr_cpu_addresses.cpu_address_cons_tr[index] = ring.base;
+	er_tr_cpu_addresses.cons_tr_no_buffs += 1;
 	IPADBG("con pipe transfer ring setup done\n");
 	return 0;
 }
 
 void ipa3_free_uc_pipes_er_tr(void)
 {
-	uint16_t index = 0;
-
-	for (index = 0; index < er_tr_cpu_addresses.no_buffs; index++) {
-		if (index < MAX_UC_PROD_PIPES_TR_INDEX) {
-			dma_free_coherent(ipa3_ctx->uc_pdev,
-			er_tr_cpu_addresses.rtp_tr_er.uc_prod_tr[index].temp_buff_size,
-			er_tr_cpu_addresses.cpu_address[index],
-			er_tr_cpu_addresses.rtp_tr_er.uc_prod_tr[index].temp_buff_pa);
-		} else if (index >= MAX_UC_PROD_PIPES_TR_INDEX &&
-				index < MAX_UC_PROD_PIPES_ER_INDEX) {
-			/* subtracting MAX_UC_PROD_TR_INDEX here because,
-			 * uc_prod_er[] is of size MAX_UC_PROD_PIPES only
-			 */
-			dma_free_coherent(ipa3_ctx->uc_pdev,
-			er_tr_cpu_addresses.rtp_tr_er.uc_prod_er[index
-					-MAX_UC_PROD_PIPES_TR_INDEX].temp_buff_size,
-			er_tr_cpu_addresses.cpu_address[index],
-			er_tr_cpu_addresses.rtp_tr_er.uc_prod_er[index
-					-MAX_UC_PROD_PIPES_TR_INDEX].temp_buff_pa);
-		} else if (index >= MAX_UC_PROD_PIPES_ER_INDEX &&
-				index < MAX_UC_CONS_PIPES_TR_INDEX) {
-			/* subtracting MAX_UC_PROD_TR_INDEX here because,
-			 * uc_cons_tr[] is of size MAX_UC_CONS_PIPES only
-			 */
-			dma_free_coherent(ipa3_ctx->uc_pdev,
-			er_tr_cpu_addresses.rtp_tr_er.uc_cons_tr[index
-					-MAX_UC_PROD_PIPES_ER_INDEX].temp_buff_size,
-			er_tr_cpu_addresses.cpu_address[index],
-			er_tr_cpu_addresses.rtp_tr_er.uc_cons_tr[index
-					-MAX_UC_PROD_PIPES_ER_INDEX].temp_buff_pa);
-		}
+	uint8_t index = 0;
+
+	for (index = 0; index < er_tr_cpu_addresses.prod_tr_no_buffs; index++) {
+		dma_free_coherent(ipa3_ctx->uc_pdev,
+		er_tr_cpu_addresses.rtp_tr_er.uc_prod_tr[index].temp_buff_size,
+		er_tr_cpu_addresses.cpu_address_prod_tr[index],
+		er_tr_cpu_addresses.rtp_tr_er.uc_prod_tr[index].temp_buff_pa);
+	}
+
+	for (index = 0; index < er_tr_cpu_addresses.prod_er_no_buffs; index++) {
+		dma_free_coherent(ipa3_ctx->uc_pdev,
+		er_tr_cpu_addresses.rtp_tr_er.uc_prod_er[index].temp_buff_size,
+		er_tr_cpu_addresses.cpu_address_prod_er[index],
+		er_tr_cpu_addresses.rtp_tr_er.uc_prod_er[index].temp_buff_pa);
+	}
+
+	for (index = 0; index < er_tr_cpu_addresses.cons_tr_no_buffs; index++) {
+		dma_free_coherent(ipa3_ctx->uc_pdev,
+		er_tr_cpu_addresses.rtp_tr_er.uc_cons_tr[index].temp_buff_size,
+		er_tr_cpu_addresses.cpu_address_cons_tr[index],
+		er_tr_cpu_addresses.rtp_tr_er.uc_cons_tr[index].temp_buff_pa);
 	}
 
 	IPADBG("freed uc pipes er and tr memory\n");