fw-api: Add HW header files for QCA6750
Add the HW header files for QCA6750 CRs-fixed: 2600285 Change-Id: I6a4f68765970cfbd8630a7c5f6173e2c034c5a81
This commit is contained in:
Alok Kumar
357
hw/qca6750/v1/reo_flush_queue.h
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357
hw/qca6750/v1/reo_flush_queue.h
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/*
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* Copyright (c) 2020 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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//
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// DO NOT EDIT! This file is automatically generated
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// These definitions are tied to a particular hardware layout
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#ifndef _REO_FLUSH_QUEUE_H_
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#define _REO_FLUSH_QUEUE_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#include "uniform_reo_cmd_header.h"
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// ################ START SUMMARY #################
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//
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// Dword Fields
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// 0 struct uniform_reo_cmd_header cmd_header;
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// 1 flush_desc_addr_31_0[31:0]
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// 2 flush_desc_addr_39_32[7:0], block_desc_addr_usage_after_flush[8], block_resource_index[10:9], invalidate_queue_and_flush[11], reserved_2a[31:12]
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// 3 reserved_3a[31:0]
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// 4 reserved_4a[31:0]
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// 5 reserved_5a[31:0]
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// 6 reserved_6a[31:0]
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// 7 reserved_7a[31:0]
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// 8 reserved_8a[31:0]
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//
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// ################ END SUMMARY #################
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#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9
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struct reo_flush_queue {
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struct uniform_reo_cmd_header cmd_header;
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uint32_t flush_desc_addr_31_0 : 32; //[31:0]
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uint32_t flush_desc_addr_39_32 : 8, //[7:0]
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block_desc_addr_usage_after_flush: 1, //[8]
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block_resource_index : 2, //[10:9]
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invalidate_queue_and_flush : 1, //[11]
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reserved_2a : 20; //[31:12]
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uint32_t reserved_3a : 32; //[31:0]
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uint32_t reserved_4a : 32; //[31:0]
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uint32_t reserved_5a : 32; //[31:0]
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uint32_t reserved_6a : 32; //[31:0]
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uint32_t reserved_7a : 32; //[31:0]
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uint32_t reserved_8a : 32; //[31:0]
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};
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/*
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struct uniform_reo_cmd_header cmd_header
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Consumer: REO
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Producer: SW
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Details for command execution tracking purposes.
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flush_desc_addr_31_0
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Consumer: REO
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Producer: SW
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Address (lower 32 bits) of the descriptor to flush
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<legal all>
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flush_desc_addr_39_32
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Consumer: REO
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Producer: SW
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Address (upper 8 bits) of the descriptor to flush
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<legal all>
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block_desc_addr_usage_after_flush
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When set, REO shall not re-fetch this address till SW
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explicitly unblocked this address
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If the blocking resource was already used, this command
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shall fail and an error is reported
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<legal all>
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block_resource_index
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Field only valid when 'Block_desc_addr_usage_after_flush
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' is set.
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Indicates which of the four blocking resources in REO
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will be assigned for managing the blocking of this address.
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<legal all>
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invalidate_queue_and_flush
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When set, after the queue has been completely flushed,
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invalidate the queue by clearing VLD and flush the queue
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descriptor from the cache.
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<legal all>
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reserved_2a
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<legal 0>
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reserved_3a
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<legal 0>
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reserved_4a
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<legal 0>
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reserved_5a
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<legal 0>
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reserved_6a
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<legal 0>
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reserved_7a
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<legal 0>
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reserved_8a
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<legal 0>
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*/
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/* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */
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/* Description REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER
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Consumer: REO/SW/DEBUG
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Producer: SW
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This number can be used by SW to track, identify and
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link the created commands with the command statusses
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<legal all>
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*/
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#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000
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#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0
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#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff
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/* Description REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED
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Consumer: REO
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Producer: SW
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<enum 0 NoStatus> REO does not need to generate a status
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TLV for the execution of this command
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<enum 1 StatusRequired> REO shall generate a status TLV
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for the execution of this command
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<legal all>
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*/
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#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000
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#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16
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#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000
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/* Description REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A
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<legal 0>
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*/
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#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000
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#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_LSB 17
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#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000
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/* Description REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0
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Consumer: REO
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Producer: SW
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Address (lower 32 bits) of the descriptor to flush
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<legal all>
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*/
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#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_OFFSET 0x00000004
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#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_LSB 0
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#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff
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/* Description REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32
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Consumer: REO
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Producer: SW
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Address (upper 8 bits) of the descriptor to flush
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<legal all>
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*/
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#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_OFFSET 0x00000008
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#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_LSB 0
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#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_MASK 0x000000ff
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/* Description REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH
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When set, REO shall not re-fetch this address till SW
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explicitly unblocked this address
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If the blocking resource was already used, this command
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shall fail and an error is reported
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<legal all>
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*/
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#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x00000008
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#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8
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#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x00000100
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/* Description REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX
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Field only valid when 'Block_desc_addr_usage_after_flush
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' is set.
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Indicates which of the four blocking resources in REO
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will be assigned for managing the blocking of this address.
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<legal all>
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*/
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#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008
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#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_LSB 9
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#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_MASK 0x00000600
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/* Description REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH
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When set, after the queue has been completely flushed,
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invalidate the queue by clearing VLD and flush the queue
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descriptor from the cache.
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<legal all>
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*/
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#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_OFFSET 0x00000008
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#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_LSB 11
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#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_MASK 0x00000800
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/* Description REO_FLUSH_QUEUE_2_RESERVED_2A
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<legal 0>
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*/
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#define REO_FLUSH_QUEUE_2_RESERVED_2A_OFFSET 0x00000008
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#define REO_FLUSH_QUEUE_2_RESERVED_2A_LSB 12
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#define REO_FLUSH_QUEUE_2_RESERVED_2A_MASK 0xfffff000
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/* Description REO_FLUSH_QUEUE_3_RESERVED_3A
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<legal 0>
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*/
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#define REO_FLUSH_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c
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#define REO_FLUSH_QUEUE_3_RESERVED_3A_LSB 0
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#define REO_FLUSH_QUEUE_3_RESERVED_3A_MASK 0xffffffff
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/* Description REO_FLUSH_QUEUE_4_RESERVED_4A
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<legal 0>
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*/
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#define REO_FLUSH_QUEUE_4_RESERVED_4A_OFFSET 0x00000010
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#define REO_FLUSH_QUEUE_4_RESERVED_4A_LSB 0
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#define REO_FLUSH_QUEUE_4_RESERVED_4A_MASK 0xffffffff
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/* Description REO_FLUSH_QUEUE_5_RESERVED_5A
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<legal 0>
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*/
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#define REO_FLUSH_QUEUE_5_RESERVED_5A_OFFSET 0x00000014
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#define REO_FLUSH_QUEUE_5_RESERVED_5A_LSB 0
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#define REO_FLUSH_QUEUE_5_RESERVED_5A_MASK 0xffffffff
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/* Description REO_FLUSH_QUEUE_6_RESERVED_6A
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<legal 0>
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*/
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#define REO_FLUSH_QUEUE_6_RESERVED_6A_OFFSET 0x00000018
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#define REO_FLUSH_QUEUE_6_RESERVED_6A_LSB 0
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#define REO_FLUSH_QUEUE_6_RESERVED_6A_MASK 0xffffffff
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/* Description REO_FLUSH_QUEUE_7_RESERVED_7A
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<legal 0>
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*/
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#define REO_FLUSH_QUEUE_7_RESERVED_7A_OFFSET 0x0000001c
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#define REO_FLUSH_QUEUE_7_RESERVED_7A_LSB 0
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#define REO_FLUSH_QUEUE_7_RESERVED_7A_MASK 0xffffffff
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/* Description REO_FLUSH_QUEUE_8_RESERVED_8A
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<legal 0>
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*/
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#define REO_FLUSH_QUEUE_8_RESERVED_8A_OFFSET 0x00000020
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#define REO_FLUSH_QUEUE_8_RESERVED_8A_LSB 0
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#define REO_FLUSH_QUEUE_8_RESERVED_8A_MASK 0xffffffff
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#endif // _REO_FLUSH_QUEUE_H_
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