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disp: msm: dsi: cphy constant fps porch calculation

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This change adds porch calculation support to maintain
constant fps during clock switch for CPhy.

Change-Id: I74b2f0e064441fba7f452b06438ece7fe3b373eb
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Harigovindan P <harigovi@codeaurora.org>
This commit is contained in:
Harigovindan P
2020-06-05 18:41:46 +05:30
committed by Steve Cohen
parent 662ac3ab89
commit 4a86b80a50
1 changed files with 15 additions and 4 deletions
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19
msm/dsi/dsi_display.c
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@@ -6447,12 +6447,15 @@ int dsi_display_get_mode_count(struct dsi_display *display,
return 0;
}
void dsi_display_adjust_mode_timing(
struct dsi_dyn_clk_caps *dyn_clk_caps,
void dsi_display_adjust_mode_timing(struct dsi_display *display,
struct dsi_display_mode *dsi_mode,
int lanes, int bpp)
{
u64 new_htotal, new_vtotal, htotal, vtotal, old_htotal, div;
struct dsi_dyn_clk_caps *dyn_clk_caps;
u32 bits_per_symbol = 16, num_of_symbols = 7; /* For Cphy */
dyn_clk_caps = &(display->panel->dyn_clk_caps);
/* Constant FPS is not supported on command mode */
if (dsi_mode->panel_mode == DSI_OP_CMD_MODE)
@@ -6473,6 +6476,10 @@ void dsi_display_adjust_mode_timing(
old_htotal = dsi_h_total_dce(&dsi_mode->timing);
new_htotal = dsi_mode->timing.clk_rate_hz * lanes;
div = bpp * vtotal * dsi_mode->timing.refresh_rate;
if (dsi_display_is_type_cphy(display)) {
new_htotal = new_htotal * bits_per_symbol;
div = div * num_of_symbols;
}
do_div(new_htotal, div);
if (old_htotal > new_htotal)
dsi_mode->timing.h_front_porch -=
@@ -6486,6 +6493,10 @@ void dsi_display_adjust_mode_timing(
htotal = dsi_h_total_dce(&dsi_mode->timing);
new_vtotal = dsi_mode->timing.clk_rate_hz * lanes;
div = bpp * htotal * dsi_mode->timing.refresh_rate;
if (dsi_display_is_type_cphy(display)) {
new_vtotal = new_vtotal * bits_per_symbol;
div = div * num_of_symbols;
}
do_div(new_vtotal, div);
dsi_mode->timing.v_front_porch = new_vtotal -
dsi_mode->timing.v_back_porch -
@@ -6540,7 +6551,7 @@ static void _dsi_display_populate_bit_clks(struct dsi_display *display,
*/
src->timing.clk_rate_hz = dyn_clk_caps->bit_clk_list[0];
dsi_display_adjust_mode_timing(dyn_clk_caps, src, lanes, bpp);
dsi_display_adjust_mode_timing(display, src, lanes, bpp);
src->pixel_clk_khz =
div_u64(src->timing.clk_rate_hz * lanes, bpp);
@@ -6569,7 +6580,7 @@ static void _dsi_display_populate_bit_clks(struct dsi_display *display,
dst->timing.clk_rate_hz = dyn_clk_caps->bit_clk_list[i];
dsi_display_adjust_mode_timing(dyn_clk_caps, dst, lanes,
dsi_display_adjust_mode_timing(display, dst, lanes,
bpp);
dst->pixel_clk_khz =