Merge "asoc: lpass-cdc: Support up to 200 coefficients for HiFi FIR"
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Gerrit - the friendly Code Review server
commit
48f26271e5
@@ -54,6 +54,13 @@
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#define LPASS_CDC_RX_MACRO_INTERP_MUX_NUM_INPUTS 3
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#define LPASS_CDC_RX_MACRO_SIDETONE_IIR_COEFF_MAX 5
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#define LPASS_CDC_RX_MACRO_FIR_COEFF_MAX 100
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#define LPASS_CDC_RX_MACRO_FIR_COEFF_ARRAY_MAX \
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(LPASS_CDC_RX_MACRO_FIR_COEFF_MAX + 1)
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/* first value represent number of coefficients in each 100 integer group */
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#define LPASS_CDC_RX_MACRO_FIR_FILTER_BYTES \
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(sizeof(u32) * LPASS_CDC_RX_MACRO_FIR_COEFF_ARRAY_MAX)
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#define STRING(name) #name
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#define LPASS_CDC_RX_MACRO_DAPM_ENUM(name, reg, offset, text) \
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@@ -360,6 +367,37 @@ struct lpass_cdc_rx_macro_iir_filter_ctl {
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} \
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}
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/* Codec supports 2 FIR filters Path */
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enum {
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RX0_PATH = 0,
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RX1_PATH,
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FIR_PATH_MAX,
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};
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/* Each RX Path has 2 group of coefficients */
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enum {
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GRP0 = 0,
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GRP1,
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GRP_MAX,
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};
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struct lpass_cdc_rx_macro_fir_filter_ctl {
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unsigned int path_idx;
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unsigned int grp_idx;
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struct soc_bytes_ext bytes_ext;
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};
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#define LPASS_CDC_RX_MACRO_FIR_FILTER_CTL(xname, pidx, gidx) \
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{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
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.info = lpass_cdc_rx_macro_fir_filter_info, \
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.get = lpass_cdc_rx_macro_fir_audio_mixer_get, \
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.put = lpass_cdc_rx_macro_fir_audio_mixer_put, \
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.private_value = (unsigned long)&(struct lpass_cdc_rx_macro_fir_filter_ctl) { \
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.path_idx = pidx, \
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.grp_idx = gidx, \
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.bytes_ext = {.max = LPASS_CDC_RX_MACRO_FIR_FILTER_BYTES, }, \
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} \
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}
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struct lpass_cdc_rx_macro_idle_detect_config {
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u8 hph_idle_thr;
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@@ -457,8 +495,12 @@ struct lpass_cdc_rx_macro_priv {
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bool reset_swr;
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int clsh_users;
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int rx_mclk_cnt;
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u8 fir_total_coeff_num[FIR_PATH_MAX];
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bool is_native_on;
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bool is_ear_mode_on;
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bool is_fir_filter_on;
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bool is_fir_coeff_written[FIR_PATH_MAX][GRP_MAX];
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bool is_fir_capable;
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bool dev_up;
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bool hph_pwr_mode;
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bool hph_hd2_mode;
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@@ -477,7 +519,10 @@ struct lpass_cdc_rx_macro_priv {
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struct lpass_cdc_rx_macro_idle_detect_config idle_det_cfg;
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u8 sidetone_coeff_array[IIR_MAX][BAND_MAX]
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[LPASS_CDC_RX_MACRO_SIDETONE_IIR_COEFF_MAX * 4];
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/* NOT designed to always reflect the actual hardware value */
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u32 fir_coeff_array[FIR_PATH_MAX][GRP_MAX]
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[LPASS_CDC_RX_MACRO_FIR_COEFF_MAX];
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u32 num_fir_coeff[FIR_PATH_MAX][GRP_MAX];
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struct platform_device *pdev_child_devices
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[LPASS_CDC_RX_MACRO_CHILD_DEVICES_MAX];
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int child_count;
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@@ -486,6 +531,7 @@ struct lpass_cdc_rx_macro_priv {
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int softclip_clk_users;
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u16 clk_id;
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u16 default_clk_id;
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struct clk *hifi_fir_clk;
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int8_t rx0_gain_val;
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int8_t rx1_gain_val;
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};
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@@ -559,6 +605,10 @@ static const char * const lpass_cdc_rx_macro_vbat_bcl_gsm_mode_text[] = {"OFF",
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static const struct soc_enum lpass_cdc_rx_macro_vbat_bcl_gsm_mode_enum =
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SOC_ENUM_SINGLE_EXT(2, lpass_cdc_rx_macro_vbat_bcl_gsm_mode_text);
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static const char *const lpass_cdc_rx_macro_fir_filter_text[] = {"OFF", "ON"};
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static const struct soc_enum lpass_cdc_rx_macro_fir_filter_enum =
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SOC_ENUM_SINGLE_EXT(2, lpass_cdc_rx_macro_fir_filter_text);
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static const struct snd_kcontrol_new rx_int2_1_vbat_mix_switch[] = {
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SOC_DAPM_SINGLE("RX AUX VBAT Enable", SND_SOC_NOPM, 0, 1, 0)
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};
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@@ -3123,6 +3173,504 @@ static int lpass_cdc_rx_macro_set_iir_gain(struct snd_soc_dapm_widget *w,
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return 0;
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}
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static int lpass_cdc_rx_macro_fir_filter_enable_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component =
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snd_soc_kcontrol_component(kcontrol);
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struct device *rx_dev = NULL;
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struct lpass_cdc_rx_macro_priv *rx_priv = NULL;
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if (!component) {
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pr_err("%s: component is NULL\n", __func__);
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return -EINVAL;
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}
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if (!lpass_cdc_rx_macro_get_data(component, &rx_dev, &rx_priv, __func__))
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return -EINVAL;
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ucontrol->value.bytes.data[0] = (unsigned char)rx_priv->is_fir_filter_on;
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return 0;
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}
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static int lpass_cdc_rx_macro_fir_filter_enable_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component =
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snd_soc_kcontrol_component(kcontrol);
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struct device *rx_dev = NULL;
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struct lpass_cdc_rx_macro_priv *rx_priv = NULL;
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int ret = 0;
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if (!component) {
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pr_err("%s: component is NULL\n", __func__);
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return -EINVAL;
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}
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if (!lpass_cdc_rx_macro_get_data(component, &rx_dev, &rx_priv, __func__))
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return -EINVAL;
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if (!rx_priv->hifi_fir_clk) {
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dev_dbg(rx_priv->dev, "%s: Undefined HIFI FIR Clock.\n",
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__func__);
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return 0;
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}
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if (!rx_priv->is_fir_capable) {
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dev_dbg(rx_priv->dev, "%s: HIFI FIR is not supported.\n",
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__func__);
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return 0;
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}
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rx_priv->is_fir_filter_on =
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(!ucontrol->value.bytes.data[0] ? false : true);
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dev_dbg(rx_priv->dev, "%s:is_fir_filter_on=%d\n",
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__func__, rx_priv->is_fir_filter_on);
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if (rx_priv->is_fir_filter_on) {
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ret = clk_prepare_enable(rx_priv->hifi_fir_clk);
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if (ret < 0) {
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dev_err_ratelimited(rx_priv->dev, "%s:hifi_fir_clk enable failed\n",
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__func__);
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return ret;
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}
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/* Enable HIFI_FEAT_EN bit */
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snd_soc_component_update_bits(component, LPASS_CDC_RX_TOP_TOP_CFG1, 0x01, 0x01);
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/* Enable FIR_CLK_EN */
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snd_soc_component_update_bits(component, LPASS_CDC_RX_RX0_RX_PATH_CTL, 0x80, 0x80);
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snd_soc_component_update_bits(component, LPASS_CDC_RX_RX1_RX_PATH_CTL, 0x80, 0x80);
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/* Start the FIR filter */
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snd_soc_component_update_bits(component, LPASS_CDC_RX_RX0_RX_FIR_CTL, 0x0D, 0x05);
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snd_soc_component_update_bits(component, LPASS_CDC_RX_RX1_RX_FIR_CTL, 0x0D, 0x05);
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} else {
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/* Stop the FIR filter */
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snd_soc_component_update_bits(component, LPASS_CDC_RX_RX0_RX_FIR_CTL, 0x0D, 0x00);
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snd_soc_component_update_bits(component, LPASS_CDC_RX_RX1_RX_FIR_CTL, 0x0D, 0x00);
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/* Disable FIR_CLK_EN */
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snd_soc_component_update_bits(component, LPASS_CDC_RX_RX0_RX_PATH_CTL, 0x80, 0x00);
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snd_soc_component_update_bits(component, LPASS_CDC_RX_RX1_RX_PATH_CTL, 0x80, 0x00);
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/* Disable HIFI_FEAT_EN bit */
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snd_soc_component_update_bits(component, LPASS_CDC_RX_TOP_TOP_CFG1, 0x01, 0x00);
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clk_disable_unprepare(rx_priv->hifi_fir_clk);
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}
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return 0;
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}
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static int lpass_cdc_rx_macro_fir_filter_info(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_info *ucontrol)
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{
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struct lpass_cdc_rx_macro_fir_filter_ctl *ctl =
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(struct lpass_cdc_rx_macro_fir_filter_ctl *)kcontrol->private_value;
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struct soc_bytes_ext *params = &ctl->bytes_ext;
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ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
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ucontrol->count = params->max;
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return 0;
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}
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static int lpass_cdc_rx_macro_fir_audio_mixer_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *ucontrol)
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{
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struct snd_soc_component *component =
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snd_soc_kcontrol_component(kcontrol);
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struct lpass_cdc_rx_macro_fir_filter_ctl *ctl =
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(struct lpass_cdc_rx_macro_fir_filter_ctl *)kcontrol->private_value;
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unsigned int path_idx = ctl->path_idx;
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unsigned int grp_idx = ctl->grp_idx;
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u32 num_coeff_grp = 0;
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u32 readArray[LPASS_CDC_RX_MACRO_FIR_COEFF_ARRAY_MAX];
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unsigned int coeff_idx = 0, array_idx = 0;
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unsigned int copy_size;
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struct device *rx_dev = NULL;
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struct lpass_cdc_rx_macro_priv *rx_priv = NULL;
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if (!component) {
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pr_err("%s: component is NULL\n", __func__);
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return -EINVAL;
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}
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if (!lpass_cdc_rx_macro_get_data(component, &rx_dev, &rx_priv, __func__))
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return -EINVAL;
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if (path_idx >= FIR_PATH_MAX) {
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dev_err(rx_priv->dev, "%s: path_idx:%d is invalid\n", __func__, path_idx);
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return -EINVAL;
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}
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if (grp_idx >= GRP_MAX) {
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dev_err(rx_priv->dev, "%s: grp_idx:%d is invalid\n", __func__, grp_idx);
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return -EINVAL;
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}
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num_coeff_grp = rx_priv->num_fir_coeff[path_idx][grp_idx];
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readArray[array_idx++] = num_coeff_grp;
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for (coeff_idx = 0; coeff_idx < num_coeff_grp; coeff_idx++) {
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readArray[array_idx++] =
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rx_priv->fir_coeff_array[path_idx][grp_idx][coeff_idx];
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}
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copy_size = array_idx;
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memcpy(ucontrol->value.bytes.data, &readArray[0], sizeof(readArray[0]) * copy_size);
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return 0;
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}
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static int set_fir_filter_coeff(struct snd_soc_component *component,
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struct lpass_cdc_rx_macro_priv *rx_priv,
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unsigned int path_idx)
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{
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int grp_idx = 0, coeff_idx = 0;
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unsigned int ret = 0;
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unsigned int max_coeff_num, num_coeff_grp;
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unsigned int path_ctl_addr = 0, wdata0_addr = 0, coeff_addr = 0;
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unsigned int fir_ctl_addr = 0;
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bool all_coeff_written = true;
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switch (path_idx) {
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case RX0_PATH:
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path_ctl_addr = LPASS_CDC_RX_RX0_RX_PATH_CTL;
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wdata0_addr = LPASS_CDC_RX_RX0_RX_FIR_COEFF_WDATA0;
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coeff_addr = LPASS_CDC_RX_RX0_RX_FIR_COEFF_ADDR;
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fir_ctl_addr = LPASS_CDC_RX_RX0_RX_FIR_CTL;
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break;
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case RX1_PATH:
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path_ctl_addr = LPASS_CDC_RX_RX1_RX_PATH_CTL;
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wdata0_addr = LPASS_CDC_RX_RX1_RX_FIR_COEFF_WDATA0;
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coeff_addr = LPASS_CDC_RX_RX1_RX_FIR_COEFF_ADDR;
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fir_ctl_addr = LPASS_CDC_RX_RX1_RX_FIR_CTL;
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break;
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default:
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dev_err(rx_priv->dev,
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"%s: inavlid FIR ID: %d\n", __func__, path_idx);
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ret = -EINVAL;
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goto exit;
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}
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max_coeff_num = LPASS_CDC_RX_MACRO_FIR_COEFF_MAX;
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for (grp_idx = 0; grp_idx < GRP_MAX; grp_idx++)
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all_coeff_written = all_coeff_written &&
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rx_priv->is_fir_coeff_written[path_idx][grp_idx];
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if (all_coeff_written)
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goto exit;
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ret = lpass_cdc_rx_macro_mclk_enable(rx_priv, 1, false);
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if (ret < 0) {
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dev_err_ratelimited(rx_priv->dev, "%s:rx_macro_mclk enable failed\n",
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__func__);
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goto exit;
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}
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ret = clk_prepare_enable(rx_priv->hifi_fir_clk);
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if (ret < 0) {
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dev_err_ratelimited(rx_priv->dev, "%s:hifi_fir_clk enable failed\n",
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__func__);
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goto disable_mclk_block;
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}
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/* Enable HIFI_FEAT_EN bit */
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snd_soc_component_update_bits(component, LPASS_CDC_RX_TOP_TOP_CFG1, 0x01, 0x01);
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/* Enable FIR_CLK_EN, datapath reset */
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snd_soc_component_update_bits(component, path_ctl_addr, 0xC0, 0xC0);
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/* Enable FIR_CLK_EN, Release Reset */
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snd_soc_component_update_bits(component, path_ctl_addr, 0xC0, 0x80);
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/* wait for data ram initialization after enabling clock */
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usleep_range(10, 11);
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for (grp_idx = 0; grp_idx < GRP_MAX; grp_idx++) {
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unsigned int coeff_idx_start = 0, array_idx = 0;
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/* Skip if this group is written and no futher update */
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if (rx_priv->is_fir_coeff_written[path_idx][grp_idx])
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continue;
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num_coeff_grp = rx_priv->num_fir_coeff[path_idx][grp_idx];
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if (num_coeff_grp > max_coeff_num) {
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dev_err(rx_priv->dev,
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"%s: inavlid number of RX_FIR coefficients:%d"
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" in path:%d, group:%d\n",
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__func__, num_coeff_grp, path_idx, grp_idx);
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ret = -EINVAL;
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goto disable_FIR;
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}
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coeff_idx_start = grp_idx * max_coeff_num;
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for (coeff_idx = coeff_idx_start;
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coeff_idx < coeff_idx_start + num_coeff_grp / 2 * 2;
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coeff_idx += 2) {
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unsigned int addr_offset = coeff_idx / 2;
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/* First coefficient in pair */
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u32 value = rx_priv->fir_coeff_array[path_idx][grp_idx][array_idx++];
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dev_dbg(rx_priv->dev, "%s: val of coeff_idx:%d, COEFF:0x%x\n",
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__func__, coeff_idx, value);
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snd_soc_component_write(component, wdata0_addr,
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value & 0xFF);
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snd_soc_component_write(component, wdata0_addr + 0x4,
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(value >> 8) & 0xFF);
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snd_soc_component_write(component, wdata0_addr + 0x8,
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(value >> 16) & 0xFF);
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snd_soc_component_write(component, wdata0_addr + 0xC,
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(value >> 24) & 0xFF);
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/* Second coefficient in pair */
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value = rx_priv->fir_coeff_array[path_idx][grp_idx][array_idx++];
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dev_dbg(rx_priv->dev, "%s: val of coeff_idx:%d, COEFF:0x%x\n",
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__func__, coeff_idx, value);
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snd_soc_component_write(component, wdata0_addr + 0x10,
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value & 0xFF);
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snd_soc_component_write(component, wdata0_addr + 0x14,
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(value >> 8) & 0xFF);
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snd_soc_component_write(component, wdata0_addr + 0x18,
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(value >> 16) & 0xFF);
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snd_soc_component_write(component, wdata0_addr + 0x1C,
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(value >> 24) & 0xFF);
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snd_soc_component_write(component, coeff_addr, addr_offset);
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snd_soc_component_update_bits(component, fir_ctl_addr, 0x02, 0x02);
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usleep_range(13, 15);
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snd_soc_component_update_bits(component, fir_ctl_addr, 0x02, 0x00);
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}
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/* odd number of coefficients in this group, handle last one */
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if (num_coeff_grp % 2 != 0) {
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int addr_offset = coeff_idx / 2;
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/* First coefficient in pair */
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u32 value = rx_priv->fir_coeff_array[path_idx][grp_idx][array_idx++];
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dev_dbg(rx_priv->dev, "%s: val of coeff_idx:%d, COEFF:0x%x\n",
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__func__, coeff_idx, value);
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snd_soc_component_write(component, wdata0_addr,
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value & 0xFF);
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snd_soc_component_write(component, wdata0_addr + 0x4,
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(value >> 8) & 0xFF);
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snd_soc_component_write(component, wdata0_addr + 0x8,
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(value >> 16) & 0xFF);
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snd_soc_component_write(component, wdata0_addr + 0xC,
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(value >> 24) & 0xFF);
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/* Second coefficient in pair */
|
||||
dev_dbg(rx_priv->dev, "%s: val of coeff_idx:%d, COEFF:0x%x\n",
|
||||
__func__, coeff_idx, 0x0);
|
||||
snd_soc_component_write(component, wdata0_addr + 0x10, 0x0);
|
||||
snd_soc_component_write(component, wdata0_addr + 0x14, 0x0);
|
||||
snd_soc_component_write(component, wdata0_addr + 0x18, 0x0);
|
||||
snd_soc_component_write(component, wdata0_addr + 0x1C, 0x0);
|
||||
|
||||
snd_soc_component_write(component, coeff_addr, addr_offset);
|
||||
snd_soc_component_update_bits(component, fir_ctl_addr, 0x02, 0x02);
|
||||
usleep_range(13, 15);
|
||||
snd_soc_component_update_bits(component, fir_ctl_addr, 0x02, 0x00);
|
||||
}
|
||||
|
||||
rx_priv->is_fir_coeff_written[path_idx][grp_idx] = true;
|
||||
dev_dbg(component->dev, "%s: HIFI FIR Path:%d Group:%d coefficients"
|
||||
" updated.\n",
|
||||
__func__, path_idx, grp_idx);
|
||||
}
|
||||
|
||||
disable_FIR:
|
||||
/* disable FIR_CLK_EN */
|
||||
snd_soc_component_update_bits(component, path_ctl_addr, 0x80, 0x00);
|
||||
|
||||
/* Disable HIFI_FEAT_EN bit */
|
||||
snd_soc_component_update_bits(component, LPASS_CDC_RX_TOP_TOP_CFG1, 0x01, 0x00);
|
||||
|
||||
clk_disable_unprepare(rx_priv->hifi_fir_clk);
|
||||
|
||||
disable_mclk_block:
|
||||
ret = lpass_cdc_rx_macro_mclk_enable(rx_priv, 0, false);
|
||||
|
||||
exit:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int lpass_cdc_rx_macro_fir_audio_mixer_put(struct snd_kcontrol *kcontrol,
|
||||
struct snd_ctl_elem_value *ucontrol)
|
||||
{
|
||||
struct snd_soc_component *component =
|
||||
snd_soc_kcontrol_component(kcontrol);
|
||||
struct lpass_cdc_rx_macro_fir_filter_ctl *ctl =
|
||||
(struct lpass_cdc_rx_macro_fir_filter_ctl *)kcontrol->private_value;
|
||||
unsigned int path_idx = ctl->path_idx;
|
||||
unsigned int grp_idx = ctl->grp_idx;
|
||||
u32 ele_size = 0, num_coeff_grp = 0;
|
||||
u32 coeff[LPASS_CDC_RX_MACRO_FIR_COEFF_ARRAY_MAX];
|
||||
|
||||
int ret = 0;
|
||||
unsigned int stored_total_num = 0;
|
||||
unsigned int grp_iidx = 0, coeff_idx = 0, array_idx = 0;
|
||||
struct device *rx_dev = NULL;
|
||||
struct lpass_cdc_rx_macro_priv *rx_priv = NULL;
|
||||
|
||||
if (!component) {
|
||||
pr_err("%s: component is NULL\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!lpass_cdc_rx_macro_get_data(component, &rx_dev, &rx_priv, __func__))
|
||||
return -EINVAL;
|
||||
|
||||
if (path_idx >= FIR_PATH_MAX) {
|
||||
dev_err(rx_priv->dev,"%s: path_idx:%d is invalid\n", __func__, path_idx);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (grp_idx >= GRP_MAX) {
|
||||
dev_err(rx_priv->dev,"%s: grp_idx:%d is invalid\n", __func__, grp_idx);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!rx_priv->hifi_fir_clk) {
|
||||
dev_dbg(rx_priv->dev, "%s: Undefined HIFI FIR Clock.\n",
|
||||
__func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (!rx_priv->is_fir_capable) {
|
||||
dev_dbg(rx_priv->dev, "%s: HIFI FIR is not supported.\n",
|
||||
__func__);
|
||||
return 0;
|
||||
}
|
||||
|
||||
ele_size = sizeof(coeff[0]);
|
||||
memcpy(&coeff[0], ucontrol->value.bytes.data, ele_size);
|
||||
num_coeff_grp = coeff[0];
|
||||
|
||||
dev_dbg(rx_priv->dev, "%s: bytes.data: path:%d, grp:%d, num_coeff_grp:%d\n",
|
||||
__func__, path_idx, grp_idx, num_coeff_grp);
|
||||
|
||||
if (num_coeff_grp > LPASS_CDC_RX_MACRO_FIR_COEFF_MAX) {
|
||||
dev_err(rx_priv->dev,
|
||||
"%s: inavlid number of RX_FIR coefficients:%d in path:%d, group:%d\n",
|
||||
__func__, num_coeff_grp, path_idx, grp_idx);
|
||||
rx_priv->num_fir_coeff[path_idx][grp_idx] = 0;
|
||||
return -EINVAL;
|
||||
} else {
|
||||
rx_priv->num_fir_coeff[path_idx][grp_idx] = num_coeff_grp;
|
||||
}
|
||||
|
||||
memcpy(&coeff[1], &(ucontrol->value.bytes.data[ele_size]), ele_size * num_coeff_grp);
|
||||
|
||||
/* Store the coefficients in FIR coeff array */
|
||||
array_idx = 1;
|
||||
for (coeff_idx = 0; coeff_idx < num_coeff_grp; coeff_idx++)
|
||||
rx_priv->fir_coeff_array[path_idx][grp_idx][coeff_idx] = coeff[array_idx++];
|
||||
|
||||
/* Clear the written flag so this group is ready to be written */
|
||||
rx_priv->is_fir_coeff_written[path_idx][grp_idx] = false;
|
||||
|
||||
stored_total_num = 0;
|
||||
for (grp_iidx = 0; grp_iidx < GRP_MAX; grp_iidx++) {
|
||||
stored_total_num += rx_priv->num_fir_coeff[path_idx][grp_iidx];
|
||||
}
|
||||
|
||||
/* Only write coeffs if total num matches, otherwise delay the write */
|
||||
if (rx_priv->fir_total_coeff_num[path_idx] == stored_total_num)
|
||||
ret = set_fir_filter_coeff(component, rx_priv, path_idx);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int lpass_cdc_rx_macro_fir_coeff_num_get(struct snd_kcontrol *kcontrol,
|
||||
struct snd_ctl_elem_value *ucontrol)
|
||||
{
|
||||
struct snd_soc_component *component =
|
||||
snd_soc_kcontrol_component(kcontrol);
|
||||
unsigned int path_idx = ((struct soc_multi_mixer_control *)
|
||||
kcontrol->private_value)->shift;
|
||||
struct device *rx_dev = NULL;
|
||||
struct lpass_cdc_rx_macro_priv *rx_priv = NULL;
|
||||
|
||||
if (!component) {
|
||||
pr_err("%s: component is NULL\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!lpass_cdc_rx_macro_get_data(component, &rx_dev, &rx_priv, __func__))
|
||||
return -EINVAL;
|
||||
|
||||
if (path_idx >= FIR_PATH_MAX) {
|
||||
dev_err(rx_priv->dev,"%s: path_idx:%d is invalid\n", __func__, path_idx);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ucontrol->value.bytes.data[0] = rx_priv->fir_total_coeff_num[path_idx];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lpass_cdc_rx_macro_fir_coeff_num_put(struct snd_kcontrol *kcontrol,
|
||||
struct snd_ctl_elem_value *ucontrol)
|
||||
{
|
||||
struct snd_soc_component *component =
|
||||
snd_soc_kcontrol_component(kcontrol);
|
||||
unsigned int path_idx = ((struct soc_multi_mixer_control *)
|
||||
kcontrol->private_value)->shift;
|
||||
u8 fir_total_coeff_num = ucontrol->value.bytes.data[0];
|
||||
struct device *rx_dev = NULL;
|
||||
struct lpass_cdc_rx_macro_priv *rx_priv = NULL;
|
||||
unsigned int ret = 0;
|
||||
unsigned int grp_idx, stored_total_num, num_coeff_addr;
|
||||
|
||||
if (!component) {
|
||||
pr_err("%s: component is NULL\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!lpass_cdc_rx_macro_get_data(component, &rx_dev, &rx_priv, __func__))
|
||||
return -EINVAL;
|
||||
|
||||
switch (path_idx) {
|
||||
case RX0_PATH:
|
||||
num_coeff_addr = LPASS_CDC_RX_RX0_RX_FIR_CFG;
|
||||
break;
|
||||
case RX1_PATH:
|
||||
num_coeff_addr = LPASS_CDC_RX_RX1_RX_FIR_CFG;
|
||||
break;
|
||||
default:
|
||||
dev_err(rx_priv->dev,
|
||||
"%s: inavlid FIR ID: %d\n", __func__, path_idx);
|
||||
ret = -EINVAL;
|
||||
goto exit;
|
||||
}
|
||||
|
||||
if (fir_total_coeff_num > LPASS_CDC_RX_MACRO_FIR_COEFF_MAX * GRP_MAX) {
|
||||
dev_err(rx_priv->dev,
|
||||
"%s: inavlid total number of RX_FIR coefficients:%d"
|
||||
" in path:%d\n",
|
||||
__func__, fir_total_coeff_num, path_idx);
|
||||
rx_priv->fir_total_coeff_num[path_idx] = 0;
|
||||
return -EINVAL;
|
||||
} else {
|
||||
rx_priv->fir_total_coeff_num[path_idx] = fir_total_coeff_num;
|
||||
}
|
||||
|
||||
snd_soc_component_write(component, num_coeff_addr, fir_total_coeff_num);
|
||||
dev_dbg(component->dev, "%s: HIFI FIR Path:%d total coefficients"
|
||||
" number updated: %d.\n",
|
||||
__func__, path_idx, fir_total_coeff_num);
|
||||
|
||||
stored_total_num = 0;
|
||||
for (grp_idx = 0; grp_idx < GRP_MAX; grp_idx++)
|
||||
stored_total_num += rx_priv->num_fir_coeff[path_idx][grp_idx];
|
||||
|
||||
if (fir_total_coeff_num == stored_total_num)
|
||||
ret = set_fir_filter_coeff(component, rx_priv, path_idx);
|
||||
|
||||
exit:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct snd_kcontrol_new lpass_cdc_rx_macro_snd_controls[] = {
|
||||
SOC_SINGLE_S8_TLV("RX_RX0 Digital Volume",
|
||||
LPASS_CDC_RX_RX0_RX_VOL_CTL,
|
||||
@@ -3148,12 +3696,23 @@ static const struct snd_kcontrol_new lpass_cdc_rx_macro_snd_controls[] = {
|
||||
SOC_SINGLE_EXT("RX_COMP2 Switch", SND_SOC_NOPM, LPASS_CDC_RX_MACRO_COMP2, 1, 0,
|
||||
lpass_cdc_rx_macro_get_compander, lpass_cdc_rx_macro_set_compander),
|
||||
|
||||
SOC_SINGLE_EXT("RX0 FIR Coeff Num", SND_SOC_NOPM, RX0_PATH,
|
||||
(LPASS_CDC_RX_MACRO_FIR_COEFF_MAX * GRP_MAX), 0,
|
||||
lpass_cdc_rx_macro_fir_coeff_num_get, lpass_cdc_rx_macro_fir_coeff_num_put),
|
||||
|
||||
SOC_SINGLE_EXT("RX1 FIR Coeff Num", SND_SOC_NOPM, RX1_PATH,
|
||||
(LPASS_CDC_RX_MACRO_FIR_COEFF_MAX * GRP_MAX), 0,
|
||||
lpass_cdc_rx_macro_fir_coeff_num_get, lpass_cdc_rx_macro_fir_coeff_num_put),
|
||||
|
||||
SOC_ENUM_EXT("HPH Idle Detect", hph_idle_detect_enum,
|
||||
lpass_cdc_rx_macro_hph_idle_detect_get, lpass_cdc_rx_macro_hph_idle_detect_put),
|
||||
|
||||
SOC_ENUM_EXT("RX_EAR Mode", lpass_cdc_rx_macro_ear_mode_enum,
|
||||
lpass_cdc_rx_macro_get_ear_mode, lpass_cdc_rx_macro_put_ear_mode),
|
||||
|
||||
SOC_ENUM_EXT("RX_FIR Filter", lpass_cdc_rx_macro_fir_filter_enum,
|
||||
lpass_cdc_rx_macro_fir_filter_enable_get, lpass_cdc_rx_macro_fir_filter_enable_put),
|
||||
|
||||
SOC_ENUM_EXT("RX_HPH HD2 Mode", lpass_cdc_rx_macro_hph_hd2_mode_enum,
|
||||
lpass_cdc_rx_macro_get_hph_hd2_mode, lpass_cdc_rx_macro_put_hph_hd2_mode),
|
||||
|
||||
@@ -3236,6 +3795,11 @@ static const struct snd_kcontrol_new lpass_cdc_rx_macro_snd_controls[] = {
|
||||
LPASS_CDC_RX_MACRO_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
|
||||
LPASS_CDC_RX_MACRO_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
|
||||
LPASS_CDC_RX_MACRO_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
|
||||
|
||||
LPASS_CDC_RX_MACRO_FIR_FILTER_CTL("RX0 FIR Coeff Group0", RX0_PATH, GRP0),
|
||||
LPASS_CDC_RX_MACRO_FIR_FILTER_CTL("RX0 FIR Coeff Group1", RX0_PATH, GRP1),
|
||||
LPASS_CDC_RX_MACRO_FIR_FILTER_CTL("RX1 FIR Coeff Group0", RX1_PATH, GRP0),
|
||||
LPASS_CDC_RX_MACRO_FIR_FILTER_CTL("RX1 FIR Coeff Group1", RX1_PATH, GRP1),
|
||||
};
|
||||
|
||||
static int lpass_cdc_rx_macro_enable_echo(struct snd_soc_dapm_widget *w,
|
||||
@@ -3867,6 +4431,33 @@ exit:
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* lpass_cdc_rx_set_fir_capability - Set RX HIFI FIR Filter capability
|
||||
*
|
||||
* @component: Codec component ptr.
|
||||
* @capable: if the target have RX HIFI FIR available.
|
||||
*
|
||||
* Set RX HIFI FIR capability, stored the capability into RX macro private data.
|
||||
*/
|
||||
int lpass_cdc_rx_set_fir_capability(struct snd_soc_component *component, bool capable)
|
||||
{
|
||||
struct device *rx_dev = NULL;
|
||||
struct lpass_cdc_rx_macro_priv *rx_priv = NULL;
|
||||
|
||||
if (!component) {
|
||||
pr_err("%s: component is NULL\n", __func__);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!lpass_cdc_rx_macro_get_data(component, &rx_dev, &rx_priv, __func__))
|
||||
return -EINVAL;
|
||||
|
||||
rx_priv->is_fir_capable = capable;
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL(lpass_cdc_rx_set_fir_capability);
|
||||
|
||||
static const struct lpass_cdc_rx_macro_reg_mask_val
|
||||
lpass_cdc_rx_macro_reg_init[] = {
|
||||
{LPASS_CDC_RX_RX0_RX_PATH_SEC7, 0x07, 0x02},
|
||||
@@ -4091,6 +4682,7 @@ static int lpass_cdc_rx_macro_probe(struct platform_device *pdev)
|
||||
char __iomem *rx_io_base = NULL, *muxsel_io = NULL;
|
||||
int ret = 0;
|
||||
u32 default_clk_id = 0;
|
||||
struct clk *hifi_fir_clk = NULL;
|
||||
u32 is_used_rx_swr_gpio = 1;
|
||||
const char *is_used_rx_swr_gpio_dt = "qcom,is-used-swr-gpio";
|
||||
|
||||
@@ -4184,6 +4776,15 @@ static int lpass_cdc_rx_macro_probe(struct platform_device *pdev)
|
||||
ops.clk_id_req = rx_priv->clk_id;
|
||||
ops.default_clk_id = default_clk_id;
|
||||
|
||||
hifi_fir_clk = devm_clk_get(&pdev->dev, "rx_mclk2_2x_clk");
|
||||
if (IS_ERR(hifi_fir_clk)) {
|
||||
ret = PTR_ERR(hifi_fir_clk);
|
||||
dev_dbg(&pdev->dev, "%s: clk get %s failed %d\n",
|
||||
__func__, "rx_mclk2_2x_clk", ret);
|
||||
hifi_fir_clk = NULL;
|
||||
}
|
||||
rx_priv->hifi_fir_clk = hifi_fir_clk;
|
||||
|
||||
rx_priv->is_aux_hpf_on = 1;
|
||||
|
||||
dev_set_drvdata(&pdev->dev, rx_priv);
|
||||
|
||||
Reference in New Issue
Block a user