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@@ -4640,7 +4640,7 @@ static int dsi_display_dynamic_clk_configure_cmd(struct dsi_display *display,
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rc = dsi_display_update_dsi_bitrate(display, clk_rate);
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if (!rc) {
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- DSI_INFO("%s: bit clk is ready to be configured to '%d'\n",
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+ DSI_DEBUG("%s: bit clk is ready to be configured to '%d'\n",
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__func__, clk_rate);
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atomic_set(&display->clkrate_change_pending, 1);
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} else {
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@@ -5253,7 +5253,7 @@ static int dsi_display_force_update_dsi_clk(struct dsi_display *display)
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rc = dsi_display_link_clk_force_update_ctrl(display->dsi_clk_handle);
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if (!rc) {
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- DSI_INFO("dsi bit clk has been configured to %d\n",
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+ DSI_DEBUG("dsi bit clk has been configured to %d\n",
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display->cached_clk_rate);
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atomic_set(&display->clkrate_change_pending, 0);
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@@ -7141,11 +7141,11 @@ int dsi_display_set_mode(struct dsi_display *display,
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goto error;
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}
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- DSI_INFO("mdp_transfer_time_us=%d us\n",
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- adj_mode.priv_info->mdp_transfer_time_us);
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- DSI_INFO("hactive= %d,vactive= %d,fps=%d\n",
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- timing.h_active, timing.v_active,
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- timing.refresh_rate);
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+ DSI_INFO("mdp_transfer_time=%d, hactive=%d, vactive=%d, fps=%d\n",
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+ adj_mode.priv_info->mdp_transfer_time_us,
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+ timing.h_active, timing.v_active, timing.refresh_rate);
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+ SDE_EVT32(adj_mode.priv_info->mdp_transfer_time_us,
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+ timing.h_active, timing.v_active, timing.refresh_rate);
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memcpy(display->panel->cur_mode, &adj_mode, sizeof(adj_mode));
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error:
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