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drm: msm: add spr by pass support

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SPR hardware can be configured by user-space clients in bypass or
normal mode. Change adds support to allow clients to enable spr
in bypass or normal mode.

Change-Id: I04641774de91ec2b40af00c665ceffd72a255eea
Signed-off-by: Gopikrishnaiah Anand <quic_agopik@quicinc.com>
This commit is contained in:
Gopikrishnaiah Anand
2022-01-26 12:22:39 -08:00
committed by Gerrit - the friendly Code Review server
parent adc0d00ae9
commit 486bd6b7a1
2 changed files with 19 additions and 4 deletions
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1
include/uapi/display/drm/msm_drm_pp.h
View File

@@ -581,6 +581,7 @@ struct drm_msm_ltm_buffer {
#define SPR_INIT_PARAM_SIZE_3 16 #define SPR_INIT_PARAM_SIZE_3 16
#define SPR_INIT_PARAM_SIZE_4 24 #define SPR_INIT_PARAM_SIZE_4 24
#define SPR_INIT_PARAM_SIZE_5 32 #define SPR_INIT_PARAM_SIZE_5 32
#define SPR_FLAG_BYPASS (1 << 0)
/** /**
* struct drm_msm_spr_init_cfg - SPR initial configuration structure * struct drm_msm_spr_init_cfg - SPR initial configuration structure

22
msm/sde/sde_hw_reg_dma_v1_color_proc.c
View File

@@ -4958,6 +4958,7 @@ void reg_dmav1_setup_spr_init_cfgv1(struct sde_hw_dspp *ctx, void *cfg)
uint32_t reg_off, reg_cnt, base_off; uint32_t reg_off, reg_cnt, base_off;
uint32_t reg[16]; uint32_t reg[16];
int i, index, rc = 0; int i, index, rc = 0;
bool spr_bypass = false;
rc = reg_dma_dspp_check(ctx, cfg, SPR_INIT); rc = reg_dma_dspp_check(ctx, cfg, SPR_INIT);
if (rc) if (rc)
@@ -4988,6 +4989,8 @@ void reg_dmav1_setup_spr_init_cfgv1(struct sde_hw_dspp *ctx, void *cfg)
return; return;
} }
spr_bypass = (payload->flags & SPR_FLAG_BYPASS) ? true : false;
reg_cnt = 2; reg_cnt = 2;
reg_off = base_off + 0x04; reg_off = base_off + 0x04;
reg[0] = APPLY_MASK_AND_SHIFT(payload->cfg0, 1, 0) | reg[0] = APPLY_MASK_AND_SHIFT(payload->cfg0, 1, 0) |
@@ -5004,6 +5007,10 @@ void reg_dmav1_setup_spr_init_cfgv1(struct sde_hw_dspp *ctx, void *cfg)
reg[0] |= APPLY_MASK_AND_SHIFT(payload->cfg11[2], 2, 12); reg[0] |= APPLY_MASK_AND_SHIFT(payload->cfg11[2], 2, 12);
reg[0] |= APPLY_MASK_AND_SHIFT(payload->cfg11[3], 1, 14); reg[0] |= APPLY_MASK_AND_SHIFT(payload->cfg11[3], 1, 14);
if (spr_bypass)
reg[0] = APPLY_MASK_AND_SHIFT(payload->cfg1, 1, 1) |
APPLY_MASK_AND_SHIFT(payload->cfg2, 1, 2);
reg[1] = 0; reg[1] = 0;
if (hw_cfg->num_of_mixers == 2) if (hw_cfg->num_of_mixers == 2)
reg[1] = 1; reg[1] = 1;
@@ -5018,6 +5025,9 @@ void reg_dmav1_setup_spr_init_cfgv1(struct sde_hw_dspp *ctx, void *cfg)
return; return;
} }
if (spr_bypass)
goto bypass;
reg_cnt = 1; reg_cnt = 1;
reg_off = base_off + 0x54; reg_off = base_off + 0x54;
reg[0] = 0; reg[0] = 0;
@@ -5079,6 +5089,7 @@ void reg_dmav1_setup_spr_init_cfgv1(struct sde_hw_dspp *ctx, void *cfg)
if (rc) if (rc)
return; return;
bypass:
REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl, REG_DMA_SETUP_KICKOFF(kick_off, hw_cfg->ctl,
dspp_buf[SPR_INIT][ctx->idx], dspp_buf[SPR_INIT][ctx->idx],
REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE, REG_DMA_WRITE, DMA_CTL_QUEUE0, WRITE_IMMEDIATE,
@@ -5603,11 +5614,14 @@ static bool __reg_dmav1_valid_hfc_en_cfg(struct drm_msm_dem_cfg *dcfg,
if (dcfg->pentile) { if (dcfg->pentile) {
w = dcfg->c0_depth * (temp / 2) + dcfg->c1_depth * temp + w = dcfg->c0_depth * (temp / 2) + dcfg->c1_depth * temp +
dcfg->c2_depth * (temp / 2); dcfg->c2_depth * (temp / 2);
if (w % 32) } else {
w = 32 - (w % 32) + w; w = dcfg->c0_depth * temp + dcfg->c1_depth * temp + dcfg->c2_depth * temp;
w = 2 * (w / 32);
w = w / (hw_cfg->num_of_mixers ? hw_cfg->num_of_mixers : 1);
} }
if (w % 32)
w = 32 - (w % 32) + w;
w = 2 * (w / 32);
w = w / (hw_cfg->num_of_mixers ? hw_cfg->num_of_mixers : 1);
if (h != hw_cfg->skip_blend_plane_h || w != hw_cfg->skip_blend_plane_w) { if (h != hw_cfg->skip_blend_plane_h || w != hw_cfg->skip_blend_plane_w) {
DRM_ERROR("invalid hfc cfg exp h %d exp w %d act h %d act w %d\n", DRM_ERROR("invalid hfc cfg exp h %d exp w %d act h %d act w %d\n",
h, w, hw_cfg->skip_blend_plane_h, hw_cfg->skip_blend_plane_w); h, w, hw_cfg->skip_blend_plane_h, hw_cfg->skip_blend_plane_w);