Merge "disp: msm: sde: update uidle wd timer load value and fal1 threshold"
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@@ -149,7 +149,7 @@
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#define SDE_UIDLE_FAL10_EXIT_DANGER 4
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#define SDE_UIDLE_FAL10_DANGER 6
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#define SDE_UIDLE_FAL10_TARGET_IDLE 50
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#define SDE_UIDLE_FAL1_TARGET_IDLE 10
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#define SDE_UIDLE_FAL1_TARGET_IDLE 40
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#define SDE_UIDLE_FAL10_THRESHOLD_60 12
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#define SDE_UIDLE_FAL10_THRESHOLD_90 13
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#define SDE_UIDLE_MAX_DWNSCALE 1500
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@@ -23,7 +23,7 @@ struct sde_hw_uidle;
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#define SDE_UIDLE_WD_GRANULARITY 1
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#define SDE_UIDLE_WD_HEART_BEAT 0
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#define SDE_UIDLE_WD_LOAD_VAL 12
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#define SDE_UIDLE_WD_LOAD_VAL 18
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struct sde_uidle_ctl_cfg {
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u32 fal10_exit_cnt;
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@@ -2861,6 +2861,7 @@ static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
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{
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struct sde_hw_pipe_uidle_cfg cfg;
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struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
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u32 fal1_threshold_max = 15;
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u32 line_time = sde_get_linetime(&crtc->mode,
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sde_crtc->src_bpp, sde_crtc->target_bpp); /* nS */
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@@ -2876,8 +2877,9 @@ static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
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cfg.enable = _sde_plane_allow_uidle(psde, src, dst);
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cfg.fal10_threshold = fal10_threshold;
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cfg.fal10_exit_threshold = fal10_threshold + 2;
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cfg.fal1_threshold = 1 +
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(fal1_target_idle_time_ns*1000/line_time*2)/1000;
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cfg.fal1_threshold = min(1 +
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(fal1_target_idle_time_ns*1000/line_time*2)/1000,
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fal1_threshold_max);
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cfg.fal_allowed_threshold = fal10_threshold +
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(fal10_target_idle_time_ns*1000/line_time*2)/1000;
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} else {
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